JPH01146431A - Radio receiver - Google Patents

Abstract

PURPOSE:To simultaneously set the frequency to a frequency for disaster communication or the like regulated newly in the FGMDSS by using the 2nd setting means so as to set the reception frequency to the 2nd frequency for disaster communication, emergency communication or safety communication when the 2nd frequency setting key is depressed after the 1st frequency setting key is depressed. CONSTITUTION:As the frequency for disaster communication defined by the article 52 of the radio wave law, 500kHz is assigned for telegram and 2182kHz is allocated in case of telephone communication. The reception frequency for a future disaster safety system is set to the frequency for disaster communication regulated by the FGMDSS by depressing the 500kHz setting key 212 or 2182kHz setting key and then depressing an UP-key 219 or DOWN-key 217. Simultaneously, the form of radio wave and the reception band width are set those corresponding to the frequency for disaster communication regulated in the FGMDSS. Thus, the reception frequency is set instantly to the frequency for disaster communication regulated in the FGMDSS with a simple operation.

Description

[Detailed description of the invention] [Industrial application fields] TECHNICAL FIELD The present invention relates to radio receivers.

[Prior Technology J] Currently, in the Radio Station Operation Regulations, an ordinance of the Ministry of Posts and Telecommunications, frequencies for ship stations or coast stations for distress communications, emergency communications, and safety communications (hereinafter referred to as distress communications, etc.) as defined in Article 52 of the Radio Law are 500 kHz is assigned to telegraph and 2182 kHz is assigned to telephone. Therefore, in conventional marine communication radio receivers, in order to be able to immediately set the receiving frequency to the above-mentioned emergency communication frequency in an emergency, the front panel of the radio receiver has a setting for setting the above-mentioned frequency for distress communication, etc. A dedicated key is provided.

[Problems to be solved by the invention] Currently, the International Maritime Organization (hereinafter referred to as IMO) is developing FGMD SS, which is a future distress and safety system.
(Future G 1obal Mari'ti
me Destress and 5afety Sys
According to the progress report of the IMO's 30th Radio Communications Subcommittee, the above-mentioned FGM
In the DSS terrestrial communication medium-wave medium-distance service, the emergency communication frequency in the 2MHz band below is used for the following communications: from ship to land, from ship to ship, and from land to ship. is being considered.

(1) 2187.5kHz--Distress alert and safety call communication using dental selective call DSC (2)
2182kHz...Distress communication and safety communication by wireless telephone (3) 2174, 5kHz...Radio telex (
Distress communication and safety communication by NBDP) Frequencies around 500kHz are also used for emergency communications from land to ships, and specifically, there is a possibility of using a 490kHz broadcasting service system for ships for emergency communications. There is a frequency of 518kHz,
Its use for transmitting navigational and weather warnings using the NAVTEX system is being considered and is already being implemented in some areas. Therefore, the frequency for distress communications, etc. used in PGMDSS is the current frequency for distress communications, etc., 500kHz, as mentioned above.
z and 2182kHz.

For example, the reception frequency and radio wave format are stored in a storage device in advance and preset, and the reception frequency is immediately set to the above-mentioned preset frequency by pressing a specified channel key or inputting a channel number using a numeric keypad. In a wireless receiver with a preset function, the receiving frequency can be immediately set to the new emergency communication frequency being considered by the IMO by presetting the new emergency communication frequency.

However, in a wireless receiver without a preset function, there is a problem in that the receiving frequency cannot be immediately set to the newly established frequency for distress communications, etc. in the above-mentioned F'GMDSS.

The purpose of the present invention is to solve the above problems and change the reception frequency by
It is an object of the present invention to provide a radio receiver that can immediately change and set a frequency for distress communications, etc., from a currently set frequency for distress communications, etc. to a newly established frequency for distress communications, etc., which is close to the frequency.

[Means for Solving the Problems] The present invention provides a first frequency setting key and the above-mentioned first frequency setting key. a second frequency setting key; a second frequency setting key; a second setting means for setting the receiving frequency to a second frequency for distress communication, emergency communication or safety communication when the second frequency setting key is pressed after the first frequency setting key is pressed; It is characterized by having

1 Effect 1 With the above configuration, for example, the first frequency is set to 500, which is a frequency for distress communication, emergency communication, or safety communication.
kHz or 2182kHz, and the second frequency is
Newly established in FGMDSS, the above 500kl
(z or a frequency close to 2182 kl-1z. This causes the first frequency setting key to be pressed and the receiving frequency to be set to 500 kI (z or 2182 kHz), and then the second frequency setting key is pressed. At this time, the second setting means sets the reception frequency to the second frequency for distress communication, emergency communication, or safety communication.

Therefore, the receiving frequency should be changed from the currently set frequency for distress communication, etc. to the above-mentioned new F GMD.
It is possible to immediately change and set the frequency for distress communication, etc. established by the SS.

[Embodiment] FIGS. 1 to 6 show an embodiment of the present invention in which the receiving frequency is 0. 1 is a block diagram of an IMHz to 40MHz wireless receiver; FIG.

The wireless receiver of this embodiment has the following features.

(1) Data regarding each rotation of the multi-knob 22, tuning knob 23, high-frequency gain knob (hereinafter referred to as RF gain knob) 24, and volume knob 25, as well as each data regarding the pressed keys 21, are stored in the central processing unit (hereinafter referred to as C
It is called PU. ) 10 and in response, CP
Ul0 outputs each of the above data to parallel input/output port I6. At this time, the parallel input/output port 16 sends the serial data Sr including each of the above data to the PLL control circuit 28.
, the signal control circuit 29, and the filter control circuit 30. Here, the serial data Sl includes reception designation data that designates each circuit 28, 29.30 to receive the data, and each circuit 28, 29.30 receives specific reception designation data assigned in advance to each circuit. The received data is latched and predetermined processing is performed only when the data is received.

(2) With the configuration in (1) above, it is possible to adjust the passband shift, impedance matching with the antenna, LED I9 on the front panel, and signal level meter (
Hereinafter referred to as S meter. ) Adjustment of illuminance of lighting for 68,
Adjustment of the threshold level to start blanking by the noise blanker gate 46, adjustment of the center frequency of the passband of the notch filter 52, adjustment of the signal level to stop each operation during seek, scan, and sweep to scan the reception frequency. , and the signal level of the line output for outputting the demodulated low frequency signal to an external device can be adjusted using one multi-knob 22.

(3) With the configuration of (1) above, keys 211 and 212 are provided for setting the receiving frequency of the radio receiver to frequencies for distress communication, etc. when using telegraph and telephone, respectively, and the key When pressing up key 219 after pressing 211 and 212, the reception frequency is 5.
18kHz and radio wave type frequency shift keying (hereinafter referred to as
It's called FSK. ), the bandwidth of a bandpass filter used to pass only the desired signal around the reception frequency (hereinafter referred to as reception bandwidth).

) IkHz, as well as receiving frequency 2187.5kHz2
It can also be set to receive a digital cell call signal, which is a radio wave type FSK, with a reception bandwidth of 1 kHz. Also,
When the keys 211 and 212 are pressed and the down key 217 is pressed, the reception frequency of the broadcasting service signal is 490kHz and the radio wave type is FSK, and the reception bandwidth is 1k.
Hz, and the reception frequency is 2174.5kHz and the radio wave type FSK is a telex signal with a reception bandwidth of 1kHz.
You can set it to receive on z.

In FIG. 1, the radio signal received by the antenna 31 is connected to the common side of the switch 3 via the antenna terminal 32, the a side of the switch Kl, and the a side of the switch 2. The b side of switch Kl is connected to the b side of switch 2 via an attenuator 33.

Here, the switches K1 and K2 are switched by the filter control circuit 30 in conjunction with each other.

The a side of switch 3 is connected to the a side of switch 8 via a band pass filter (hereinafter referred to as BPF) Bll that passes only signals of 23 to 40 MHz.

The b side of switch 3 is connected to the common side of switch 4. The a side of the switch 4 is connected to the a side of the switch 7 via an impedance matching circuit 34 for matching the output impedance of the antenna 31 to the input impedance of the LPF 36 of the high frequency amplification section of the wireless receiver.

The impedance matching circuit 34 is, for example,
10 inductors connected in series between the input and output terminals of 4, and 10 inductors connected in parallel with each of the above inductors.
and a capacitor connected between the output terminal of the circuit 34 and ground. Each switch in the impedance matching circuit 34 receives serial data S
It is turned on or off by a control drive circuit 35 operating in response to matching setting data included in the circuit 34, thereby changing the inductance value of the circuit 34 and performing the impedance matching operation.

1 by interlocking switches 5 and 6.
One BPF' Any one BPF from Bl to BIO is connected between the common side of the switch 5 and the common side of the switch 6. Bl is a BPF that passes only signals of 0.1 to 0.3 MHz, B2 is a BPF that passes only signals of 0.3 to 0.53 MHz, and B3 only passes signals of 0.53 to 1.6 MHz. It is a BPF' that passes through. Also, B4 is 1.6 to 2.
It is a BPF' that only passes 4MHz signals, and B5
B allows only 2.4 to 3.6 MHz signals to pass through
B6 is a BPF that passes only signals of 3.6 to 5°4 MHz. Furthermore, B7 is a BPF that only passes signals of 5.4 to 8 MHz;
8 is a BPF that only passes signals of 8 to 12 MHz.
B9 is a BPF that passes only signals of I2 to 18 MHz, and BIO is a BPF that passes only signals of 18 to 23 MHz.

The common side of switch 6 is connected to the b side of switch 7, the common side of switch 7 is connected to the b side of switch 8, and the common side of switch 8 is connected to the high frequency amplification section of this radio receiver. Low pass filter (hereinafter referred to as LPF) 3
It is connected to the input terminal of 6. 3 and 8 on the above switch,
Switches 4 and 7 and switches 5 and 6 are respectively switched by the filter control circuit 30 in conjunction with each other.

The signal input to the LPF 36 is passed through the high frequency amplifier 37 to the first
input to mixer 38. On the other hand, the first rear oscillator 100
Frequency output from 80°555 to 120.45
The first local oscillation signal of 5 MHz is input to the first mixer 38 via the buffer amplifier 39. The first mixer 38 multiplies the input received signal and the first local oscillation signal, extracts a first intermediate frequency signal, and transmits the first intermediate frequency signal to the post-amplifier 40 and the intermediate frequency amplifier 4. It is output to the second mixer 42 via (2). Here, the gain of the intermediate amplifier 4I is determined by automatic gain adjustment control (hereinafter referred to as
It's called AGC. ) controlled by DC voltage. on the other hand,
Frequency 80MHz output from second local oscillator 120
The second local oscillation signal is input to the second mixer 42 via the buffer amplifier 43.

The second mixer 42 multiplies the input first intermediate frequency signal and the second local oscillation signal, extracts the second intermediate frequency signal, and transmits the second intermediate frequency signal to the post amplifier 44 and the buffer amplifier. 45. The signal output from the post-amplifier 44 is output to the common side of the switch 8 via a noise blanker gate 46 that switches whether or not to pass the input signal and an intermediate frequency amplifier 48. On the other hand, the buffer amplifier 45
extracts the noise component from the input signal, amplifies it, and then outputs it to the noise blanker control circuit 47.

The noise blanker control circuit 47 switches the noise blanker gate 46 from on to off when the noise signal input from the buffer amplifier 45 exceeds the noise blanker threshold level data value NBV input from the signal control circuit 29. .

The switches 9 and KIO are switched by the signal control circuit 29 in conjunction with each other, so that one of the four reception bandwidth selection BPFs B21 to B24 is selected.
A PF is connected between the common side of switch 9 and the common side of switch KIO.

Here, B21 is a BPF having a reception bandwidth of 6 kHz centered on the reception frequency, and similarly, B22 to B24 are 3 kHz and I kHz, respectively.

It is a BPF with a reception bandwidth of 0.2kHz.

The second intermediate frequency signal output from the common side of the switch KIO is input to the third mixer 50 via the intermediate frequency amplifier 49. 380 output from the third local oscillator 130
The third local oscillation signal of kHz±3kHz is sent to the buffer amplifier 5.
It is input to the third mixer 50 via I. Third mixer 5
0 multiplies the input second intermediate frequency signal by the third local oscillation signal, extracts the third intermediate frequency signal, and then outputs it to the common side of the switch K11. Here, the intermediate frequency amplifier 4
The gain of 9 is controlled by the AGC DC voltage output from the DC amplifier 7I.

The a side of switch Kll is connected to the a side of switch KI2, and the b side of switch Kll is connected to the b side of switch KI2 via a notch filter 52 having a predetermined passband width. Here, the switches Kll and KI2 are switched by the signal control circuit 29 in conjunction with each other. The third intermediate frequency signal output from the common side of switch KI2 is
The signal is inputted via an intermediate frequency amplifier 53 to a buffer amplifier 54, a buffer amplifier 56, and an AGC detector 58. Here, the gain of the intermediate frequency amplifier 53 is controlled by the AGC DC voltage output from the DC amplifier 71.

The third intermediate frequency signal output from the buffer amplifier 54 is a single sideband amplitude modulation signal (hereinafter referred to as SSB) demodulator 5
5 and is outputted to the a side of the switch K13 via the preamplifier 60. Further, the third intermediate frequency signal output from the buffer amplifier 56 is a double sideband amplitude modulation signal (hereinafter referred to as DS
It's called B. ) is outputted to the b side of the switch KI3 via the demodulator 57 and preamplifier 61. On the other hand, the fourth local oscillator 140 outputs a frequency of 75kHz±6kHz.
The local oscillation signal is a beat frequency oscillation signal (hereinafter referred to as BFO).
It's called a signal. ), SSB via buffer amplifier 72
It is output to the return Fm55.

The switch KI3 is switched by the signal control circuit 29, and the demodulated low frequency signal output from the common side of the switch 13 is output to the speaker 64 via the low frequency volume controller 62 and the low frequency amplifier 63. , is outputted to the line output terminal 67 and the a side of the switch KI4 via the low frequency volume controller 65 and the low frequency amplifier 66. Here, the low frequency volume controllers 62 and 65 control the speaker output volume control data A output from the signal control circuit 29.
The amount of attenuation of each adjuster is controlled in response to FV and line output volume control data LINEG.

Further, the low frequency signal outputted from the common side of the switch KI3 is outputted to the AGC control circuit 59 via the AGC detector 69. The AGC detector 58 performs envelope detection on the input signal and outputs the detection output to the AGC control circuit 59.

The AGC control circuit 59 controls on/off of the AGC output from the signal control circuit 29 and performs high-speed (FAST) control of the AGC.
) and AGC control signals including low speed (SLOW) control,
Also, in response to the high frequency gain control data RFC, the AG
The detection output input from the C detector 56 and the AGC detector 6
From the detection output input from 9, an AGC DC voltage for gain control of the first intermediate frequency signal and an AGC DC voltage for gain control of the second and third intermediate frequency signals are generated, and each signal is converted into a DC voltage. Output to amplifiers 70 and 71.

Here, the AGC control circuit 59 controls the intermediate frequency amplifier 4! in proportion to the value of the input high frequency gain control data RFC.
A output to the DC amplifier 70 so that the gain of
Controls GC DC voltage. Further, the AGC control circuit 59 generates a level signal indicating the average level of the received signal from the detection output input from the AGC detector 58, and outputs the level signal to the inverting input terminal of the comparator 74.
It is output to the S meter 68 via the b side of the switch KI4. Here, the switch 14 is switched by the signal control circuit 29.

The scanning stop threshold data 5CANV output from the signal control circuit 29 is converted into digital/analog conversion (hereinafter referred to as D/A).
This is called A conversion. ) After being D/A converted in the device 75,
It is input to the non-inverting input terminal of comparator 74. Comparator 74
When the level signal input to the inverting input terminal exceeds the level of the threshold data 5CANV input to the non-inverting input terminal, the scan stop signal 5TOP goes to L level.
is output to the parallel input/output port I6.

Next, the configurations of the first to fourth local oscillators 100, 120, 130, and 140 will be explained with reference to FIGS. 3 and 4.

In FIG. 3, the reference oscillator 10! is 10°24 M
A Hz signal is generated and the reference signal is passed through a phase-locked loop circuit (hereinafter referred to as PLL) 1102, PLLII[1
31, PL, LIV141, and output to the mixer 111, as well as PLLl11 via the 115 frequency divider 103.
Output to 04.

The PLL 1102 has a frequency multiplication ratio of 16 based on data N 1 and A I input from the PL and L control circuit 28.
A signal obtained by frequency-dividing the signal inputted from the prescaler 107 having a prescaler 107 having an I/I7 and an inputted reference signal of 10°24MHz are phase-detected, and the detected output is converted into a voltage via an LPF having a predetermined cutoff frequency. Controlled oscillator (hereinafter referred to as
It's called a VCO. 105, and output as a phase control voltage. The VCO R105 outputs a first local oscillation signal of 80°555 to 120.455 MHz to the buffer amplifier 39 and the mixer 106 in response to the input phase control voltage. The mixer +06 multiplies the input first local oscillation signal and the signal input from the BPF 114, extracts a signal representing the difference in frequency between the two signals, and outputs the signal to the PLL 102 via the prescaler 107. Here, PLLlI
The frequency division ratio NTI of the entire PLL circuit by O2 and the prescaler 107 is given by the following equation.

NTI=16NI+AI...(1)
In addition, PLL1102, VCOfI05, mixer 106
, and a prescaler 107, a first local oscillation signal that changes in steps of 40 kHz is obtained.

PLLI[l 04 is data N2. Frequency multiplication ratio 12 based on A2
Phase detection is performed on a signal obtained by frequency-dividing a signal manually inputted from a prescaler 109 having a frequency of 8/129 and a reference signal frequency-divided by 115, and the detection output is sent to the VCOn 108 via an LPF having a predetermined cutoff frequency. Output as phase control voltage.

VCOn + 08 responds to the input phase control voltage and converts the 44 to 48 MHz signal into the I/100 frequency divider +
10 to the mixer I11, and the prescaler 109 to the PLLI[I04. Here, the frequency division ratio NT2 of the entire PLL circuit by PLLI[I 04 and the prescaler 109 is given by the following equation.

NT2=128N2+A2 ・・・・・・(2
) Also, by a circuit composed of PLLn104, VCOIr108, and hybrid scaler 109, IkHz
Obtain the output signal of the VCOI 1108 that changes in the steps of .

The mixer 111 receives the signal input from the frequency divider +10,
After multiplying by the 10.24 MHz reference signal and extracting the signal of each frequency difference between both signals, the signal is output to the mixer +13 via the BPF 112 having a passband of 1007±2'0 kHz. .

The mixer 113 receives the signal input from the BPF 112, and
The second 80MHz signal output from the second local oscillator 120
After multiplying by the local oscillation signal and extracting a signal of the difference in each frequency of both signals, the extracted signal is converted to a passing frequency of 69.2.
Output to mixer 106 via BPF II 4 having a frequency of 8 to 69.32 MHz.

The second local oscillator 120 generates a second local oscillation signal of 80 MHz and outputs it to the mixer 113 and the buffer amplifier 43.

In FIG. 4, the IO output from the reference oscillator 101
, 24 MHz reference signals are input to PL, LIII I31 and PLLIVI41.

PLLl 131 receives data N3. input from PLL control circuit 28. Phase detection is performed on a signal obtained by dividing the signal input from the prescaler 133 having a frequency multiplication ratio of 16/+7 based on A3 and the input reference signal, and the detected output is passed through an LPF having a predetermined cutoff frequency. It is output as a phase control voltage to VCOI[I 132 through the VCOI[I 132]. VCOIII 132 responds to the input phase control voltage and converts the 76MHz±0.6MHz signal to 1/100
It is output as a signal of 380 KHz±3 kHz to the buffer amplifier 51 via the frequency divider 134 and the I/2 frequency divider 135, and is output to the buffer amplifier 51 as a signal of 380 KHz±3 kHz via the prescaler 133. TePLL11
Output to 1131. Here, the frequency division ratio N T of the entire PLL circuit by PLLr[[131 and prescaler 133
3 is given by the following equation.

NT3=16N3+A3 ・・・・・・(3)
Also, PLLIII I 31. VCOI 132,
and a circuit consisting of prescaler +33,
It is possible to obtain the output signal of VCOI[I 132 that changes in steps of 5 kHz, and therefore to obtain a signal in steps of 25 Hz as the third local oscillation signal.

PLLIVI41 receives data N4. input from PLI and control circuit 28. Frequency multiplication ratio 16/1 based on A4
The signal obtained by frequency-dividing the signal input from the prescaler 143 having a prescaler 143 having a frequency of 7 and the input reference signal is phase-detected, and the detection output is passed through an LPF having a predetermined cutoff frequency to the VCOIVI 42 as a phase control voltage. Output. VCOIV I42 responds to the input phase control voltage and sends a 75MHz±6MHz signal to buffer amplifier 7 via I/100 frequency divider 144 and 1/IO frequency divider 145.
2, it is output as a signal of 75 MHz±6 kHz, and the PLLIV 141 is output via the prescaler 143. The frequency divider 145 is enabled and outputs the fourth local oscillation signal when the H-level BFO signal output from the PLL control circuit 28 is input;
When the BFO signal at L level is input, it is disabled and stops outputting the fourth local oscillation signal. Here, the frequency division ratio NT4 of the entire PI and L circuit based on the PLLIVI41 and the prescaler I43f is given by the following equation.

NT4=16N4+A4 (4) Also, PLLIV141. The circuit composed of the VCOIV 142 and the prescaler 143 makes it possible to obtain an output signal of the VCOIV 142 that changes in steps of 5 kHz, and therefore it is possible to obtain a signal in steps of 5 Hz as the fourth local oscillation signal.

In FIG. 5, CPU10 is a control circuit that controls the entire wireless receiver, receives a clock for CPU operation of a predetermined frequency from a clock generator 11, and operates in response to the clock.

The CPU 10 has a read-only memory (hereinafter referred to as R
It's called OM. ) 14, the power source is backed up by battery B, and any 400
A RAM 15 is connected that stores the channel reception frequency, the emergency communication reception frequency, and setting data for each reception frequency, and is used as a CPU IQ work area.

Furthermore, parallel input/output ports 16 and I7 are connected to CPU10 via address bus I2 and data bus 13. The parallel input/output boat 16 outputs a clock SCK and serial data S in response to an instruction from CPU10.
RF gain knob 24 and volume knob 25 which are input from an analog/digital converter (hereinafter referred to as A/D converter) 26 while transmitting r and latch signal RCK.
Setting data corresponding to the rotational position of is transferred to CPU10. Further, when the parallel input/output boat 16 receives the scanning stop signal 5TOP output from the comparator 74 in FIG. 2, it transfers the signal 5TOP to the CPU 1O. Here, each of the DC voltage output circuits of the RF gain knob 24 and the volume knob 25 outputs a predetermined DC voltage to the A/D converter 26 according to the rotational position of the knob 24, 25. In response, the A/D converter 26 converts the input DC voltage into 6-bit setting data for the knobs 24 and 25, and outputs the data to the parallel input/output port I6.

The parallel input/output port I7 takes in setting data by pressing various keys 21 on the front panel of the wireless receiver shown in FIG. 7, outputs the setting data onto the data bus 13, and displays various displays on the front panel. Data for driving the light emitting diode (hereinafter referred to as LED) is outputted to the LED 19 via the latch and the LED drive circuit I8. The scan circuit 20 is enabled, and in response, the enabled key scan circuit 20' scans each key of the keys 21, and the data of the pressed key is transferred to the parallel input/output port 17 and the data bus!3. As a result, data indicating whether key 2■ has been pressed is output to CPUl0
It is taken into 0.

Further, an encoder counter 18 is connected to the CPU10 via a data bus 13. The encoder counter 18 is connected to the output terminal of the pulse output circuit of the multi-knob 22 and the output terminal of the pulse output circuit of the tuning knob 23, and when the multi-knob 22 or the tuning knob 23 is rotated, a pulse is output depending on the direction of rotation. The phases are different and pulses are output to the encoder counter I8 only during rotation. The encoder counter 18 is a multi-knob 22 or a tuning knob 23.
When a pulse is input from the pulse output circuit of
The identification data of the tuning knob 23 is outputted to the CPU 10 via the data bus 13. When CPU10 receives the interrupt signal IRQ, it receives the pulse data and identification data from the encoder counter 18.

The parallel output port 16 outputs the serial data Sl together with the clock SCK to the PLL control circuit 28, the signal control circuit 29, and the filter control circuit 30 when transmitting each data to be described in detail later, and then outputs the latch signal RCK. . The serial data SI includes 8-bit reception designation data indicating a shift register group in the control circuits 28, 29.30 to be received, which will be described in detail later, and a number of bits that differs depending on the control circuits 2g, 29.30 to be received. It has 19 bits, 24 bits, or 16 bits of setting data. The format of this serial data Sl will be described in detail later with reference to FIG.

As shown in FIG.
D201a to 201k, and an EDI9 is provided at the upper center of the front panel of the radio receiver. Also,
A tuning knob 23 and a multi-knob 22 are rotatably provided at the center and right side of the front panel of the radio receiver, respectively, and an RF gain knob 24 and a volume knob 25 are rotatably provided at the front panel to the left of the tuning knob 23. juxtaposed.

The key 2I provided on the front panel of the wireless receiver is the seventh
It has many keys as shown in the figure. That is, 202
a to 202r are radio wave types USB, LSB (hereinafter referred to as
SSB using the lower sideband is called LSB. ), telegraph (C
W), FSK, facsimile (FAX), and DSB, and are keys 203a to 2
03d is 6kHz, 3kHz, 1kHz, and 0.2k to pass the desired signal around the receiving frequency
This is a key for specifying the reception bandwidth in Hz.

204a to 204e, and 2053 to 205
c, 20B are keys that can perform predetermined adjustments, which will be described in detail later, using the multi-knob 22.

204a becomes a passband shift key when a radio wave type other than telegraph (CW) is selected, and becomes a BFO key when telegraph (CW) is selected as a radio wave type. Here, passband shifting refers to pseudo-shifting the passing center frequency of a bandpass filter for intermediate frequency signals that determines the selectivity characteristics of a wireless receiver, thereby making it possible to eliminate interference. . When the passband shift key 204a is pressed when a radio wave type other than telegraph (CW) is selected, the shift 1 of the passband shift can be changed by rotating the multi-knob 22. In this embodiment, the above path is changed by changing the setting data A1 or N1 and the setting data A4 or N4 so that the frequency of the first local oscillation signal and the frequency of the fourth local oscillation signal are respectively shifted by the same frequency. Achieves band shift.

On the other hand, when the key 204a is pressed when telegraph (CW) is selected as the radio wave type, the tone of the telegraph output from the speaker 64 can be adjusted by rotating the multi-knob 22. In this example,
The tone of the telegram is changed by changing the setting data A4 or N4 so that the frequency of the fourth local oscillation signal changes.

204b is a filter key, and the filter key 204
When b is pressed, switches K 3 and K 8 are switched to the b side, and the switch 4. 7 is switched to the a side, and the antenna 3I and the LPF 3 of the high frequency amplification section
An impedance matching circuit 34 is connected between 6 and 6. Here, by rotating the multi-knob 22, the matching setting data can be changed. 204c is a day marquee, and by pressing down the day marquee 2040 and rotating the multi-knob 22, the illuminance of the LED I 9 and the illuminance of the S meter 68 illumination (not shown) can be controlled. 204d is a noise blanker key. When the noise blanker key 204d is pressed, the noise blanker control circuit 47 is enabled, and by rotating the multi-knob 22, the level of the noise signal to be blanked can be adjusted.

204e is a notch filter key, and when the notch filter key 204e is pressed, 11. to 1
A notch filter 52 is connected between the third mixer 50 and the intermediate frequency amplifier 53, which attenuates only specific frequency components within the reception bandwidth including the reception frequency. By rotating the multi-knob 22, the center frequency of the notch filter 52 can be shifted in a pseudo manner, thereby making it possible to remove, for example, beat interference. In this embodiment, by changing the setting data A3 or N3 and the setting data A4 or N4 so that the frequency of the third local oscillation signal and the frequency of the fourth local oscillation signal are respectively shifted by the same frequency, the above-mentioned This realizes changing the center frequency of the notch filter 52.

Note that the key 22a is a hold key, and when the hold key 22a is pressed, the pulse output circuit of the multi-knob 22 does not output pulses even if the multi-knob 22 is rotated. can be disabled and the data set by the corresponding knob 22 can be retained.

Furthermore, keys 204b, 202b, 203b, 204c
, 202c, 203c, 204d, 202d, 203d
, 202e constitute a numeric keypad, and when predetermined data is input using the numeric keypad, the key 20
3a transfers data entered using the numeric keypad to the CPU10.
Used as the enter key to transfer to.

205a is a seek key, and after pressing the seek key 2°5a, pressing the up key 2+9 or the down key 2!7 changes the receiving frequency continuously upward or downward, and then rotates the multi-knob 22 to set the received frequency. When a signal level equal to or higher than the scan stop threshold is received, the seek scan is stopped.

205b is a scan key;
When pressing b and inputting a predetermined group number in the channel registered in advance in RAM 15 using the numeric keypad, and pressing the enter key 203a, the receiving frequency will be changed between each channel in the registered group. scanned. At this time, as in the case of the seek, when a signal level equal to or higher than the scan stop threshold set by rotating the multi-knob 22 is received, the scan is stopped.

205C is a sweep key;
After pressing c and inputting the group number that combines the lower end frequency, upper end frequency, and step frequency at the time of scanning registered in advance in the RAM 15 using the numeric keypad, press the enter key 203a. The reception frequency is scanned using the specified frequency within the selected group.

At this time, as in the case of the seek and scan described above, when a signal level equal to or higher than the scan stop threshold set by rotating the multi-knob 22 is received, the scan by the sweep is stopped.

208 is a line key, and when the line key 208 is pressed, the switch 14 is switched from the b side to the a side, and the display of the S meter becomes the display of the signal level output to the line output terminal 67.

At this time, by rotating the multi-knob 22 while pressing the key 2!8, the line output volume control data LINEG can be changed, thereby making it possible to change the attenuation amount of the low frequency volume controller 65. terminal 6
The signal level of the line output output to 7 can be changed.

206a is a key for turning off AGC;
6b is a key for setting high speed (FAST) AGC, and 206C is a key for setting low speed (SLOW) AGC. Reference numeral 207 is a key for interlocking switch Kl with 2 to switch from the a side to the b side and insert the attenuator 33 into the input terminal of the radio receiver.

210 is a fine key for setting fine adjustment of tuning using the tuning knob 23; 211 is a key for setting the receiving frequency to 2182 kHz, the frequency for telephone distress communications, etc.; 2!2; is a key for setting the receiving frequency to 500 kHz, which is the frequency for distress communication, etc. for telegraph. Furthermore, 213 is a lock key for holding the set reception frequency after the reception frequency is set using the key 210 and the tuning knob 23 or the keys 211 and 212.

214 is a channel key, and after pressing the key 214 and inputting the channel number using the numeric keypad,
By pressing the enter key 203a, the receiving frequency can be set to the frequency of the input channel registered in advance in RAM+5. 215 is a frequency key, and by pressing this key, the receiving frequency is input using the numeric keypad, and then the enter key 203 is pressed.
By pressing a, you can set any frequency.

Reference numeral 216 is a memory key, which is used to set the receiving frequency using the above-mentioned operations, as well as setting the radio wave type, setting the receiving bandwidth, setting AGC, and setting whether or not to insert the attenuator 33.
Setting whether to insert the impedance matching circuit 34,
Also, after setting the matching setting data in the impedance matching circuit 34 (hereinafter, the setting data of the above seven items other than the reception frequency is referred to as preset data), press the memory key 216 and use the numeric keypad to set the matching setting data. By inputting the channel number in which the receiving frequency and the preset data are registered and pressing the enter key 203a, the receiving frequency and the preset data are stored in a predetermined address corresponding to the channel in the RAM 1S.

217 is a down key for changing the currently set channel or reception frequency to a channel with a smaller channel number or a lower frequency. Reference numeral 218 is a function key for performing a predetermined additional function when setting a channel or reception frequency or setting matching setting data in the impedance matching section 3. 21
9 is an up key for changing the currently set channel or reception frequency to a channel with a larger channel number or a higher frequency.

In FIG. 6, the clock SCK output from the parallel input/output port I6 is connected to the SCK terminal of the Toshiba Electric Corporation TC74HC595P 8-bit shift register integrated circuit UIO in the PLL control circuit 28 and the Motorola MC
4 serial manual PLL frequency synthesizer integrated circuits U11 to U1.4 each CLOC of type I45156P
It is input to the K terminal and also to the RCK terminal of the integrated circuit UIO via the inverter INVI. Here, each of the integrated circuits Ull to UI4 includes a 7-bit shift register, a 10-bit shift register, and a 2-bit shift register, and has a total of 19-bit shift registers. The clock SCK is also input to each SCK terminal of seven shift register integrated circuits U20 to 026 of the TC74H (, 595P type) in the signal control circuit 29, and the clock SCK
SCK terminal of C595P type shift register integrated circuit U30 and Mitsubishi Electric (manufactured by Mitsubishi Electric) in filter control circuit 30
It is input to each clock input terminal T of four 8-bit shift register integrated circuits U31 to U34 of the M54975P type. The clock SCK is input to the RCK of the integrated circuit U30 via the inverter INV2.

The eight serial data output from the parallel input/output board 16 are sent to the S■ terminal of the integrated circuit UIO, and the integrated circuit U20.
and the SI terminal of the integrated circuit U30. Furthermore, the latch signal RCK output from the parallel input/output board 16 is inputted to each first input terminal of the AND gates AND1 to AND4 in the PLL control circuit 28, and is input to the integrated circuit in the signal control circuit 29. U
It is input to the RCK terminal of No. 20. Further, the latch signal is input to the AND gate ANDll in the filter control circuit 30.
and ANDI 2 is input to each second input terminal.

In the PLL control circuit 28, the output terminals QE, QF, QG, and QH of the shift register integrated circuit U l'0 are connected to the second input terminals of the AND gates A N I) I to AND4, respectively, and QH of circuit UIO
'The data output terminal is connected to each data input terminal DATA of the shift register integrated circuits U11 to UI4. Each output terminal of AND I to A N D 4 is connected to a shift register integrated circuit Ull to U, respectively.
Connected to each ENABLE terminal of I4. integrated circuit ul
The data output terminals of l to UI4 are each connected to a PLL.
I I 02, PLLff 104, PLLllll3
1. It is also connected to each data input terminal of PLL I41 and the enable terminal of frequency divider I45.

In the two signal control circuits, the shift register integrated circuit U
The 20 QC output terminals are connected to each RCK input terminal of integrated circuits U24 to U26, and the QD output terminal of integrated circuit tJ20 is connected to each RCK input terminal of integrated circuits 02+ to U23. The QH' output terminal of integrated circuit 020 is connected to each ST terminal of integrated circuits U2+ and U24. The QH' output terminal of integrated circuit U21 is connected to Sl of integrated circuit U22.
The QH' output terminal of integrated circuit U22 is connected to the Sl input terminal of integrated circuit U23. The QH' output terminal of integrated circuit U24 is connected to the Sl input terminal of integrated circuit U25, and the QH' output terminal of integrated circuit U25 is connected to the Sl input terminal of integrated circuit U26.

In the filter control circuit 30, the QA of the integrated circuit U30
The output terminal is connected to a first input terminal of AND gate AND+2, and the QB output terminal of integrated circuit U30 is connected to a first input terminal of AND gate ANDI+. The output terminal of the AND gate AND II is connected to each LATC1 terminal of the integrated circuits U31 and U32, and the output terminal of the AND gate AND+2 is connected to each LATCH terminal of the integrated circuits U33 and U34. QH of integrated circuit U30
'The output terminal is connected to each SIN input terminal of integrated circuits U31 and U33, the 5OUT output terminal of integrated circuit U31 is connected to the SIN input terminal of integrated circuit U32, and the 5OUT output terminal of integrated circuit U33 is connected to the SIN input terminal of integrated circuit U34. Connected to the input terminal. The QA and QC or QG output terminals of the integrated circuit 031 and the QA or QF and QG output terminals of the integrated circuit U32 are connected to a switching control circuit SC which switches the switches K1 to 8. QD or QH output terminal of integrated circuit U33 and integrated circuit U3
The QD or QH output terminals of No. 4 are connected to the data input terminal of the control drive circuit 35.

The above shift register integrated circuit UIO1U20 to U2
6 and 030, as is well known, after reading the data manually input from the S terminal into the internal shift register at the rising edge of the clock SCK, latching the read data at the rising edge of the latch signal RCK and outputting it to the output terminal QA or QA. Q Output to I-T and QH'. The above integrated circuit U
11 to U14, as is well known, read the data input from the DATA terminal into the internal shift register at the rising edge of the Cr, OCK terminal, and then the latch signal input to the ENABLE terminal reaches the ■] level. The data read when the logic level is the same is latched and output to the data output terminal.

As is well known, the shift register integrated circuits U'31 to U3-1 read the data manually input from the SIN terminal into the internal shift register at the rising edge of the clock input to the T terminal, and then input the data to the LATcH terminal. When the latch signal is at H level (logic level "BI"), the read data is latched and output to the OA or QH output terminal.

As shown in FIG. 8, the normal data Sr is transmitted to one or more shift registers (hereinafter referred to as
This is called a shift register group. ), 8-bit reception designation data bl to b8, and 19-bit, 24-bit
It consists of setting data of bits or 16 bits (b9 onwards), and is transmitted to each circuit 28, 29, 30 by the parallel input/output port 16 starting from the bit with the larger bit number. Note that in FIG. 8, "-" indicates an empty bit.

In the PLL control circuit 28, the serial data St input to the Sl input terminal of the integrated circuit UIO is transmitted to the integrated circuit UIO.
It is input to each data input terminal DATA of the integrated circuits U11 to UI4 via the QH' output terminal of IO. The integrated circuit UIO receives 8 pieces of reception designation data bl to b8.
This is a shift register for latching. Further, the four integrated circuits Ull to UI4 include shift registers for receiving the 19-bit setting data, and each of the integrated circuits U11 to UI4 independently constitutes the shift register groups G1 to G4. A to D in FIG. 8 are integrated circuit UIO and integrated circuit U, respectively.
Shift register group G corresponding to ll to U14
8 is a format diagram showing data to be received by G4, and the serial data of each A to D in FIG.
It consists of bit reception designation data bl to b8 and 19-bit setting data b9 to b27.

In A and B of FIG. 8, AI, Nl, A2 and N2
are respectively 7 bits, 10 bits, 7 bits, and 10 bits of setting data for changing the frequency of the first local oscillation signal, and data AI and Nl are the setting data of the integrated circuit U.
ll to PLL I 102, and data A2.
N2 is output from integrated circuit U12 to PLLII I04. In C of FIG. 8, A3 and N3 are respectively 7-bit and 10-bit setting data for changing the frequency of the third local oscillation signal, and data A3°N3 is output from the integrated circuit UI3 to the PLLllll31. Ru. In D of FIG. 8, A4 and N4 are each
These are 7-bit and 10-bit setting data for changing the frequency of the fourth local oscillation signal, and data A4. N
4 is output from the integrated circuit UI4 to the PLLIV141. Bit b27 of D in FIG. 8 is a bit that controls whether or not the frequency divider 145 is enabled.

In the signal control circuit 29, an integrated circuit U20 is a shift register for latching 8-bit reception designation data. Furthermore, each of the three integrated circuits U21 to U23 and U24 to U26 is connected to a shift register group G5. G
6.

E and F in FIG. 8 are shift register groups G, respectively.
8 is a format diagram showing the data to be received by G6, and the serial data SI of each E and F in FIG.
It consists of 8-bit reception designation data bt to b8 and 24-bit setting data b9 to b32. Here, the 8-bit setting data b9 to b16 of E and F in FIG. 8 are latched by the integrated circuits U21 and U24, and the 8-bit setting data b17 to b24 are latched by the integrated circuit U22.
．． The 8-bit setting data b25 to b32 latched by U25 are sent to the integrated circuit U23. It is latched by U26.

In E of FIG. 8, b15 and b16 are the S meter 6
This is control data for switching the switch 14 to the a side or the b side for switching the output signal to the 8, and b17 to b22 are 6-bit line output volume control data LIN.
It is EG. In addition, in E of FIG. 8, b25 to b30 are 6-bit speaker output volume control data AFV.
, and b31° and b32 convert the output of the SSB demodulator 55 or DSB demodulator 57 into the low frequency sound ff1Pi moderator 6
This is control data for switching the switch KI3 to the a side or the b side in order to switch to the a side or the b side to output the signal. In F of FIG. 8, b9 to b12 are 4-bit scan stop threshold data 5CANV, and b14 is switch Kl.
This is control data for switching whether or not to insert the switching notch filter 52 on the a side or the b side by interlocking the notch filters 1 and 12. In addition, in F of FIG. 8, b15 and b16 are AGC off and AGO high speed (FA
b17 to b22 are 6-bit high frequency gain control data RPC. Furthermore, in F of FIG. 8, b25 to b28
9 and KI are used as switches for switching the reception bandwidth.
This is control data for switching O, and b29 to b32 are 4-bit noise blanker control threshold data NBV.

In the filter control circuit 30, the integrated circuit U3.0 is 8
This is a shift register for latching bit reception designation data. In addition, two integrated circuits 031 and U32 each
, and shift register group G for latching 6-bit setting data in 033 and U34, respectively.
7. Configure G8. G and H in FIG. 8 are respectively shift register loops G7. This is a format diagram showing data to be received by G8, and each G and H serial data in FIG. 8 is 8-bit reception designation data bl to b8.
and 16-bit setting data b9 to b24. Here, the 8-bit setting data b9 to bl6 of G and H in FIG. 8 are stored in the integrated circuit U31. U33 latches the 8-bit setting data b17 to b24 to the integrated circuit U32. It is latched by U34.

In G in Figure 8, b9 is a switch! and 2 are interlocked to switch whether or not to insert the attenuator 33. bll to bl5 and bl7 to b22 are control data for switching 3 to 8 to the switch to switch whether or not to insert the attenuator 33. any one B
This is control data for inserting the PF, and b23 is control data for switching the switch from 3 to 8 to switch whether or not to insert the impedance matching circuit 34. Moreover, in H of FIG. 8, bl2 to bl
6 and b20 to b24 are matching setting data for setting the inductance value by switching 10 switches in the impedance matching circuit 34.

Regarding the operation of the radio receiver configured as described above, in particular, the parallel input/output port 16, the PLL control circuit 28,
The operation of serial data transmission between the signal control circuit 29 and the filter control circuit 30 will be explained.

For example, when the operator rotates the tuning knob 23 to change the reception frequency, a predetermined pulse is output from the pulse output circuit of the tuning knob 23 in FIG. 5 to the encoder counter I8, and in response, the encoder counter 18 The interrupt signal IRQ is output to the CPU 10, and the data regarding the pulse is sent to the CPU 10 via the data bus 13.
Output to. At this time, the CPU 10 calculates the reception frequency corresponding to the rotation of the tuning knob 23 from the current reception frequency data stored in the RAM 15 and the input data, and calculates the reception frequency corresponding to the calculated reception frequency. After calculating the setting data AI to A3 and N1 to N3, the data is output to the parallel input/output port 16.

In response to this, the parallel input/output port I6 first
Together with the 7-bit clock SCK, the 27-bit serial data Sr including the setting data AI and N1 is sent in the order of b27...bl in the signal format of A in Fig. 8, and then is transmitted with one H-level pulse. A certain latch signal RC
Send K. On the other hand, in the PLL control circuit 28, the inverted signal of the clock SCK is output to the integrated circuit UIO as described above.
Since it is input to the RCK input terminal of the integrated circuit UIO, only the QH terminal of the integrated circuit UIO becomes H level at the end of sending out the serial data S2. Next, when the latch signal RCK is input to the second input terminal of the AND gate AND I, the AND gate AND 1 outputs an H level signal to the ENABLE terminal of the integrated circuit Ul 1 (1'). As a result, the 19-bit setting data input to the integrated circuit U11 corresponding to the shift register group Gl is latched, and the setting data AI and N included in the setting data are latched.
l is output to PLL 1!02. At this time, since bl to b7 of the serial data Sr are all 0'', the serial data SI input to each shift register of the other shift register groups G2 to G8 is not latched.

Next, the parallel input/output port I6, as described above,
Setting data A2 and N in the signal format of B in Figure 8.
In addition to transferring 2 to the integrated circuit U12 and latching it,
Setting data A3 and N in the signal format of C in Figure 8.
Transfer 3 to integrated circuit UI31. to latch. As a result, the configuration data A2 and N2 are transferred from the integrated circuit UI2 to the PLLlll04, and the configuration data A3 and N3 are transferred to the PLLlll04.
is transferred from the integrated circuit U13 to the PLLllll31.

The setting data AI, Nl, A2 . N2, and A3. Since N3 is set in each PLL 102, 104.131, each frequency of the first and third local oscillation signals is changed, thereby changing the reception frequency.

Also, setting data A4. When setting N4, when transmitting serial data SI in the signal format D in Figure 8, when changing the matching setting data of the impedance matching circuit 34, and when setting Even when transmitting the serial data SI in the signal format, the parallel input/output port 16 transmits the serial data Sr in the signal format A in FIG. 8 described above, and in response, each control circuit 28゜30
works similarly.

Further, for example, when the operator rotates the volume knob 25 in order to change the volume of the demodulated signal output from the speaker 64, the DC voltage output circuit of the volume knob 25 in FIG. A DC voltage of a predetermined voltage corresponding to the above is outputted to the parallel input/output port 16 via the A/D converter 26, and in response, the parallel input/output port [6 receives the A/D converted DC voltage data. 6-bit speaker output volume control data AF
Output V to CPU10. In response to this, CPUl0
is the data AFV for the parallel input/output boat 16.
to the signal control circuit 29.

Parallel input/output boat in response! 6 is first 8
After sending out the 8-bit L level serial data S2 together with the bit clock SCK, the latch signal RCK, which is one H level pulse, is sent out. This causes shift register integrated circuit U10. U20. 8 to U30
Bit data "oooooooo" is latched, and each integrated circuit U10, U20 . An L level signal with data "0" is output from each QA to QH output terminal of U30, and as a result, each of the control circuits 28, 29, 30
is reset. Next, the parallel input/output boat 16
is the 32-bit clock SCK as well as E in Figure 8.
The 32-bit serial data Sl including the above speaker output volume control data AFV in the signal format b32
. . . After sending out the signals in the order of bi, the latch signal RCK, which is one pulse at H level, is sent out. On the other hand, in the signal control circuit 29, only b4 of the reception designation data b1 to b8 is set to 'l', so at the end of sending out the above-mentioned social data Sr, only the QD terminal of the integrated circuit U20 becomes H level. , the I (level signal is integrated circuit U2
It is input to the RCK terminals 1 to U23.

As a result, the 24-bit setting data b to b32 excluding the above-mentioned reception designation data input to the integrated circuits U21 to U23 corresponding to the shift register group G5
is latched, and the speaker output volume control data AFV included in the setting data is output to the low frequency sound WdEJ moderator 62. In response to this, the low frequency sound 11 section 62 attenuates and collapses the switch K in response to the input data APV.
Attenuates the low frequency signal output from the common side of I3.

As a result, the volume of the demodulated low frequency signal output from the speaker 64 is adjusted.

Furthermore, data other than data AFV in E of FIG. 8 and each data in F of FIG. 8 are transferred in the same procedure as the above-described transfer of data AFV.

As explained above, in transmitting each setting data from the parallel input/output port I6 to each control circuit 28, 29.30, the transmitted serial data Sl is used to specify the shift register group Gl to G8 to be received. The shift register includes reception designation data bl8 and predetermined each of the above setting data, and when the reception designation data is the same as the preset own reception designation data and a latch signal is input, the shift register belongs to the corresponding shift register group. A shift register performs a latch operation. Therefore, as shown in FIG. 8, serial data Sr in multiple signal formats can be transferred to a parallel input/output board using only three data lines for transmitting clock SCK, serial data S, and latch signal RCK. 16 to desired shift register group G
It has the advantage of being able to avoid being transferred and latched to each of the shift registers 1 to G8.

Furthermore, the operation and operation when setting the reception frequency in the above-mentioned radio receiver to the current communication frequency and the above-mentioned communication frequency for ft pheasant communication etc. of the PGMDSS will be explained.

Note that the data on the radio wave formats and reception bandwidths shown in Table 1 corresponding to the communication frequencies for each of the above-mentioned distress communications, etc. are stored in advance in the ROM+4 as preset data.

(1) Frequency 2182kHz for telephone distress communications, etc.
In this case, when the 2182kHz setting key 2+1 is pressed, the CPU 10 transmits data indicating that the key 2II was pressed from the key 21 in FIG. 5 to the parallel input/output port 17 and the data bus I3 using the method described above. At this time, the CPU 10 receives the reception frequency 2182kl
(The above setting data AI to A3 and Nl corresponding to z
to N3, outputs the data to the parallel input/output port I6, reads out data regarding the radio wave format and reception bandwidth corresponding to the frequency 2182kHz stored in advance in ROM+4, and outputs the data to the parallel input/output port I6. Transfer to.

In response to this, the parallel input/output port 16 first
Together with the 7-bit clock SCK, the 27-bit serial data S■ including the setting data AI and N1 in the signal format A in FIG. 8 is PL in the order of A27...bl.
After sending the signal to the L control circuit 28, the latch signal RCK, which is one pulse at the H level, is sent to the PLL control circuit 28. Next, the parallel input/output port 16 similarly receives the setting data A2. N2. A3 and N3 are PLL control circuit 2
Send on 8th. In response, the PLL control circuit 28 transfers the received setting data AI and Nl5A2 and N2, A3 and N3 to PL[l102, PLLff104, respectively.
, PL, L, ll1131. At this time, the first
The local oscillator 100 and the third local oscillator 130 generate first and third local oscillation signals in response to the setting data,
This sets the reception frequency to 2182kHz.

Plus, a parallel input/output port! 6 sends out the 8-bit L-level serial data Sl along with the 8-bit clock SCK, and then sends out the latch signal RCK, which is one H-level pulse, to reset the control circuits 28 to 30 described above. perform an action.

Next, the parallel input/output port 16 outputs the 32-bit clock SCK and bits b31 and 0 of "B" indicating the radio wave format DSB in the signal format E in FIG.
A32・Noreal data S■ including bit b32 of “
. . bl are sent to the signal control circuit 29 in order, and then the latch signal RCK, which is one pulse of 4 levels, is sent to the two signal control circuits. In addition, parallel input/output port 16
is the 32-bit clock SCK as well as F in FIG.
After sending the normal data S■ containing bits b25 to A28 of "1000" indicating the reception bandwidth 6kl-Iz in the signal formant to the signal control circuit 29 in the order of A32...bl, the I-■ level is A latch signal RCK, which is a pulse II of , is sent to the signal control circuit 29 .

The signal control circuit 29 switches the switch K13 to the b side in response to the data regarding the received radio wave format and reception bandwidth, and the BPP B21 is inserted between the switch K9 and each common side of the KIO. So, switch to 9
By switching the K I O and the above operations, the receiving frequency is set to 2182 kHz, and the radio wave format and receiving bandwidth are set to DSB and 6 kHz, respectively, and reception is possible in the above setting state.

(2) When setting the frequency for telegraph distress communication, etc. to 500kHz In this case, when the 500kHz setting key 212 is pressed,
The CPU 10 takes in data indicating that the key 212 has been pressed from the key 21 in FIG. 5 via the parallel input/output port I7 and the data bus I3 using the method described above.

At this time, the CPU10 calculates the setting data AI to A3 and N1 to N3 corresponding to the receiving frequency of 500kI4z, outputs the data to the parallel input/output port 16, and also calculates the setting data corresponding to the frequency of 500kHz stored in advance in the 110M14. Data regarding the radio wave format and reception bandwidth to be transmitted is read out, and the data is transferred to the parallel input/output port 16. In response, the parallel input/output port I6 transfers the setting data and data regarding the radio wave format and reception bandwidth to the PLL control circuit 28 and the signal control circuit 29 in the same manner as described above. As a result, the reception frequency is set to 500kHz, and the radio wave format and reception bandwidth are set to the radio wave format and reception bandwidth corresponding to the reception frequency shown in Table 1, as described above. It is possible to receive data with this setting.

(3) When setting the frequency for distress communications, etc. for the Navitex system in FGMDSS to 518 kHz In this case, after pressing the 500 kHz setting key 212,
When the up key 219 is pressed, the CPU 10 sequentially transmits data indicating that the key 212 and the key 219 have been pressed from the key 21 in FIG. and import it. At this time, the CPUIQ calculates the setting data A1 to A4 and N1 to N4 corresponding to the receiving frequency of 518 kHz, outputs the data to the parallel input/output boat Natsu 6, and at the same time outputs the data to the frequency 518 kHz previously stored in the ROMIJ. Data regarding the corresponding radio wave format and reception bandwidth is read, and the data is transferred to the parallel input/output port 16. In response, the parallel input/output port I6 transfers the setting data and data regarding the radio wave format and reception bandwidth to the PLL control circuit 28 and the signal control circuit 29 in the same manner as described above. by this,
Similarly to the above, the reception frequency is set to 518kHz, and the radio wave format and reception bandwidth are set to the radio wave format and reception bandwidth corresponding to the reception frequency shown in Table 1, and the above setting state It can be received at

(4) When setting the frequency for ships in FGMDSS to 490 kHz for distress communications, etc. for the broadcasting service system. In this case, after pressing the 500 kHz setting key 212,
When the down key 217 is pressed, the CPU 10 sequentially transmits data indicating that the down key 212 and the key 217 have been pressed, starting from the key 2 in FIG. Import via. At this time, CPUl0 has a receiving frequency of 490k14z
The above setting data A1 to A4 and N1 to N4 corresponding to
At the same time, data regarding the radio wave format and reception bandwidth corresponding to the frequency of 490 kHz stored in advance in the ROMI 4 is read out, and the data is transferred to the parallel input/output port 16. In response, the parallel input/output port 16 transfers the setting data and data regarding the radio wave format and reception bandwidth to the PLL control circuit 28 and signal control circuit 29 in the same manner as described above. As a result, the reception frequency is set to 490kHz, and the radio wave format and reception bandwidth are set to the radio wave format and reception bandwidth corresponding to the reception frequency shown in Table 1, as described above. It is possible to receive data with this setting.

(5) Digital advance selection call in FGMDSS
When setting the frequency to 2187.5 kHz for distress communication, etc. for distress alarms and safety calls by S , data indicating that the key 211 and the key 219 have been pressed are sequentially taken in from the key 2 in FIG. 5 via the parallel input/output port 17 and the data bus 13. At this time, CPU10 receives the reception frequency 2187.
The setting data AI to A4 and Nl to N4 corresponding to 5kHz,z are calculated, and the data is output to the parallel input/output port 16, and the radio wave corresponding to the frequency 2187.5kHz stored in advance in the ROMI 4 is calculated. It reads data regarding the format and reception bandwidth and forwards the data to the parallel input/output port 16. In response, the parallel input/output port I6 transfers the above setting data and data regarding the radio wave format and reception bandwidth to the PLL.
It is transferred to the control circuit 28 and signal control circuit 29 in the same manner as described above. As a result, the receiving frequency becomes 21, as described above.
The frequency is set to 87.5 kHz, and the radio wave format and reception bandwidth are set to the radio wave format and reception bandwidth corresponding to the reception frequency shown in Table 1, and reception is possible in the above setting state.

(6) Radio telex (NBDP) in FGMDSS
) When setting the frequency for distress communication and safety communication to 2174.5kHz, in this case, 21
82kHz setting key 2] After pressing 1, press down key 2
When the key 17 is pressed, the CPU 10 sequentially takes in data indicating that the key 21+ and the key 217 have been pressed from the key 2I in FIG. . At this time,
The CPU 10 calculates the setting data AI to A4 and N1 to N4 corresponding to the receiving frequency of 2174.5 kHz, and outputs the data to the parallel input/output port I6.
Data regarding the N-wave format and reception bandwidth corresponding to 74.5 kHz is read and transferred to the parallel input/output port 16. In response, the parallel input/output port 16 transfers the setting data and data regarding the radio wave format and reception bandwidth to the PLL control circuit 28 and the signal control circuit 29 in the same manner as described above. by this,
Similarly to the above, the reception frequency is set to 2174.5kHz, and the radio wave format and reception bandwidth are set to the radio wave format and reception bandwidth corresponding to the reception frequency shown in Table 1. It becomes possible to receive in the setting state.

As explained above, after pressing the 500kHz setting key 212 or the 2182kHz setting key, the up key 21
9 or down key 217, the receiving frequency is set to the frequency for distress communications, etc. established in the above-mentioned FGMDSS, and the radio wave format and receiving bandwidth are set to the radio wave format and reception corresponding to the frequency for distress communications, etc. Bandwidth can be set, and reception is possible in the above setting state. Therefore, there is an advantage that the receiving frequency can be set to the frequency for distress communications etc. established in the FGMDSS instantly and with a simple operation.

Table 1 [Effects of the Invention] As detailed above, according to the present invention, when the first frequency setting key is pressed, the reception frequency is set to the first frequency for distress communication, emergency communication, or safety communication. In a wireless receiver equipped with a first setting means, when the second frequency setting key is pressed after the first frequency setting key is pressed, the receiving frequency is set for distress communication, emergency communication, or safety communication. Since the second setting means for setting the second frequency is provided,
For example, the first frequency may be 500kHz or 2182kHz, which is a frequency for distress communication, emergency communication, or safety communication.
Hz, and the above-mentioned second frequency is newly established in PGMDSS, and the above-mentioned 500kHz or 2182kHz
By setting the frequency close to the above, the receiving frequency will be immediately changed from the currently set frequency for distress communications, etc. to the newly established frequency for distress communications, etc. in the above-mentioned FGMDSS, which is close to that frequency. can,
There is an advantage that the communication operation for changing the reception frequency described above can be simplified compared to the conventional example.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a signal processing section of a radio receiver according to an embodiment of the present invention, FIG. 3 is a block diagram of first and second local oscillators of the radio receiver of FIG. 1, 4 is a block diagram of the third and fourth local oscillators of the radio receiver of FIG. 1, FIGS. 5 and 6 are block diagrams of the control section of the radio receiver of FIG. 1, and FIG. 1 is a front view of the front panel of the radio receiver shown in FIG. 1, and FIG. 8 is a signal format diagram of data transmitted by the radio receiver shown in FIG. 10... central processing circuit (CPU), 14...
Read only memory (ROivD, 15... Random access memory (RAM), I6... Parallel input/output port, I8... Encoder counter, 22... Multi knob, 23... Tuning knob, 24... RF gain knob, 25... Volume knob, 28... PLL control circuit, two... Signal control circuit, 30... Filter control circuit, 31... Antenna, 34... Impedance matching circuit, 35. ...Control drive circuit, 37..High frequency amplifier, 38..First mixer, 41.48,.19.53..Intermediate frequency amplifier, 55
...SSB demodulator, 57...DSB demodulator, 62.65...Low frequency volume controller, 63.66...Low frequency amplifier, 64...Speaker, +00...First local section Oscillator, 120...Second local oscillator, +30...Third local oscillator, 140...Fourth local oscillator, 211...2182kHz setting key, 212...5
00kHz setting key, 217... down key, 219 up key, K1 to KI4... switch, UIO, U20 to U26. U30. U31 or U
34...Shift register integrated circuit, Ull or UI4
...Serial manual PLL frequency synthesizer integrated circuit, INVI or INV2...Inverter, ANDI or AND4. ANDl +, ANDl2...and gate. Patent applicant Furuno Electric Co., Ltd. agent Patent attorney Maeda Hoshi and 2 others

Claims (1)

[Claims] (1) A first frequency setting key; and a first setting means for setting the reception frequency to a first frequency for distress communication, emergency communication, or safety communication when the first frequency setting key is pressed. a second frequency setting key, and when the second frequency setting key is pressed after the first frequency setting key is pressed, the received frequency is set to a distress communication,
A second frequency set to a second frequency for emergency or safety communications.
A wireless receiver characterized by comprising a setting means.