JPH01146495A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To reduce data lines between a transmitter and a receiver by transmitting a transmission designating data to designate a receiver together with setting data to carry out prescribed setting with a transmitter and detecting whether or not the data are the receipt designated data which are received with the receiver and set beforehand. CONSTITUTION:The data concerning the respective rotations of a multi-knob 22, a tuning knob 23, a high frequency gaining knob 24, and a volume knob 25 and the respective data concerning a pushed key 21 are transmitted to a central processing unit 10, and the respective data are outputted to a parallel input/output port 16. Serial data SI include the receipt designating data to designate respective circuits 28, 29 and 30 to receive them, the data to be received only when the respective circuits 28, 29 and 30 receive the specific receipt designating data alotted to respective circuits beforehand are latched, and a prescribed processing is carried out. Thus, the data line for the latch to have been necessary at every receiver is made into one.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a data transmission device.

[Prior Art] FIG. 9 is a block diagram of a conventional serial data transmission device, which is composed of a transmission control device 500 and ten reception control devices 501 to 510. Here, the reception control device 50! to 51O include a predetermined number of serial registers for temporary storage of serial data.

In FIG. 9, transmission control device 500 has clock SC
After transmitting serial data SI of predetermined bits together with K to the reception control devices 501 to 510, the reception control devices 501 to 5 that should receive the transmitted serial data
The latch signals RCK1 to RCKIO are transmitted to 10. Therefore, the reception control devices 501 to 510 that have received the launch signal latch the received norial data and perform predetermined processing using the serial data.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, the launch signals RCKI to RCKIO are used to identify whether or not to latch the transmitted serial data for each reception control device 501 to 510. Therefore, in the above case, the transmission control device 500 and the reception control devices 501 to 51
0, 12 data lines are required.For example, when there are N reception control devices, (2+N
) book data line is required.

Therefore, as the number of receiving devices increases, the number of data lines increases significantly, which complicates the circuitry of each device and increases the time required for maintenance and inspection. Furthermore, if the data line is connected using a connector etc.
Since the number of pins of the connection connector increases, there are problems in that the cost of the transmission device including the connection connector increases and the reliability of the entire transmission device decreases.

An object of the present invention is to solve the above problems, and provide a data transmission device for transmitting data between a transmitting device and a plurality of receiving devices, in which the number of data lines connected between the transmitting device and each receiving device is An object of the present invention is to provide a data transmission device that can reduce the amount of noise compared to the conventional example.

[Means for Solving the Problems] The present invention includes a transmitting device that transmits configuration data for performing predetermined settings and reception designation data that specifies a receiving device that should receive the configuration data, and a plurality of receiving devices. a data transmission device comprising: receiving means for receiving the setting data and the reception designation data transmitted from the transmitting device;
Detecting whether or not the reception designation data received by the reception means is reception designation data set in advance to be different for each receiving device, and outputs a detection signal when the reception designation data is the reception designation data set in advance. Each of the receiving apparatuses is characterized in that each of the receiving apparatuses includes a detecting means and a setting means for making a predetermined setting based on setting data received by the receiving means in response to a detection signal output from the detecting means.

The present invention also provides a receiving means for receiving setting data for performing predetermined settings and reception designation data specifying a receiving device that should receive the setting data, and a reception means for receiving the reception designation data received by the reception means. a detection means for detecting whether or not it is the own reception designation data, which is set in advance to be different for each device, and outputting a detection signal when the reception designation data is the preset reception designation data; and the detection means output from the detection means. The apparatus is characterized by comprising a setting means for performing predetermined settings based on setting data received by the receiving means in response to a detection signal.

[Operation] With the former configuration, the transmitting device sends setting data for performing predetermined settings and reception designation data specifying a receiving device that should receive the setting data to each of the plurality of receiving devices. Send.

On the other hand, the receiving means of the receiving device receives the setting data and the reception designation data transmitted from the transmitting device, and then the detection means detects that the reception designation data received by the reception means is transmitted to each receiving device. It is detected whether or not the reception designation data is set differently in advance, and a detection signal is output when the reception designation data is the preset reception designation data.

Further, the setting means performs predetermined settings based on setting data received by the receiving means in response to the detection signal output from the detecting means.

Further, by configuring the latter, the receiving means of the data transmission device receives the setting data and the reception designation data transmitted from the transmitting device, and then the detecting means receives the setting data and the reception designation data transmitted from the transmitting device. The receiver detects whether or not the reception designation data is reception designation data set in advance to be different for each receiving device, and outputs a detection signal when it is the reception designation data set in advance. Further, the setting means performs predetermined settings based on setting data received by the receiving means in response to the detection signal output from the detecting means.

Therefore, the transmitter transmits the reception designation data together with the setting data, and in response, the reception device detects whether or not the received reception designation data is preset reception designation data. Therefore, for example, when each data line for clock, serial data, and latch is used as in the conventional example, the data line for the notch that is required for each receiver can be reduced to one. , the data line between the transmitting device and the receiving device is 3
It becomes a book.

[Embodiment] FIGS. 1 to 6 are block diagrams of a radio receiver having a receiving frequency of 0.1 MHz to 40 MH2, which is an embodiment of the present invention.

The wireless receiver of this embodiment has the following features.

(1) Data regarding each rotation of the multi-knob 22, tuning knob 23, high-frequency gain knob (hereinafter referred to as RF gain knob) 24, and volume knob 25, as well as each data regarding the pressed keys 21, are stored in the central processing unit (hereinafter referred to as C
It is called PU. ) IO and in response, the CP
Ul0 or each of the above data is output to the parallel input/output port I6. At this time, the parallel input/output boat 16 transfers the serial data Sl including each of the above data to the PLL control circuit 28.
, the signal control circuit 29, and the filter control circuit 30. Here, the serial data SI includes reception designation data that designates each circuit 28, 29.30 to receive the data, and each circuit 28, 29.30 receives specific reception designation data assigned in advance to each circuit. The received data is latched and predetermined processing is performed only when the data is received.

(2) With the above configuration, adjustment of the shift bond of the bus band shift, adjustment of impedance matching with the antenna,
Adjustment of the illuminance of the LED 19 on the front panel and the signal level meter (hereinafter referred to as S meter) 68, adjustment of the threshold level for starting blanking by the noise blanker gate 46, and adjustment of the pass band of the notch filter 52. Adjustment of the center frequency, adjustment of the signal level to stop each operation during seek, scan and sweep to scan the received frequency, and adjustment of the signal level of the line output to output the demodulated low frequency signal to an external device. Adjustments can be made using one multi-knob 22.

(3) With the configuration described in (1) above, the receiving frequency of the radio receiver is set to a frequency for distress communication, emergency communication, or safety communication when using a telegraph and telephone (hereinafter referred to as a frequency for fL pheasant communication, etc.). ), keys 211 .
212, when the keys 211 and 212 are pressed f2 and the up gear 219 is pressed, respectively,
The reception frequency is 518 kHz and the frequency shift keying (hereinafter referred to as FSK) Navtex signal is used to pass only the desired signal around the reception frequency. ) at IkHz, as well as receiving frequency 21
It can be set to receive digital cell call signals of 87.5 kHz and radio wave type FSK with a reception bandwidth of 1 kHz. In addition, when the down key 217 is pressed after pressing the keys 211 and 212, the reception frequency is 49.
0kHz and radio wave type FSK with a reception bandwidth of 1kHz, and a reception frequency of 2174.
It can be set to receive telex signals of 5 kHz and radio wave type FSK with a reception bandwidth of 1 kHz.

In FIG. 1, the radio signal received by the antenna 31 is connected to the common side of the switch 3 via the antenna terminal 32, the a side of the switch Kl, and the a side of the switch 2. The b side of the switch Kl is connected to the switch K via an attenuator 33.
Connected to the b side of 2.

Here, the switches K1 and K2 are switched by the filter control circuit 30 in conjunction with each other.

The a side of switch 3 is connected to the a side of switch 8 via a band pass filter (hereinafter referred to as PPP) B11 that passes only signals of 23 to 40 MHz.

The b side of switch 3 is connected to the common side of switch 4. The a side of the switch 4 is connected to the a side of the switch 7 via an impedance matching circuit 34 for matching the output impedance of the antenna 31 to the input impedance of the LPF 36 of the high frequency amplification section of the wireless receiver. The impedance matching circuit 34 is, for example, the circuit 3
10 inductors connected in series between the input and output terminals of 4, and 10 inductors connected in parallel with each of the above inductors.
and a capacitor connected between the output terminal of the circuit 34 and ground. Each switch in the impedance matching circuit 34 receives serial data Sl.
It is turned on or off by a control drive circuit 35 operating in response to matching setting data included in the circuit 34, thereby changing the inductance value of the circuit 34 and performing the impedance matching operation.

1 by interlocking switches 5 and 6.
One BPF' One BPF from Bl to BIO is connected between the common side of switch 5 and the common side of switch 6. Bl is a BPF that passes only signals of 0.1 to 0.3 MHz, B2 is a BPF that passes only signals of 0.3 to 0.53 MHz, and B3 only passes signals of 0.53 to 1.6 MHz. It is a BPF that passes through. Also, B4 is 1.6 to 2.4
BPF' is a BPF that passes only MHz signals, and B5 is a BP that passes only 2.4 to 3.6 MHz signals.
F', and B6 is a BPF that passes only signals of 36 to 5.4 MHz. Further, B7 is a BPF that passes only 5.4 to 8 M I-(z signals, B8 is a BPF that passes only 8 to 12 MHz signals, and B9 only passes 12 to 18 MHz signals. BPF, BIO is 18 to 23M
This is a BPF that passes only Hz signals.

The common side of switch 6 is connected to the b side of switch 7, the common side of switch 7 is connected to the b side of switch 8, and the common side of switch 8 is connected to the high frequency amplification section of this radio receiver. Low pass filter (hereinafter referred to as LPP) 3
It is connected to the input terminal of 6. 3 and 8 on the above switch,
Switches 4 and 7 and switches 5 and 6 are respectively switched by the filter control circuit 30 in conjunction with each other.

The signal input to the LPF 36 is passed through the high frequency amplifier 37 to the first
input to mixer 38. On the other hand, the first local oscillator 100
Frequency output from 80°555 to 120.45
The first local oscillation signal of 5 MHz is input to the first mixer 38 via the buffer amplifier 39. The first mixer 38 multiplies the manually input received signal and the first local oscillation signal, extracts the first intermediate frequency signal, and transmits the first intermediate frequency signal to the post-amplifier 40 and intermediate frequency amplifier 41. It outputs to the second mixer 42 via. Here, the power gain of the intermediate amplifier 11 is controlled by an automatic gain adjustment control (hereinafter referred to as AGC) DC voltage output from the DC amplifier 71. On the other hand, the frequency output from the second local oscillator 120 is 80M.
The second local oscillation signal of Hz is input to the second mixer 42 via the buffer amplifier 43.

The second mixer 42 multiplies the input first intermediate frequency signal and the second local oscillation signal, extracts the second intermediate frequency signal, and transmits the second intermediate frequency signal to the post amplifier 44 and the buffer amplifier. 45. The signal output from the post-amplifier 44 is output to the common side of the switch 8 via a noise blanker gate 46 that switches whether or not to pass the input signal and an intermediate frequency amplifier 48. On the other hand, the buffer amplifier 45
extracts the noise component from the input signal, amplifies it, and then outputs it to the noise blanker control circuit 47.

The noise blanker control circuit 47 turns the noise blanker gate 46 from on to off when the noise signal manually input from the buffer amplifier 15 exceeds the noise blanker threshold level data value NBV input from the signal control circuit 29. Switch.

The switches 9 and KIO are switched by the signal control circuit 29 in conjunction with each other, so that one of the four reception bandwidth selection BPFs B21 to B24 is selected.
A PF is connected between the common side of switch 9 and the common side of switch KIO.

Here, B11 is a BPF having a reception bandwidth of 6kHz centered on the reception frequency, and similarly, B22 to B24 have reception bandwidths of 3kHz and 1kl-1z, respectively.
It is a BPF with a reception bandwidth of 10.2kHz.

The second intermediate frequency signal output from the common side of the switch KIO is input to the third mixer 50 via the intermediate frequency amplifier 49. 380 output from the third local oscillator 130
The third local oscillation signal of kHz±3kHz is sent to the buffer amplifier 5.
1 to the third mixer 50. Third mixer 5
0 multiplies the input second intermediate frequency signal and the third local oscillation signal, extracts the third intermediate frequency signal, and then outputs it to the common side of the switch Kll. Here, the intermediate frequency amplifier 4
The gain of 9 is controlled by the AGC DC voltage output from the DC amplifier 7I.

The a side of switch Kll is connected to the a side of switch K12, and the b side of switch Kll is connected to the b side of switch 12 via a notch filter 52 having a predetermined passband width. Here, the switches Kll and K12 are switched by the signal control circuit 29 in conjunction with each other. The third intermediate frequency signal output from the common side of switch K12 is
The signal is inputted via an intermediate frequency amplifier 53 to a buffer amplifier 54, a buffer amplifier 56, and an AGC detector 58. Here, the gain of the intermediate frequency amplifier 53 is controlled by the AGC DC voltage output from the DC amplifier 7I.

The third intermediate frequency signal output from the buffer amplifier 54 is a single sideband amplitude modulation signal (hereinafter referred to as SSB) demodulator 5
5, and is output to the a side of the switch 13 via the preamplifier 60. Further, the third intermediate frequency signal output from the buffer amplifier 56 is a double sideband amplitude modulation signal (hereinafter referred to as DS
It's called B. ) is output to the b side of the switch 13 via the demodulator 57 and preamplifier 61. On the other hand, the fourth local oscillator 140 outputs a frequency of 75kHz±6kHz.
The local oscillation signal is a beat frequency oscillation signal (hereinafter referred to as BFO).
It's called a signal. ), SSB via buffer amplifier 72
It is output to the demodulator 55.

The switch KI3 is switched by the signal control circuit 29, and the demodulated low frequency signal output from the common side of the switch KI3 is outputted to the speaker 64 via the low frequency sound unit 62 and the low frequency amplifier 63. At the same time, the signal is output to the line output terminal 67 and the switch 14 on the a side via the low frequency volume controller 65 and low frequency amplifier 66. Here, the low frequency volume controllers 62 and 65 control the speaker output volume control data A output from the signal control circuit 29.
The amount of attenuation of each adjuster is controlled in response to FV and line output volume control data L I NEG.

Further, the low frequency signal outputted from the common side of the switch KI3 is outputted to the AGC control circuit 59 via the AGC detector 69. The AGC detector 58 performs envelope detection on the manually input signal and outputs the detection output to the ACC control circuit 59 .

The AGC control circuit 59 controls on/off of the AGC output from the signal control circuit 29 and performs high-speed (FAST) control of the AGC.
) and AGC control signals including low speed (SLOW) control,
Also, in response to the high frequency gain control data RFG, the AG
The detection output input from the C detector 56 and the AGC detector 6
From the detection output input from 9, an AGC DC voltage for gain control of the first intermediate frequency signal and an AGC DC voltage for gain control of the second and third intermediate frequency signals are generated, and each signal is converted into a DC voltage. Output to amplifiers 70 and 71.

Here, the AGC control circuit 59 controls the intermediate frequency amplifier 41 in proportion to the value of the input high frequency gain control data RFC.
A output to the DC amplifier 70 so that the gain of
Controls GC DC voltage. Further, the AGC control circuit 59 generates a level signal indicating the average level of the received signal from the detection output input from the AGC detector 58, and outputs the level signal to the inverting input terminal of the comparator 74.
It is output to the S meter 68 via the b side of the switch KI4. Here, the switch 14 is switched by the signal control circuit 29.

The scanning stop threshold data 5CANV output from the signal control circuit 29 is converted into digital/analog conversion (hereinafter referred to as D/A).
This is called A conversion. ) After being D/A converted in the device 75,
It is input to the non-inverting input terminal of comparator 74. Comparator 74
When the level of the level signal input to the inverting input terminal exceeds the level of the threshold data 5CANV input to the non-inverting input terminal, the scan stop signal 5TOP goes to L level.
is output to the parallel input/output port 16.

Next, the configurations of the first to fourth local oscillators 100, 120, 130, and 140 will be described with reference to FIGS. 3 and 4.

In FIG. 3, the reference oscillator 101 is 10°24MH
z signal and converts the reference signal into a phase-locked loop circuit (hereinafter referred to as PLL).
PLLIVI 41. and is output to the mixer 111, and the PLLI[I 04
Output to.

The PLL 1102 adjusts the frequency multiplication ratio to 16/1 based on the data N I and A I input from the PLL control circuit 28 .
A signal obtained by frequency-dividing a signal input from a prescaler 107 having a prescaler 107 having a prescaler 107 and an input reference signal of 10° 24 MHz are phase-detected, and the detected output is sent to a voltage controlled oscillator via an LPF having a predetermined cutoff frequency. (Hereinafter, vC
It's called O. 0105, it is output as a phase control voltage.

VCO[105 responds to the input phase control voltage to
A first local oscillation signal of 0°555 to 120.455 MHz is output to the buffer amplifier 39 and the mixer 106.

The mixer 106 mixes the input first local oscillation signal and the BPF.
After multiplying the signal by the manually inputted signal from 114, a signal representing the difference in frequency between both signals is extracted and outputted to PLL I102 via prescaler 107. Here, PLL11
02 and the prescaler 107, the frequency division ratio N T l of the entire PLL circuit is given by the following equation.

NT1=16NI+AI...(1)
In addition, PLL11Q2, VCO1105, mixer 106
, and a prescaler 107, a first local oscillation signal that changes in steps of 40 kHz is obtained.

PLLn 104 receives data N2. input from PLL control circuit 28. Frequency multiplication ratio 128/1 based on A2
A signal obtained by frequency-dividing a signal input from a prescaler 109 having a prescaler 109 having a prescaler 109 having a frequency of
It is output as a phase control voltage to Vcontos via PF'.

vcontos is 4 in response to the manually applied phase control voltage.
4 to 48MHz signal by I/100 divider +10
It is output to mixer III via prescaler 109 and to PLLllll04 via prescaler 109. Here, the frequency division ratio NT2 of the entire PLL circuit formed by the PLLn 104 and the prescaler 109 is given by the following equation.

NT2=128N2+A2 ・・・・・・(2
) In addition, the IkHz
Obtain the output signal of VCOIII08 that changes in steps of z.

The mixer 111 receives a signal input from the frequency divider 110, and
IO and a reference signal of 24 MHz, and after extracting a signal of each frequency difference between both signals, the signal is output to the mixer 113 via the BPF l 12 having a passband l017±20 kHz.

The mixer 113 multiplies the signal input from the BPF 112 and the second local oscillation signal of 80 MHz output from the second local oscillator 120, extracts a signal of the difference in each frequency of both signals, and then The extracted signal is converted to a passing frequency of 69.
It is output to mixer 106 via BPF 114 having a frequency of 28 to 69.32 MHz.

The second local oscillator +20 generates a second local oscillation signal of 80 MHz and outputs it to the mixer 113 and the buffer amplifier 43.

In FIG. 4, the IO output from the basic oscillator 101
, 24MI-Iz are input to PLL[ll31 and PLL1102.

r'LL1] 1131 is data N3. Frequency multiplication ratio + based on A3
A signal obtained by frequency-dividing a signal manually inputted from a prescaler 133 having a prescaler 133 having a frequency of 6/I7 and an input reference signal is phase-detected, and the detected output is converted into an L having a predetermined cutoff frequency.
It is output as a phase control voltage to VCOI[I I 32 via PF. The VCO II 32 responds to the input phase control voltage by converting a 76MHz ±0.6MHz signal into 1
It is output to the buffer amplifier 51 via the /100 frequency divider 134 and the I/2 frequency divider 135 as a 380KHz ±3kHz signal, and is also output to the PL signal via the prescaler 133.
Output to LI[1131. Here, PLLII[+
31 and the prescaler 133, the frequency division ratio NT3 of the entire PLL circuit is given by the following equation.

NT3=16N3+A3 ・・・・・・(3)
Also, PLLIII I 31. VCOI [I 13
2, and a prescaler +33, the VCOII1132 changes in steps of 5kHz.
Therefore, a 25 Hz step signal can be obtained as the third local oscillation signal.

PLLIVI41 receives data N4. input from the PLL control circuit 28. Frequency multiplication ratio +6/+ based on A4
phase-detecting the input reference signal and the signal obtained by frequency-dividing the signal manually inputted from the prescaler 143 having
The detected output is output as a phase control voltage to VC'0IV142 via an LPF having a predetermined cut-off frequency. VCOIVI42 responds to the input phase control voltage and converts the signal of 75MHz±6MHz to 1/100.
It is output as a 75MHz±6kHz signal to the buffer amplifier 72 via the frequency divider 144 and the I/10 frequency divider 145, and is output to the PLLIV1 via the prescaler 143.
41. The frequency divider 145 is enabled and outputs the fourth local oscillation signal when the H-level BFO signal output from the PLL control circuit 28 is input,
On the other hand, when the BFO signal at L level is input, it is disabled and the output of the fourth local oscillation signal is stopped.

Here, the frequency division ratio NT4 of the entire PLL circuit including the PLLIV141 and the Briske-5143 is given by the following equation.

NT4'=16N4+A4 ・・・・・・(4
) Also, a circuit consisting of PLLIV141, VCO [Vl 42, and prescaler +43]
It is possible to obtain the output signal of the VCOIV 142 that changes in steps of Hz, and therefore the fourth local oscillation signal is
A signal in Hz steps can be obtained.

In FIG. 5, the CPU operation circuit is a control circuit that controls the entire radio receiver, and receives a clock for CPU operation at a predetermined frequency from the clock generator 11, and operates in response to the clock. do.

The CPU 10 has a read-only memory (hereinafter referred to as R
It's called OM. ) +4, and the power is backed up by battery B, and the radio receiver receives 400
A RAM+5 is connected which stores the channel reception frequency, the emergency communication reception frequency, and setting data for each reception frequency, and is used as a work area for the CPU10.

Further, parallel input/output ports 16 and 17 are connected to the CPU 10 via an address bus 12 and a data bus 13. The parallel input/output boat 16 outputs a clock SCK and serial data S in response to an instruction from CPU10.
RF' gain knob 24 and volume knob 2 which are input from analog/digital converter (hereinafter referred to as A/D converter) 26 while transmitting I and latch signal RCK.
The setting data corresponding to rotational position No. 5 is transferred to CPU10. Further, when the parallel input/output boat 16 receives the scanning stop signal 5TOP output from the comparator 74 in FIG. 2, it transfers the signal 5TOP to the CPU 1O. child,
The DC voltage output circuits of the iron, RF gain knob 24, and volume knob 25 output predetermined DC voltages to the A/D converter 26 in accordance with the rotational positions of the knobs 24 and 25. In response, the A/D converter 26 converts the input DC voltage into 6-bit setting data for the knobs 24 and 25 and outputs it to the parallel input/output port 16.

The parallel input/output board 17 takes in setting data by pressing various keys 21 on the front panel of the radio receiver shown in FIG. 7, outputs the setting data onto the data bus 13, and displays various displays on the front panel. The data for driving the light emitting diode (hereinafter referred to as LED) 19 is latched and the LED drive circuit 18
Output to LEDI9 via. Here, the parallel input/output board 17 periodically enables the key scan circuit 20, and in response, the enabled key scan circuit 20 scans each key of the keys 21, and the data of the pressed key is The signal is output to the CPU10 via the parallel input/output port 17 and the data bus 13. As a result, data indicating whether or not the key 21 has been pressed is transmitted to the CPU10.
be taken in.

Further, an encoder counter 18 is connected to the CPU10 via a data bus 13. The encoder counter 18 is connected to the output terminal of the pulse output circuit of the multi-knob 22 and the output terminal of the pulse output circuit of the tuning knob 23, and when the multi-knob 22 or the tuning knob 23 is rotated, a pulse is output depending on the direction of rotation. The phases are different and pulses are output to the encoder counter 18 only during rotation. The encoder counter 18 is a multi-knob 22 or a tuning knob 23.
When a pulse is input from the pulse output circuit of
The identification data of the tuning knob 23 is outputted to the CPU 10 via the data bus 13. When CPU10 receives the interrupt signal IRQ, it receives the pulse data and identification data from the encoder counter 18.

The parallel input/output boat 16 outputs the serial data Sl together with the clock SCK to the PLL control circuit 28, the signal control circuit 29, and the filter control circuit 30, and then outputs the latch signal RCK when transmitting each data to be described in detail later. . The serial data SI includes 8-bit reception designation data indicating a shift register group, which will be described in detail later, in the control circuits 28, 29.30 to be received, and a number of bits that differs depending on the control circuits 28, 29.30 to be received. It has 19 bits, 24 bits, or 16 bits of setting data. The format of this serial data Sl will be described in detail later with reference to FIG.

As shown in FIG. 7, the LED 19 includes seven 7-segment LEDs 200a to 200g and 11 LEDs.
201a to 201k, and the LED I 9 is provided at the upper center of the front panel of the wireless receiver. Further, a tuning knob 23 and a multi-knob 22 are rotatably provided at the center and right side of the front panel of the wireless receiver, respectively, and an RF gain knob 2 is provided at the front panel to the left of the tuning knob 23.
4 and a volume knob 25 are rotatably juxtaposed.

The key 21 provided on the front panel of the wireless receiver is the seventh key.
It has many keys as shown in the figure. That is, 202
a to 202f are radio wave types USB, LSB (hereinafter referred to as
SSB using the lower sideband is called LSB. ), telegraph (C
W), FSK, facsimile (FAX), and DSB, and are keys 203a to 2
03d is 6 kHz, 3 kHz, 1 kHz, to pass the desired signal around the reception frequency.
and a key for specifying the reception bandwidth of 0.2kHz.

204a to 204e, and 2058 to 205
C, 208 is a key that allows predetermined adjustments, which will be described in detail later, using the multi-knob 22.

204a becomes a bus band shift key when a radio wave type other than telegraph (CW) is selected, and becomes a BFO key when telegraph (CW) is selected as a radio wave type. Here, passband shifting refers to pseudo-shifting the passing center frequency of a bandpass filter for intermediate frequency signals that determines the selectivity characteristics of a wireless receiver, thereby making it possible to eliminate interference. . When the passband shift key 204a is pressed when a radio wave type other than telegraph (CW) is selected, the amount of deviation of the passband shift can be changed by rotating the multi-knob 22. In this embodiment, the above-mentioned path is changed by changing the setting data AI or N1 and the setting data A4 or N4 so that the frequency of the first local oscillation signal and the frequency of the fourth local oscillation signal are respectively shifted by the same frequency. Achieves band shift.

On the other hand, when the key 204a is pressed when telegraph (CW) is selected as the radio wave type, the tone of the telegraph output from the speaker 64 can be adjusted by rotating the multi-knob 22. In this example,
The tone of the telegram is avoided by changing the setting data A4 or N4 so that the frequency of the fourth local oscillation signal changes.

204b is a filter key, and the filter key 204
When b is pressed, 3. 8 is switched to the b side, and the switch 4. 7 is switched to the a side, and an impedance matching circuit 34 is connected between the antenna 31 and the LPF 36 of the high frequency amplification section. Here, by rotating the multi-knob 22, the matching setting data can be changed. 204c is a day marquee, and when the day marquee 204c is pressed down, the multi-knob 2
By rotating 2, the illuminance of the LED 9 and the illuminance of the S meter 68 illumination (not shown) can be controlled. 204d is a noise blanker key. When the noise blanker key 204d is pressed, the noise blanker control circuit 47 is enabled, and by rotating the multi-knob 22, the level of the noise signal to be blanked can be adjusted.

204e is a notch filter key, and when the notch filter key 204e is pressed, 1 is applied to switch Kll.
A notch filter 52 is connected between the third mixer 50 and the intermediate frequency amplifier 53, which attenuates only specific frequency components within the reception bandwidth including the reception frequency. By rotating the multi-knob 22, the center frequency of the notch filter 52 can be shifted in a pseudo manner, thereby making it possible to remove, for example, beat interference. In this embodiment, by changing the setting data A3 or N3 and the setting data A4 or N4 so that the frequency of the third local oscillation signal and the frequency of the fourth local oscillation signal are respectively shifted by the same frequency, the above-mentioned This realizes changing the center frequency of the notch filter 52.

Note that the key 22a is a hold key, and when the hold key 22a is pressed, the pulse output circuit of the multi-knob 22 does not output pulses even if the multi-knob 22 is rotated. The data set by the multi-knob 22 can be held by disabling the multi-knob 22.

Furthermore, keys 204b, 202b, 203b, 204c
, 202c, 203c, 204d, 202d, 203d
, 202e constitute a numeric keypad, and when predetermined data is input using the numeric keypad, the key 20
3a transfers data entered using the numeric keypad to the CPU10.
Used as the enter key to transfer to.

205a is a seek key, and by pressing the up key 219 or the down key 217 after pressing the seek key 205a, the receiving frequency is continuously changed upward or downward, respectively, and the scanning stop is set by rotating the multi-knob 22. When a signal level equal to or higher than the threshold is received, scanning by the seek is stopped.

205b is a scan key;
When pressing b and inputting a predetermined group number of the channels registered in advance in the RAM 15 using the numeric keypad, and then pressing the enter key 203a, the receiving frequency will be changed between each channel in the registered group. scanned. At this time, as in the case of the seek, when a signal level equal to or higher than the scan stop threshold set by rotating the multi-knob 22 is received, the scan is stopped.

205c is a sweep key;
After pressing c and inputting the group number that combines the lower end frequency, upper end frequency, and step frequency at the time of scanning registered in advance in the RAM 15 using the numeric keypad, press the enter key 203a. The reception frequency is scanned using the specified frequency within the selected group.

At this time, as in the case of the seek and scan described above, when a signal level equal to or higher than the scan stop threshold set by rotating the multi-knob 22 is received, the scan by the sweep is stopped.

208 is a line key, and when the line key 208 is pressed, the switch K14 is switched from the b side to the a side, and the display of the S meter becomes the display of the signal level output to the line output terminal 67.

At this time, by rotating the multi-knob 22 while pressing the key 218, the line output volume control data LINEG can be changed, thereby changing the amount of attenuation of the low frequency volume adjuster 65, and the line terminal 6
The signal level of the line output output to 7 can be changed.

206a is a key for turning off AGC;
6b is a key for setting high speed (F'AST) AGC, and 206C is a key for setting low speed (SLOW) AGC. 207 is the switch Kl, to 2
This key is used to switch from the a side to the b side in conjunction with the above and insert the attenuator 33 into the input end of the radio receiver.

210 is a fine key for setting fine adjustment of tuning using the tuning knob 23; 211 is a key for setting the reception frequency to 2182kHz, a frequency for telephone distress communications; and 212 is a This key is used to set the frequency to 500 kHz, which is the frequency for telegraph distress communications, etc. Furthermore, 213 is a lock key for holding the set reception frequency after setting the reception frequency using the key 210 and the tuning knob 23 or keys 2!1, 2+2.

214 is a channel key, and after pressing the key 214 and inputting the channel number using the numeric keypad,
By pressing the enter key 203a, the receiving frequency can be set to the frequency of the input channel registered in advance in the RAM 15. 2+5 is a frequency key, and by pressing this key, input the receiving frequency using the numeric keypad, and then press the enter key -203.
By pressing 8, you can set any frequency.

Reference numeral 216 is a memory key, which is used to set the receiving frequency using the above-mentioned operations, as well as setting the radio wave type, setting the receiving bandwidth, setting AGC, and setting whether or not to insert the attenuator 33.
Setting whether to insert the impedance matching circuit 34,
Also, after setting the matching setting data in the impedance matching circuit 34 (hereinafter, the setting data of the above seven items other than the reception frequency is referred to as preset data), press the memory key 216 and use the numeric keypad to set the matching setting data. By inputting the channel number in which the receiving frequency and the preset data are registered and pressing the enter key 203a, the receiving frequency and the preset data are stored in a predetermined address corresponding to the channel in RAM+5.

217 is a down key for changing the currently set channel or reception frequency to a channel with a smaller channel number or a lower frequency. A function key 218 is used to perform a predetermined additional function when setting a channel or reception frequency or setting matching setting data in the impedance matching section 3. 21
9 is an up key for changing the currently set channel or reception frequency to a channel with a larger channel number or a higher frequency.

In FIG. 6, the clock SCK output from the parallel input/output board 16 is connected to the SCK terminal of the Toshiba Electric Corporation TC74HC595P 8-bit shift register integrated circuit UIO in the PLL control circuit 28 and the Motorola MC
4 serial manual PLL frequency synthesizer integrated circuits of type 145156P Ull to U1'4 each CLO
The signal is input to the CK terminal and is also input to the RCK terminal of the integrated circuit UIO via the inverter INVI. Here, each of the integrated circuits U11 to U14 includes a 7-bit shift register, a 10-bit shift register, and a 2-bit shift register, and has a total of 19-bit shift registers. The clock SCK is also input to each SCK terminal of seven shift register integrated circuits U20 to U26 of the TC74HC595P type in the signal control circuit 29, and the clock SCK is also input to each SCK terminal of seven shift register integrated circuits U20 to U26 of the TC74HC595P type in the signal control circuit 29.
SCK terminal of C595P type shift register integrated circuit U30 and Mitsubishi Electric (manufactured by Mitsubishi Electric) in filter control circuit 30
It is input to each clock input terminal T of four 8-bit shift register integrated circuits U31 to U34 of the M54975P type. The clock SCK is input to the RCK of the integrated circuit U3Q via the inverter INV2.

The serial data SI output from the parallel input/output port 16 is sent to the Sl terminal of the integrated circuit UIO, the integrated circuit U20.
and the Sl terminal of the integrated circuit U30. Furthermore, the latch signal RCK output from the parallel input/output board 16 is input to each first input terminal of the AND gates AND1 to AND4 in the PLL control circuit 28, and the integrated circuit U2 in the signal control circuit 29.
It is input to the RCK terminal of 0. Further, the latch signal is input to each second input terminal of the AND gates ANDll and ANDl2 in the filter control circuit 30.

In the PLL control circuit 28, the QB, QF', QG, and QH output terminals of the shift register integrated circuit UIO are connected to the second input terminals of the AND gates AND1 to AND4, respectively, and the QH' data of the integrated circuit UIO is connected to each second input terminal of the AND gates AND1 to AND4. The output terminal is connected to each data input terminal DATA of the shift register integrated circuits Ull to UI4. Each output terminal of the AND gates AND1 to AND4 is connected to each ENABL of the shift register integrated circuits Ull to UI4, respectively.
Connected to E terminal. The data output terminals of integrated circuits Ull to Ut4 are PLL I 102 and PLL, respectively.
ff104, PLLII[I 31, and PLL, r
It is connected to each data input terminal of V141 and the enable terminal of frequency divider 145.

In the signal control circuit 29, the shift register integrated circuit U
The 20 QC output terminals are connected to each RCK input terminal of integrated circuits U24 to U26, and the QD output terminal of integrated circuit U20 is connected to each RCK input terminal of integrated circuits U21 to U23. The QH' output terminal of integrated circuit 020 is connected to each Sl terminal of integrated circuits U21 and 024. The QH' output terminal of integrated circuit U21 is connected to the S input terminal of integrated circuit U22, and the QI-I' output terminal of integrated circuit U22 is connected to the S1 input terminal of integrated circuit U23. The QH' output terminal of integrated circuit U24 is the sr of integrated circuit U25.
and the QH' output terminal of the integrated circuit U25 is connected to the S1 input terminal of the integrated circuit U26.In the filter control circuit 30, the QA of the integrated circuit U30
The output terminal is connected to the first input terminal of the AND gate AND l 2, and the QB output terminal of the integrated circuit U30 is connected to the first input terminal of the AND gate AND11. The output terminal of ANDl 1 is connected to each LATCH terminal of integrated circuits U31 and U32, and
The output terminal of ND+2 is connected to each LATCH terminal of integrated circuits U33 and U34. QH' of integrated circuit U30
The output terminal is connected to each SIN input terminal of integrated circuits U31 and U33, and the 5OUT output terminal of integrated circuit U31 is connected to the SIN input terminal of integrated circuit U32.
The 5OUT output terminal of 33 is connected to the SIN input terminal of integrated circuit U34. The QA and QC to QG output terminals of integrated circuit U31 and the QA to QP and QG output terminals of integrated circuit tJ32 are connected to a switching control circuit SC which switches the switches from 1 to 8. QD or QH output terminal of integrated circuit U33 and integrated circuit U3
The QD or QH output terminals of No. 4 are connected to the data input terminal of the control drive circuit 35.

The above shift register integrated circuit UIO1U20 to 02
6 and U30, as is well known, reads the data input from the Sl terminal into the internal shift register at the rising edge of the clock SCK, latches the read data at the rising edge of the latch signal RCK, and outputs the data to the output terminal QA. output to QH and QHo. As is well known, the integrated circuits Ull to U14 input the DA to the internal shift register at the rising edge of the clock input to the CLOCK terminal.
After reading the data input from the TA terminal, the ENA
When the latch signal input to the BLE terminal is at H level (logical level "1"), the read data is latched and output to the data output terminal.

As is well known, the shift register integrated circuits U31 to U34 read the data input from the SIN terminal into the internal shift register at the rising edge of the clock input to the T terminal, and then output the latch signal input to the LATCH terminal. The data read at the H level (logic level "B") is latched and output to the QA or QH output terminal.

As shown in FIG. 8, the serial data Sl is transmitted to one or more shift registers (hereinafter referred to as
This is called a shift register group. ), 8-bit reception designation data bl to U8, 19 bits, 24
It consists of setting data of bits or 16 bits (b9 onwards), and is transmitted to each circuit 28, 29, 30 by the parallel input/output port 16 starting from the bit with the larger bit number. Note that in FIG. 8, "-" indicates an empty bit.

In the PLL control circuit 28, the serial data Sl input to the SI input terminal of the integrated circuit UIO is transmitted to the integrated circuit UIO.
It is input to each data input terminal DATA of the integrated circuits Ull to U14 via the QH' output terminal of IO. The integrated circuit UIO receives 8-bit reception designation data bl to U8.
This is a shift register for latching. Further, the four integrated circuits Ull to U14 include shift registers for receiving the 19-bit setting data, and each of the integrated circuits Ull to U14 independently constitutes the shift register groups G1 to G4. A to D in FIG. 8 are integrated circuit UIO and integrated circuit U, respectively.
Shift register group G corresponding to ll to U14
8 is a format diagram showing the data to be received by G4, and the serial data of each A to D in FIG.
It consists of bit reception designation data b1 to U8 and 19-bit setting data b9 to U27.

In A and B of FIG. 8, AI, Nl, A2 and N2
are respectively setting data of 7 bits, 10 bits, 7 bits, and 10 bits for changing the frequency of the first local oscillation signal, and data Al and Nl are the setting data of the integrated circuit U.
ll to PLL I 102, and data A2.
N2 is output from integrated circuit U12 to PLL1104. In C of FIG. 8, A3 and N3 are respectively 7-bit and 10-bit setting data for changing the frequency of the third local oscillation signal, and data A3°N3
is output from integrated circuit U13 to PLLI[1131. In D of FIG. 8, A4 and N4 are the fourth
These are 7-bit and 10-bit setting data for changing the frequency of the local oscillation signal, and data A 4 ,
N4 is output from integrated circuit UI4 to PLLrVI41. Furthermore, bit b27 of D in FIG.
This bit controls whether to enable or not.

In the signal control circuit 29, an integrated circuit U20 is a shift register for latching 8-bit reception designation data. Furthermore, each of the three integrated circuits U21 to U23 and U24 to U26 is connected to a shift register group G5. G
6.

E and F in FIG. 8 are shift register groups G, respectively.
5. This is a format diagram showing data to be received by G6, and each serial data S of E and F in FIG. 8 is composed of 8-bit reception designation data bl to U8 and 24-bit setting data b9 to U32. . Here, the eighth
8-bit setting data b9 to U16 of E and F in the figure
are latched by integrated circuits U2+ and U24, and 8-bit setting data b17 to U24 are latched by integrated circuits U22. U2
5 and 8-bit setting data b25 to U
32 is an integrated circuit U23. It is latched by U26.

In E of FIG. 8, bl5 and bl6 are S meter 6
This is control data for switching the switch 14 to the a side or the b side for switching the output signal to the 8, and bl7 to b22 are 6-bit line output volume control data LI
It is NEG. In addition, in E of FIG. 8, b25 to b30 are 6-bit speaker output volume control data AF.
b31 and b32 are control data for switching the switch 13 to the a side or the b side in order to switch the output of the SSB demodulator 55 or the DSB demodulator 57 to the low frequency volume controller 62 and output it. be. In F of FIG. 8, b9 to bl2 are 4-bit scan stop threshold data 5CANV, and bl4 is switch Kll and K
This is control data for switching whether or not to insert the notch filter 52 by switching the notch filter 52 to the a side or the b side in conjunction with the notch filter 52. In addition, in F of FIG. 8, bl5 and bl6 are AGC off and AGC high speed (F A S
bl7 to b22 are 6-bit high frequency gain control data RFC. Furthermore, in F of FIG. 8, b25 to b28 are switches 9 and KIO for switching the receiving bandwidth.
This is control data for switching b29 to b
32 is 4-bit noise blanker control threshold data NBV.

In filter control circuit 30, integrated circuit U30 is a shift register for latching 8-bit reception designation data. In addition, two integrated circuits U31 and U32 each,
and shift register group G for latching 16-bit setting data in U33 and tJ34, respectively.
7. Configure G8. G and H in FIG. 8 are respectively shift register groups G7. This is a format diagram showing data to be received by G8, and each G and H serial data in FIG. 8 is 8-bit reception designation data b! Or b8
and 16-bit setting data b to b24. Here, the 8-bit setting data b9 to bl6 of G and H in FIG. 8 are stored in the integrated circuit U31. U33 latches the 8-bit setting data b17 to b24 to the integrated circuit U32. It is latched by U34.

In G of FIG. 8, b9 is control data for switching switches Kl and 2 in conjunction with each other to switch whether or not to insert the attenuator 33, and b2 to bl5 and b
For l7 to b22, switch 3 to 8 to select one BP from BPP Bl to Bit.
This is control data for inserting F, and b23 is control data for switching between 3 and 8 in the switch to switch whether or not to insert the impedance matching circuit 34. Moreover, in H of FIG. 8, bl2 to bl6
and b20 to b24 are impedance matching circuits 3
This is matching setting data for setting an inductance value by switching 10 switches in 4.

Regarding the operation of the radio receiver configured as described above, in particular, the parallel input/output board 16, the PLL control circuit 28,
The operation of serial data transmission between the signal control circuit 29 and the filter control circuit 30 will be explained.

For example, when the operator rotates the tuning knob 23 to change the reception frequency, a predetermined pulse is output from the pulse output circuit of the tuning knob 23 shown in FIG. 5 to the encoder counter 1B, and in response, the encoder counter 18 The interrupt signal IRQ is output to the CPU1O, and the data related to the above pulse is sent to the data bus! CPU10 through 3
Output to. At this time, the CPU 10 calculates the reception frequency corresponding to the rotation of the tuning knob 23 from the current reception frequency data stored in the RAM 15 and the input data, and calculates the reception frequency corresponding to the calculated reception frequency. After calculating the setting data AI to A3 and Nl to N3, the data is output to the parallel input/output port 16.

In response to this, the parallel input/output boat 16 first
Together with the 7-bit clock SCK, the 27-bit serial data Sl including the setting data AI and Nl is sent in the order of b27...bl in the signal format of A in Figure 8, and then is transmitted with one H-level pulse. A certain latch signal RC
Send K. On the other hand, in the PLL control circuit 28, the inverted signal of the clock SCK is transmitted to the integrated circuit Ul(
) is input to the RCK input terminal of the integrated circuit UIO.
Only the terminal becomes H level. Then, the latch signal RCK
is input to the second input terminal of the AND gate AND1, the AND gate AND1 outputs an H level signal to the ENABLE terminal of the integrated circuit Ujl. As a result, the integrated circuit Ul corresponding to the shift register group Gl
The 19-bit setting data input to l is latched,
Setting data AI and N1h (P
It is output to LL1102. At this time, since bl to bl of the serial data SI are all "o",
Serial data SI input to each shift register of other shift register groups G2 to G8 is not latched.

Next, the parallel input/output boat 16, as described above,
Setting data A2 and N in the signal format of B in Figure 8.
2 is transferred to the integrated circuit U12 and latched, and
Setting data A3 and N in the signal format of C in Figure 8.
3 is transferred to the integrated circuit U13 and latched. This allows setting data A2 and N2 to be transferred from integrated circuit U12 to P
The setting data A3 and N3 are transferred from the integrated circuit U13 to the PL, LLlll 31.

As described above, the setting data AI, Nl, A2. N2, and A3. Since N3 is set in each PLL 102, 104, 131, each frequency of the first and third local oscillation signals is changed, thereby changing the receiving frequency.

Also, setting data A4. When setting N4, send serial data SI in the signal format D in Figure 8.
When changing the matching setting data of the impedance matching circuit 34, and when transmitting serial data ST in the G or H signal format shown in FIG. The serial data S is sent in the signal format of A in FIG.
works similarly.

Furthermore, for example, when the operator rotates the volume knob 25 in order to change the volume of the demodulated signal output from the speaker 64, the DC voltage output circuit of the volume knob 25 in FIG. A DC voltage of a predetermined voltage corresponding to the position is output to the parallel input/output board 16 via the A/D converter 26, and in response, the parallel input/output board 16 outputs the A/D converted DC voltage data. 6-bit speaker output volume control data A
Output the FV to the CPU 10. In response to this, the CPU
0 indicates the data AP for the parallel input/output port 16.
Instructs to transfer V to the signal control circuit 29.

In response to this, the parallel input/output board 16 first
Along with the bit clock SCK, the 8-bit L level serial data S! After sending out the latch signal RCK, which is one pulse at H level. This causes the shift register integrated circuit U10. U2. (],,U
30, 8-bit data "oooooooo" is latched into each integrated circuit U10, U20 . L level signals with data "0" are output from each Q, A to QH output terminal of U30, and as a result, each of the control circuits 28,
29.30 will be reset. Next, the parallel input/output board 16 receives the 32-bit clock SCK.
32-bit serial data S including the above speaker output volume control data APV in the signal format E in FIG.
After sending r in the order of b32...bl, the H level 1
The latch signal RCK, which is a pulse, is sent out. on the other hand,
In the signal control circuit 29, only b4 of the reception designation data bt to b8 is "B", so when the transmission of the serial data S is finished, the Q of the integrated circuit U20 is
Only the D terminal becomes H level, and the H level signal is input to the RCK terminals of integrated circuits U21 to U23.

As a result, the 24-bit setting data b9 to b32 excluding the above-mentioned reception designation data input to the integrated circuits U21 to U23 corresponding to the shift register group G5
is latched, and the speaker output volume control data AFV included in the setting data is output to the low frequency sound ff1FI moderator 62. In response to this, the low frequency volume controller 62
The low frequency signal output from the common side of the switch K l 3 is attenuated by an attenuation amount corresponding to the input data AFV. As a result, the volume of the demodulated low frequency signal output from the speaker 64 is adjusted.

Furthermore, the transfer of data other than data AFV in E of FIG. 8 and each data in F of FIG. 8 is performed in the same procedure as the above-described transfer of data AFV.

As explained above, in transmitting each setting data from the parallel input/output board 16 to each control circuit 28, 29.30, the serial data S to be transmitted specifies the shift register group Ct to G8 to be received. includes reception designation data bl to b8 and predetermined each of the above setting data, and when the reception designation data is the same as the preset own reception designation data and a latch signal is input, the shift register belongs to the corresponding shift register group. A shift register performs a latch operation. Therefore, as shown in FIG.
There is an advantage that K can be transferred from the parallel input/output port 16 to each shift register of the desired shift register groups G1 to G8 and latched using only three data lines for transmitting K.

In the above embodiments, the case where serial data Sl is transmitted has been described, but the present invention is not limited to this, and can be applied to the case where multiple bits of parallel data are transmitted.

Note that the transmitting device described in the claims corresponds to the parallel input/output port 16 in this embodiment, and the receiving device is
It corresponds to the PLL control circuit 28, the signal control circuit 29, and the filter control circuit 30. Further, the receiving means includes each control circuit 2.
8, 29, and 30, the detection means corresponds to the integrated circuit UIO and AND gates AND1 to AND4 in the control circuit 28, the integrated circuit U20 in the control circuit 29, and the integrated circuit UIO in the control circuit 30. integrated circuit U
30 and the AND gates ANDII and AND +2. Furthermore, the setting means includes integrated circuits Ull to U14 and PLLs 102 to 14 in the control circuit 28.
1. Integrated circuits U21 to U26 in the control circuit 29 and integrated circuits U31 to U34 in the control circuit 30,
It corresponds to the switching control circuit SC1 and the control drive circuit 35.

[Effects of the Invention] As detailed above, according to the present invention, a transmitting device transmits setting data for making predetermined settings as well as reception designation data that designates a receiving device, and in response, the receiving device Since it is detected whether the received reception designation data is predetermined reception designation data, for example, when the clock, serial data, and latch data lines are used as in the conventional example, The number of data lines required for latching for each receiving device can be reduced to one, thereby reducing the number of data lines between the transmitting device and the receiving device to three. Therefore, the number of data lines between the transmitting device and the receiving device can be significantly reduced compared to the conventional example, and the circuits within each device can be simplified, reducing the time required for maintenance and inspection. . In addition, for example, when the data lines are connected using a connector, the number of pins of the connector is reduced compared to the conventional example, reducing the cost of the transmission device including the connector, and reducing the number of pins of the connector. There is an advantage that the reliability of the entire device can be improved compared to the conventional example.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a signal processing section of a radio receiver according to an embodiment of the present invention, FIG. 3 is a block diagram of first and second local oscillators of the radio receiver of FIG. 1, 4 is a block diagram of the third and fourth local oscillators of the radio receiver of FIG. 1, FIGS. 5 and 6 are block diagrams of the control section of the radio receiver of FIG. 1, and FIG. Figure 1 is a front view of the front panel of the wireless receiver, Figure 8 is a signal format diagram of data transmitted by the wireless receiver in Figure 1, and Figure 9 is a block diagram of a conventional serial data transmission device. . 10... central processing circuit (CPU), 14...
Read only memory (ROM), 15... Random access memory (RAM), 16... Parallel input/output board, 18... Encoder counter, 22... Multi knob, 23... Tuning knob, 24. ...RF gain knob, 25...Volume knob, 28...PLL control circuit, 29...Signal control circuit, 30...Filter control circuit, UIO, U20 to U26. U30. U31 or U
34...Shift register integrated circuit, Ull to U1
4...Serial human power PLL frequency synthesizer integrated circuit, INVI or INV2...Inno kuichita, ANDl
or AND4. ANDl! , AND12...and gate. Patent Applicant Furuno Electric Co., Ltd. Agent Patent Attorney Aohaku Ao and 2 others

Claims (2)

[Claims] (1) A data transmission device comprising a transmitting device that transmits configuration data for performing predetermined settings and reception designation data that specifies a receiving device that should receive the configuration data, and a plurality of receiving devices, the transmitting device a receiving means for receiving the setting data and the reception designation data transmitted from the receiver; and whether the reception designation data received by the reception means is reception designation data set in advance to be different for each receiving device. a detection means for detecting the data and outputting a detection signal when the reception designation data is the preset reception designation data; A data transmission device characterized in that each of the receiving devices described above is provided with a setting means for making settings. (2) receiving means for receiving setting data for performing predetermined settings and reception specification data specifying a receiving device that should receive the setting data; a detection means for detecting whether or not the data is the own reception designation data set in advance to be different from the above, and outputting a detection signal when the reception designation data is the preset reception designation data; and a detection signal output from the detection means. 1. A data transmission device comprising: a setting means for performing predetermined settings based on setting data received by the receiving means in response to the above.