JPH0447495B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a radio receiver. [Prior Art] Currently, under the Radio Station Operation Regulations, an ordinance of the Ministry of Posts and Telecommunications, frequencies for ship stations or coast stations for distress communications, emergency communications, and safety communications (hereinafter referred to as frequencies for distress communications, etc.) are defined in Article 52 of the Radio Law. 500kHz is assigned for telegraph and 2182kHz is assigned for telephone. Therefore, in conventional marine communication radio receivers, in order to be able to immediately set the receiving frequency to the emergency communication frequency in an emergency, the front panel of the radio receiver is set to the frequency for distress communication, etc. A special key is provided for this purpose. [Problems to be solved by the invention] Currently, the International Maritime Organization (hereinafter referred to as IMO)
FGMDSS (Future Global Maritime Destress)
and Safety System) are being considered.
According to the report on the progress of deliberations at the IMO's 30th Radio Communications Subcommittee, in the above-mentioned FGMDSS terrestrial communication medium-wave medium-distance service, the following 2MHz band emergency communication frequencies are used for the following communications: It is being considered to be used from ships to land, from ships to ships, and from land to ships. (1) 2187.5kHz…Digital selection call (DSC)
Distress alarm and safety call communication (2) 2182kHz...Distress communication and safety communication by wireless telephone (3) 2174.5kHz...Distress communication and safety communication by radio telephony (NBDP) In addition, frequencies around 500kHz are used for emergencies from land to ships. used for communications, specifically 490kHz marine broadcast service systems may be used for emergency communications, and 518kHz
The use of Hz frequencies to transmit navigational and weather warnings using the NAVTEX system is being considered and is already being implemented in some areas. Therefore, the frequency for distress communications, etc. used in FGMDSS is the current frequency of 500 kHz for distress communications, etc., as mentioned above.
It appears to be set close to 2182kHz. For example, the receiving frequency and radio wave format are stored in advance in a storage device and preset, and the receiving frequency is immediately set to the above-mentioned preset frequency by pressing a specified channel key or inputting a channel number using a numeric keypad. For wireless receivers with preset functions that can
By presetting the new emergency communication frequency being considered by IMO, the receiving frequency can be immediately set to the new emergency communication frequency. However, for wireless receivers that do not have a preset function, the receiving frequency may be set to the above FGMDSS.
There was a problem in that it was not possible to immediately set the frequency for distress communication, etc., which was newly established in 2015. The purpose of the present invention is to solve the above-mentioned problems, and to immediately change the receiving frequency from the currently set frequency for distress communications, etc. to the newly established frequency for distress communications, etc., which is close to the frequency. The purpose of the present invention is to provide a wireless receiver that can be configured according to the following conditions. [Means for Solving the Problems] The radio receiver according to the present invention has a specific frequency setting key, and when the specific frequency setting key is pressed, the receiving frequency is set to the first frequency for distress communication, emergency communication, or safety communication. and a first setting means for setting the frequency to a frequency, the upper frequency setting key is pressed after the upper frequency setting key, the lower frequency setting key, and the specific frequency setting key are pressed. In this case, the reception frequency is set to a frequency near the first frequency and higher than the first frequency. a second setting means for setting a second frequency for distress communication, emergency communication or safety communication; and when the lower frequency setting key is pressed after the specific frequency setting key is pressed, the reception frequency is set to a second frequency for distress communication, emergency communication or safety communication; The frequency is near the first frequency and lower than the first frequency. It is characterized by comprising a third setting means for setting a third frequency for distress communication, emergency communication, or safety communication. [Operation] With the above configuration, for example, the first frequency is a frequency for distress communication and safety communication.
2182kHz, the second frequency is 2187.5kHz, which is the frequency for distress alarm and safety call communication, and the third frequency is 2174.5kHz, which is the frequency for distress communication and safety call communication. At this time, when the specific frequency setting key is pressed, the receiving frequency is set to the first frequency by the first setting means. Further, when the upper frequency setting key is pressed after the specific frequency setting key is pressed, the reception frequency is set to the second frequency by the second setting means. Further, when the lower frequency setting key is pressed after the specific frequency setting key is pressed, the receiving frequency is set to the third frequency by the third setting means. Therefore, the receiving frequency can be immediately changed from the currently set frequency for distress communications, etc. to a newly established frequency for distress communications, etc. in the vicinity of the frequency set in the FGMDSS. [Embodiment] FIGS. 1 to 6 are block diagrams of a radio receiver having a receiving frequency of 0.1 MHz to 40 MHz, which is an embodiment of the present invention. The wireless reception of this embodiment has the following features. (1) Data regarding each rotation of the multi-knob 22, tuning knob 23, high-frequency gain knob (hereinafter referred to as RF gain knob) 24, and volume knob 25, as well as each data regarding the pressed keys 21, are stored in a central processing unit (hereinafter referred to as CPU). ) 10, and in response, the CPU 10 outputs each of the above data to the parallel input/output port 16. At this time, the parallel input/output port 16 outputs serial data SI including the above-mentioned data to the PLL control circuit 28, signal control circuit 29, and filter control circuit 30. Here, the serial data SI is received by each circuit 28, 29,
30, and each circuit 28, 29, 30 latches received data and performs predetermined processing only when receiving specific reception designation data assigned in advance to each circuit. (2) With the configuration described in (1) above, the shift amount of the passband shift is adjusted, the impedance matching with the antenna is adjusted, and the illumination intensity for the front panel LED 19 and signal level meter (hereinafter referred to as S meter) 68 is adjusted. adjustment, noise blanker gate 4
6, adjustment of the threshold level to start blanking, adjustment of the center frequency of the passband of the notch filter 52, adjustment of the signal level to stop each operation during seek, scan, and sweep to scan the reception frequency, and demodulation. One multi-knob 22 can be used to adjust the signal level of the line output that outputs the low frequency signal to an external device. (3) With the configuration described in (1) above, key 2 is used to set the receiving frequency of the radio receiver to the frequency for distress communications, etc. when using telegraph and telephone, respectively.
11, 212, and the key 21
1,212 and then press the Up key 219, the reception frequency is 518kHz and the radio wave type frequency shift keying (hereinafter referred to as
It's called FSK. ), the bandwidth of the bandpass filter used to pass only the desired signal around the reception frequency (hereinafter referred to as reception bandwidth) is 1kHz, and
It can be set to receive digital cell call signals with a reception frequency of 2187.5kHz and a radio wave type FSK with a reception bandwidth of 1kHz. Also, key 21
1, 212 and then the down key 217, the reception frequency is 490kHz and the radio wave type FSK broadcast service signal is received with a reception bandwidth of 1kHz, and the reception frequency is 2174.5K.
It can be set to receive telex signals in Hz and radio wave type FSK with a reception bandwidth of 1kHz. In FIG. 1, the radio signal received by the antenna 31 is transmitted to the antenna terminal 32, a of the switch K1.
side, and switch K through the a side of switch K2.
Connected to the common side of 3. The b side of switch K1 is connected to the b side of switch K2 via an attenuator 33. Here, the switches K1 and K2 are switched by the filter control circuit 30 in conjunction with each other. The a side of switch K3 is a band pass filter (hereinafter referred to as
It's called BPF. ) a of switch K8 via B11
connected to the side. The b side of switch K3 is connected to the common side of switch K4. The a side of the switch K4 is connected to the a side of the switch K7 via an impedance matching circuit 34 for matching the output impedance of the antenna 31 to the input impedance of the LPF 36 of the high frequency amplification section of the radio receiver. The impedance matching circuit 34 is, for example,
10 inductors connected in series between the input and output terminals of the circuit 34, 10 switches connected in parallel with each of the above inductors, and connected between the output terminal of the circuit 34 and ground. and a capacitor. Each switch in the impedance matching circuit 34 is a control drive circuit 3 that operates in response to matching setting data included in the serial data SI.
5 is turned on or off, thereby changing the inductance value of the circuit 34 and performing the impedance matching operation described above. By the coordinated switching of switches K5 and K6, any one of the eleven BPFs B1 to B10 is connected between the common side of switch K5 and the common side of switch K6. B1 is a BPF that only passes signals of 0.1 to 0.3MHz,
B2 is a BPF that passes only signals of 0.3 to 0.53 MHz, and B3 is a BPF that passes only signals of 0.53 to 1.6 MHz. Also, B4 is 1.6
B5 is a BPF that passes only signals of 2.4 to 2.4 MHz, B5 is a BPF that passes only signals of 2.4 to 3.6 MHz, and B6 is a BPF that passes only signals of 3.6 to 5.4 MHz. , furthermore, B7 is
BPF is a BPF that only passes 5.4 to 8 MHz signals, B8 is a BPF that only passes 8 to 12 MHz signals, B9 is a BPF that only passes 12 to 18 MHz signals, and B10 is a BPF that only passes 12 to 18 MHz signals.
This is a BPF that only passes 23MHz signals. The common side of switch K6 is connected to the b side of switch K7, and the common side of switch K7 is connected to switch K8.
The common side of the switch K8 is connected to the input terminal of a low pass filter (hereinafter referred to as LPF) 36 of the high frequency amplification section of this radio receiver. The switches K3 and K8, the switches K4 and K7, and the switches K5 and K6 are respectively operated in conjunction with each other by the filter control circuit 30. The signal input to the LPF 36 is input to the first mixer 38 via the high frequency amplifier 37 after unnecessary signals of 40 MHz or higher are removed. On the other hand, the first
A first local oscillation signal having a frequency of 80.555 to 120.455 MHz output from the local oscillator 100 is input to the first mixer 38 via the buffer amplifier 39 .
After multiplying the received signal input to the first mixer 38 and the first local oscillation signal, a first intermediate frequency signal is extracted, and the first intermediate frequency signal is transmitted to the post-amplifier 40,
and a second mixer 42 via an intermediate frequency amplifier 41
Output to. Here, the gain of the intermediate amplifier 41 is controlled by an automatic gain adjustment control (hereinafter referred to as AGC) DC voltage output from the DC amplifier 71. On the other hand, a second local oscillation signal with a frequency of 80 MHz output from the second local oscillator 120 is input to the second mixer 42 via the buffer amplifier 43. The second mixer 42 multiplies the input first intermediate frequency signal and the second local oscillation signal, extracts the second intermediate frequency signal, and transmits the second intermediate frequency signal to the post amplifier 44 and the buffer amplifier. 45. The signal output from the post-amplifier 44 is sent to a switch K via a noise blanker gate 46 and an intermediate frequency amplifier 48, which switch whether or not to pass the input signal.
It is output to the common side of 8. One side, buffer amplifier 45
extracts the noise component from the input signal, amplifies it, and then outputs it to the noise blanker control circuit 47. The noise blanker control circuit 47 controls the noise signal input from the buffer amplifier 45 to the signal control circuit 29.
When the threshold level data value NBV of the noise blanker inputted from is exceeded, the noise blanker gate 46 is switched from on to off. The switches K9 and K10 are switched in conjunction with each other by the signal control circuit 29, thereby controlling the four reception bandwidth selection BPFs B21 to B2.
One of the four BPFs is connected between the common side of switch K9 and the common side of switch K10.
Here, B21 is 6k around the reception frequency.
is a BPF with a receive bandwidth of Hz, and similarly,
B22 to B24 are 3kHz, 1kHz, respectively.
It is a BPF with a reception bandwidth of 0.2kHz. The second intermediate frequency signal output from the common side of the switch K10 is passed through the intermediate frequency amplifier 49 to the third intermediate frequency signal.
input to mixer 50. Third local oscillator 130
A third local oscillation signal of 380kHz±3kHz outputted from the third mixer 50 is inputted to the third mixer 50 via the buffer amplifier 51. The third mixer 50 receives the second
After multiplying the intermediate frequency signal and the third local oscillation signal and extracting the third intermediate frequency signal, it is output to the common side of the switch K11. Here, the intermediate frequency amplifier 49
The gain of the AGC output from the DC amplifier 71 is
Controlled by DC voltage. The a side of switch K11 is connected to the a side of switch K12, and the b side of switch K11 is connected to the b side of switch K12 via a notch filter 52 having a predetermined passband width. Here, the switches K11 and K12 are connected to the signal control circuit 2.
9. The third intermediate frequency signal output from the common side of the switch K12 is input to the buffer amplifier 54, the buffer amplifier 56, and the AGC detector 58 via the intermediate frequency amplifier 53, where the gain of the intermediate frequency amplifier 53 is is controlled by the AGC DC voltage output from the DC amplifier 71. The third intermediate frequency signal outputted from the buffer amplifier 54 is outputted to the a side of the switch K13 via a single sideband amplitude modulation signal (hereinafter referred to as SSB) demodulator 55 and a preamplifier 60. Further, the third intermediate frequency signal output from the buffer amplifier 56 is
A double sideband amplitude modulation signal (hereinafter referred to as DSB) is outputted to the b side of the switch K13 via a demodulator 57 and a preamplifier 61. On the other hand, the fourth local oscillation signal of 75kHz±6kHz output from the fourth local oscillator 140 is a beat frequency oscillation signal (hereinafter referred to as
This is called the BFO signal. ) is output to the SSB demodulator 55 via the buffer amplifier 72. The switch K13 is switched by the signal control circuit 29, and the demodulated low frequency signal output from the common side of the switch K13 is transmitted to the speaker 64 via the low frequency volume controller 62 and the low frequency amplifier 63.
It is output to the line output terminal 6 via a low frequency volume controller 65 and a low frequency amplifier 66.
7, and is output to the a side of switch K14. Here, the low frequency volume controllers 62 and 65 are connected to speaker output volume control data AFV and line output volume control data output from the signal control circuit 29.
Controls the amount of attenuation for each regulator in response to LINEG. Further, the low frequency signal outputted from the common side of the switch K13 is outputted to the AGC control circuit 59 via the AGC detector 69. The AGC detector 58 is
Envelope detection is performed on the input signal and the detection output is
It is output to the AGC control circuit 59. The AGC control circuit 59 includes on/off control of AGC output from the signal control circuit 29, and control of AGC high speed (FAST) and low speed (SLOW).
AGC control signal and high frequency gain control data
In response to the RFG, the detection output input from the AGC detector 56 and the detection output input from the AGC detector 69 are used to control the gain of the first intermediate frequency signal.
Generating an AGC DC voltage and an AGC DC voltage for gain control of the second and third intermediate frequency signals,
Each signal is output to DC amplifiers 70 and 71. Here, the AGC control circuit 59 controls the AGC DC voltage output to the DC amplifier 70 so that the gain of the intermediate frequency amplifier 41 increases in proportion to the value of the input high frequency gain control data RFG. Also,
The AGC control circuit 59 generates a level signal indicating the average level of the received signal from the detection output input from the AGC detector 58, and transfers the level signal to the comparator 7.
The signal is output to the inverting input terminal of switch K14, and is also output to the S meter 68 via the b side of switch K14.
Here, the switch K14 is switched by the signal control circuit 29. The scan stop threshold data SCANV output from the signal control circuit 29 is converted into a digital/analog converter (hereinafter referred to as D/A converter) 75.
After being A-converted, the signal is input to the non-inverting input terminal of the comparator 74. The comparator 74 sends an L-level scanning stop signal STOP to the parallel input/output port 16 when the level of the level signal input to the inverting input terminal exceeds the level of threshold data SCANV input to the non-inverting input terminal. Output. Next, referring to FIGS. 3 and 4, the first to fourth local oscillators 100, 120, 130, 140
The configuration of is explained below. In Fig. 3, reference oscillator 101, 10.24M
Hz signal is generated and the reference signal is passed through a phase locked loop circuit (hereinafter referred to as PLL) 102, PLL.
131, PLL 141, and mixer 111, and outputs to PLL via 1/5 frequency divider 103.
104. The PLL 1102 determines the frequency multiplication ratio based on data N1 and A1 input from the PLL control circuit 28.
A signal obtained by dividing the signal input from the prescaler 107 having a frequency of 16/17, and a 10.24MHz input signal.
The detected output is output as a phase control voltage to a voltage controlled oscillator (hereinafter referred to as VCO) 105 via an LPF having a predetermined cutoff frequency. The VCO 105 responds to the input phase control voltage from 80.555 to
The first local oscillation signal of 120.455MHz is output to the buffer amplifier 39 and mixer 106. mixer 106
is the input first local oscillation signal and BPF114
After multiplying the two signals by the signal input from the PLL 102 , a signal representing the difference in frequency between the two signals is extracted and outputted to the PLL 102 via the prescaler 107 . Here, PLL
The frequency division ratio NT1 of the entire PLL circuit by the prescaler 102 and the prescaler 107 is given by the following equation. NT1=16N1+A1...(1) Also, PLL102, VCO105, mixer 1
06 and a prescaler 107, a first local oscillation signal that changes in steps of 40 kHz is obtained. The PLL 104 determines the frequency multiplication ratio based on data N2 and A2 input from the PLL control circuit 28.
A signal obtained by frequency-dividing the signal input from the prescaler 109 having a frequency of 128/129 and a reference signal frequency-divided by 1/5 is phase-detected, and the detected output is sent to the VCO 108 via an LPF having a predetermined cut-off frequency.
output as a phase control voltage. VCO10
8 responds to the input phase control voltage from 44 to
The 48MHz signal is output to the mixer 111 via the 1/100 frequency divider 110, and the prescaler 1
09 to the PLL 104. here,
PLL with PLL104 and prescaler 109
The frequency division ratio NT2 of the entire circuit is given by the following equation. NT2=128N2+A2...(2) Also, by the circuit consisting of PLL104, VCO108, and prescaler 109,
Obtain the output signal of VCO 108 that changes in 1kHz steps. The mixer 111 multiplies the signal input from the frequency divider 110 by the 10.24MHz reference signal, and then
After extracting the signal of each frequency difference between both signals, the signal is passed through a BPF112 with a passband of 10.7±20kHz.
The output signal is output to mixer 113 via . mixer 113
multiplies the signal input from the BPF 112 and the second local oscillation signal of 80 MHz output from the second local oscillator 120, extracts the difference between the frequencies of both signals, and then converts the extracted signal to , passing frequency
The signal is output to the mixer 106 via the BPF 114 having a frequency of 69.28 to 69.32 MHz. The second local oscillator 120 generates a second local oscillation signal of 80 MHz, and mixer 113 and buffer amplifier 4
Output to 3. In FIG. 4, the 10.24MHz reference signal output from the reference oscillator 101 is connected to the PLL 131 and
It is input to PLL141. The PLL 131 determines the frequency multiplication ratio based on data N3 and A3 input from the PLL control circuit 28.
A signal obtained by frequency-dividing the signal input from the prescaler 133 having a frequency of 16/17 and the input reference signal is phase-detected, and the detected output is sent to the VCO 132 via an LPF having a predetermined cut-off frequency as a phase control voltage. Output. VCO132 responds to the input phase control voltage to 76MHz±0.6MHz
1/100 frequency divider 134 and 1/2 frequency divider 13
5 to the buffer amplifier 51 as a signal of 380 MHz ± 3 kHz, and the prescaler 13
3 to the PLL 131. here,
PLL with PLL131 and prescaler 133
The frequency division ratio NT3 of the entire circuit is given by the following equation. NT3=16N3+A3...(3) Also, by the circuit consisting of PLL131, VCO132, and prescaler 133,
It is possible to obtain the output signal of VCO 132 that changes in 5kHz steps. Therefore, a 25 Hz step signal can be obtained as the third local oscillation signal. The PLL 141 determines the frequency multiplication ratio based on data N4 and A4 input from the PLL control circuit 28.
A signal obtained by frequency-dividing the signal input from the prescaler 143 having a frequency of 16/17 and the input reference signal is phase-detected, and the detected output is sent to the VCO 142 via an LPF having a predetermined cut-off frequency, and is applied to a phase control voltage. Output as . VCO142 responds to the input phase control voltage to 75MHz±6MHz
1/100 frequency divider 144 and 1/10 frequency divider 1
45 to the buffer amplifier 72, 75MHz±6kHz
In addition to outputting it as a signal, prescaler 1
43 to the PLL 141. The frequency divider 145 is enabled and outputs the fourth local oscillation signal when the H level BFO signal output from the PLL control circuit 28 is input, and on the other hand, when the L level BFO signal is input. It is disabled and stops outputting the fourth local oscillation signal. Here, the frequency division ratio NT4 of the entire PLL circuit formed by the PLL 141 and the prescaler 143 is given by the following equation. NT4=16N4+A4...(4) Also, by the circuit consisting of PLL141, VCO142, and prescaler 143,
It is possible to obtain the output signal of the VCO 142 that changes in steps of 5 kHz.Therefore, it is possible to obtain a signal in steps of 5 Hz as the fourth local oscillation signal. In FIG. 5, a CPU 10 is a control circuit that controls the entire radio receiver, and receives a clock for CPU operation of a predetermined frequency from a clock generator 11, and operates in response to the clock. The CPU 10 includes a read-only memory (hereinafter referred to as ROM) 14 that stores programs and data for overall control of the wireless receiver via an address bus 12 and a data bus 13;
The power is backed up by battery B, and the receiving frequencies of any 400 channels within the receiving frequencies of the wireless receiver, the above-mentioned receiving frequency for emergency communication, and each setting data for each receiving frequency are stored, and the work of the CPU 10 is stored. A RAM 15 used as an area is connected. The CPU 10 also has a parallel input/output port 1 via an address bus 12 and a data bus 13.
6 and 17 are connected. The parallel input/output port 16 outputs clock SCK, serial data SI and latch signal RCK in response to instructions from CPU 10.
At the same time, setting data corresponding to the rotational positions of the RF gain knob 24 and volume knob 25 inputted from the analog/digital converter (hereinafter referred to as A/D converter) 26 is transferred to the CPU 10. In addition, the parallel input/output port 16
Scanning stop signal output from comparator 74 in the figure
When STOP is received, the signal STOP is sent to CPU10.
Transfer to. Here, each of the DC voltage output circuits of the RF gain knob 24 and the volume knob 25 outputs a predetermined DC voltage from the A/D converter 26 according to the rotational position of the knobs 24 and 25, respectively. In response, the A/D converter 26 converts the input DC voltage into 6-bit setting data for the knobs 24 and 25 and outputs it to the parallel input/output port 16. The parallel input/output port 17 takes in setting data by pressing various keys 21 on the front panel of the wireless receiver shown in FIG. 7, outputs the setting data onto the data bus 13, and displays various displays on the front panel. Data for driving a light emitting diode (hereinafter referred to as an LED) 19 is transmitted through a latch and an LED drive circuit 18.
Output to LED19. Here, the parallel input/output port 17 periodically enables the key scan circuit 20, and in response, the enabled key scan circuit 20 scans each key of the keys 21, and the data of the pressed key is transmitted to the parallel CPU via input/output port 17 and data bus 13
10 is output. As a result, data indicating whether or not the key 21 has been pressed is taken into the CPU 10. Further, an encoder counter 18 is connected to the CPU 10 via a data bus 13, and an output terminal of a pulse output circuit of the multi-knob 22 and an output terminal of a pulse output circuit of the tuning knob 23 are connected to the encoder counter 18. The multi-knob 2
When the tuning knob 2 or the tuning knob 23 is rotated, the phase of the pulse differs depending on the direction of rotation, and the pulse is output to the encoder counter 18 only during rotation. When a pulse is input from the pulse output circuit of the multi-knob 22 or the tuning knob 23, the encoder counter 18 outputs an interrupt signal IRQ to the CPU 10, and then outputs pulse data according to the phase and number of pulses and the multi-knob 22 or tuning. The identification data of the knob 23 is output to the CPU 10 via the data bus 13. When the CPU 10 receives the interrupt signal IRQ, it receives the pulse data and identification data from the encoder counter 18. The parallel input/output port 16 outputs the serial data SI together with the clock SCK to the PLL control circuit 28, signal control circuit 29, and filter control circuit 30, and then outputs the latch signal RCK when transmitting each data to be described in detail later. . The above serial data SI is transmitted to the control circuits 28, 29, 3 to be received.
0 contains 8-bit reception designation data indicating a shift register group, which will be described in detail later, and the number of bits varies depending on the received control circuits 28, 29, and 30, and can be 19 bits, 24 bits, or 16 bits. Consists of configuration data. This serial data
The SI format will be described in detail later with reference to FIG. As shown in FIG.
Segment LED 200a to 200g and 11
It has LEDs 201a to 201k, and
An LED 19 is provided at the top center of the front panel of the radio receiver. Further, a tuning knob 23 and a multi-knob 22 are rotatably provided at the center and right sides of the front panel of the radio receiver, respectively, and an RF gain knob 24 is provided at the front panel to the left of the tuning knob 23.
and a volume knob 25 are rotatably juxtaposed. Key 21 provided on the front panel of the wireless receiver
has a large number of keys as shown in FIG. In other words, 202a to 202f are radio wave types.
USB, LSB (hereinafter, SSB using the lower sideband is referred to as LSB)
That's what it means. ), telegraph (CW), FSK, facsimile (FAX), and DSB keys, and 203a to 203d are keys for passing the desired signal around the reception frequency.
This key is used to specify the reception bandwidth of Hz, 3kHz, 1kHz, and 0.2kHz. 204a to 204e, 205a to 205c, and 208 are keys by which predetermined adjustments, which will be described in detail later, can be made using the multi-knob 22. 204a becomes a passband shift key when a radio wave type other than telegraph (CW) is selected, and becomes a BFO key when telegraph (CW) is selected as a radio wave type. Here, passband shifting refers to pseudo-shifting the passing center frequency of a bandpass filter for intermediate frequency signals that determines the selectivity characteristics of a radio receiver, thereby eliminating interference. I can do it. When the passband shift key 204a is pressed when a radio wave type other than telegraph (CW) is selected, the amount of deviation of the passband shift can be changed by rotating the multi-knob 22. In this embodiment, the above path is changed by changing the setting data A1 or N1 and the setting data A4 or N4 so that the frequency of the first local oscillation signal and the frequency of the fourth local oscillation signal are respectively shifted by the same frequency. Achieves band shift. On the other hand, when the key 204a is pressed when telegraph (CW) is selected as the radio wave type, by rotating the multi-knob 22, the speaker 64
You can adjust the tone of the telegraph output from the. In this embodiment, setting data A4 or N4 is used to change the frequency of the fourth local oscillation signal.
The tone of the above telegram is changed by changing the . 204b is a filter key, and when the filter key 204b is pressed, switches K3 and K8 are activated.
is switched to the b side, and the switch K is switched to the b side.
4, K7 is switched to the a side, and the impedance matching circuit 34 is connected between the antenna 31 and the LPF 36 of the high frequency amplification section. Here, Multi Knob 2
By rotating 2, the matching setting data can be changed. 204c is a day marquee, and by pressing down the day marquee 204c and rotating the multi-knob 22, the illuminance of the LED 19 and the illuminance of the S meter 68 (not shown) can be controlled. 204d is a noise blanker key, and the noise blanker key 20
When 4d is pressed, noise blanker control circuit 4
7 is enabled, and by rotating the multi-knob 22, the level of the noise signal for blanking can be adjusted. 204e is a notch filter key, and when the notch filter key 204e is pressed, switches K11 and K12 are respectively switched from the a side to the b side, and attenuate only specific frequency components within the reception bandwidth including the reception frequency. Notsuchi Filter 5
2 is connected between the third mixer 50 and the intermediate frequency amplifier 53. By rotating the multi-knob 22, the center frequency of the notch filter 52 can be shifted in a pseudo manner, thereby making it possible to eliminate, for example, beat interference. In this embodiment, the frequency of the third local oscillation signal and the frequency of the fourth local oscillation signal are
By changing the setting data A3 or N3 and the setting data A4 or N4 so as to shift the frequency of the local oscillation signal by the same frequency, the center frequency of the notch filter 52 can be changed. Note that the key 22a is a hold key, and when the hold key 22a is pressed, even if the multi-knob 22 is rotated, the multi-knob 2
The second pulse output circuit does not output pulses, thereby disabling the function of the multi-knob 22 and retaining the data set by the multi-knob 22. Furthermore, keys 204b, 202b, 203b,
204c, 202c, 203c, 204d, 20
2d, 203d, and 202e constitute a numeric keypad, and when predetermined data is input using the numeric keypad, the key 203a is used as an enter key to transfer the data input using the numeric keypad to the CPU 10. It will be done. 205a is a seek key;
5a and then press the up key 219 or the down key 217 to continuously change the reception frequency upward or downward, respectively, and turn the multi-knob 22 to raise the signal level above the scan stop threshold set. When received, scanning by the seek is stopped. 205b is a scan key, and after pressing the scan key 205b and inputting a predetermined group number in the channel previously registered in the RAM 15 using the numeric keypad, the enter key 203 is pressed.
When pressing a, the reception frequency is scanned between each channel in the registered group. At this time, as in the case of seek above, multi knob 2
When a signal level equal to or higher than the scan stop threshold set by rotating the switch 2 is received, the scan is stopped. 205c is a sweep key, and after pressing the sweep key 205c and inputting the group number which is a group of the lower end frequency, upper end frequency, and step frequency at the time of scanning registered in advance in the RAM 15 using the numeric keypad, press the enter key. key 2
When pressing 03a, the reception frequency is scanned using the frequency specified within the registered group. At this time, as in the case of seek and scan described above, when a signal level equal to or higher than the scan stop threshold set by rotating the multi-knob 22 is received, the scan by the sweep is stopped. 208 is a line key, and the line key 20
When 8 is pressed, the switch K14 is switched from the b side to the a side, and the display on the S meter becomes the display of the signal level output to the line output terminal 67. At this time, by rotating the multi-knob 22 while pressing the key 218, the line output volume control data LINEG can be changed, thereby changing the amount of attenuation of the low frequency volume adjuster 65. The signal level of the line output output to the line terminal 67 can be changed. 206a is a key for turning off AGC, 206b is a key for setting high speed (FAST) AGC, and 206c is a key for setting low speed (SLOW).
This is the key to configure AGC. 207 is
This is a key for interlocking the switches K1 and K2 to switch from the a side to the b side and inserting the attenuator 33 into the input terminal of the radio receiver. 210 is a fine key for setting fine adjustment of tuning using the tuning knob 23;
is the reception frequency for telephone distress communications, etc.
This is the key to set the reception frequency to 2182kHz, and 212 is the frequency for distress communication, etc.
This is the key to set it to 500kHz, and in addition,
A lock key 213 is used to hold the set reception frequency after the reception frequency is set using the key 210 and the tuning knob 23 or the keys 211 and 212. 214 is a channel key;
By pressing , inputting a channel number using the numeric keypad, and then pressing the enter key 203a, the reception frequency can be set to the frequency of the input channel registered in advance in the RAM 15. 215 is a frequency key,
By pressing this key, enter the reception frequency using the numeric keypad, and then press the enter key 203.
By pressing a, you can set any frequency. Reference numeral 216 is a memory key, which is used to set the receiving frequency using the operations described above, as well as setting the radio wave type, setting the receiving bandwidth, setting AGC, setting whether to insert the attenuator 33, and setting the impedance matching circuit 3.
4 and setting the matching setting data in the impedance matching circuit 34 (hereinafter, the setting data for the above seven items other than the reception frequency is referred to as preset data). Press the memory key 216, use the numeric keypad to enter the channel number in which the received frequency and preset data are registered, and press the enter key 203.
By pressing a, the receiving frequency and the preset data are stored in the RAM 15 at a predetermined address corresponding to the channel. 217 is a down key for changing the currently set channel or reception frequency to a channel with a smaller channel number or a lower frequency. Reference numeral 218 is a function key for performing a predetermined additional function when setting a channel or reception frequency or setting matching setting data in the impedance matching section 3. 219 is
This is the Up key to change the currently set channel or reception frequency to a channel with a larger channel number or a higher frequency. In FIG. 6, the clock SCK output from the parallel input/output port 16 is the clock SCK output from the PLL control circuit 2.
SCK terminal of Toshiba Electric Co., Ltd. TC74HC595P type 8-bit shift register integrated circuit U10 in 8,
It is input to each CLOOK terminal of four serial input PLL frequency synthesizer integrated circuits U11 to U14 of Motorola MC145156P type, and
of integrated circuit U10 via inverter INV1.
Input to RCK pin. Here, integrated circuit U1
1 to U14 each include a 7-bit shift register, a 10-bit shift register, and a 2-bit shift register, providing a total of 19-bit shift registers. The clock SCK is also applied to each of the seven shift register integrated circuits U20 to U26 of the TC74HC595P type in the signal control circuit 29.
It is input to the SCK terminal of the TC74HC595P type shift register integrated circuit U30 in the filter control circuit 30, and the four 8-bit shift register integrated circuits of the Mitsubishi Electric M54975 type in the filter control circuit 30. It is input to each clock input terminal T of U31 to U34. The clock SCK is inputted to the RCK of the integrated circuit U30 via the inverter INV2. Serial data SI output from the parallel input/output port 16 is input to the SI terminal of the integrated circuit U10, the SI terminal of the integrated circuit U20, and the SI terminal of the integrated circuit U30. Furthermore, the latch signal RCK output from the parallel input/output port 16 is applied to the AND gate AND1 or AND gate in the PLL control circuit 28.
4, and is also input to the RCK terminal of the integrated circuit U20 in the signal control circuit 29. Further, the above latch signal is applied to the AND gate AND11 in the filter control circuit 30 and
It is input to each second input terminal of AND12. In the PLL control circuit 28, each output terminal of QE, QF, QG, and QH of the shift register integrated circuit U10 is connected to an AND gate AND1 or an AND gate, respectively.
4, each second input terminal of the integrated circuit U
The 10 QH' data output terminals are the respective data input terminals of the shift register integrated circuits U11 to U14.
Connected to DATA. Each output terminal of the AND gates AND1 to AND4 is connected to each ENABLE of the shift register integrated circuits U11 to U14, respectively.
Connected to the terminal. Integrated circuits U11 to U14
The data output terminals of PLL102 and
PLL104, PLL131, and PLL1
41 and an enable terminal of the frequency divider 145. In the signal control circuit 29, the QC output terminal of the shift register integrated circuit U20 is connected to each RCK input terminal of integrated circuits U24 to U26, and the QD output terminal of integrated circuit U20 is connected to each RCK input terminal of integrated circuits U21 to U23. be done. The QH' output terminal of integrated circuit U20 is connected to each SI terminal of integrated circuits U21 and U24. Integrated circuit U21
The QH' output terminal of integrated circuit U22 is connected to the SI input terminal of integrated circuit U22, and the QH' output terminal of integrated circuit U22 is connected to the SI input terminal of integrated circuit U23. The QH' output terminal of integrated circuit U24 is connected to the SI input terminal of integrated circuit U25, and the QH' output terminal of integrated circuit U25 is connected to the SI input terminal of integrated circuit U26. In the filter control circuit 30, the integrated circuit U3
The QA output terminal of 0 is connected to the first input terminal of the AND gate AND12, and the QB output terminal of the integrated circuit U30
The output terminal is connected to the first input terminal of the AND gate AND11. The output terminal of the AND gate AND11 is each LATCH of the integrated circuits U31 and U32.
The output terminal of the AND gate AND12 is connected to each LATCH terminal of the integrated circuits U33 and U34. The QH' output terminal of integrated circuit U30 is connected to each SIN input terminal of integrated circuits U31 and U33, the SOUT output terminal of integrated circuit U31 is connected to the SIN input terminal of integrated circuit U32, and the SOUT output terminal of integrated circuit U33 is Integrated circuit U34
Connected to the SIN input terminal of Integrated circuit U31
The QA and QC to QG output terminals and the QA to QF and QG output terminals of the integrated circuit U32 are connected to a switching control circuit SC which switches the switches K1 to K8. QD or integrated circuit U33
The QH output terminal as well as the QD or QH output terminal of integrated circuit U34 are connected to the data input terminal of control drive circuit 35. As is well known, the shift register integrated circuits U10, U20 to U26, and U30 read the data input from the SI terminal into the internal shift register at the rising edge of the clock SCK, and then
At the rising edge of the latch signal RCK, the read data is latched and the output terminals QA or QH are
Output to QH′. The above integrated circuits U11 to U1
4, as is well known, is input to the internal shift register at the rising edge of the clock input to the CLOCK pin.
After reading the data input from the DATA terminal, the latch signal input to the ENABLE terminal goes high.
The data read at the level (logic level "1") is latched and output to the data output terminal.
The above shift register integrated circuits U31 to U34
As is well known, after the data input from the SIN terminal is read into the internal shift register at the rising edge of the clock input to the T terminal, the latch signal input to the LATCH terminal becomes H level (“1” at logic level). ”), the data read is latched and output to the QA or QH output terminal. As shown in FIG. 8, the serial data SI includes one or more shift registers (hereinafter referred to as a shift register group) that should receive configuration data.
It consists of 8-bit reception designation data b1 to b8 that specify the , 29, 30. Note that in FIG. 8, "-" indicates an empty bit. In the PLL control circuit 28, the integrated circuit U10
The serial data SI input to the SI input terminal of
Each data input terminal of the integrated circuits U11 to U14 is connected via the QH' output terminal of the integrated circuit U10.
Input to DATA. Integrated circuit U10 is a shift register for latching 8-bit reception designation data b1 to b8. The four integrated circuits U11 to U14 each include a shift register for receiving the 19-bit setting data, and each of the integrated circuits U11 to U14 independently
The shift register groups G1 to G4 are configured. A to D in FIG. 8 are format diagrams showing data to be received by the shift register groups G1 to G4 corresponding to the integrated circuit U10 and the integrated circuits U11 to U14, respectively. The data consists of 8-bit reception designation data b1 to b8 and 19-bit setting data b9 to b27. In A and B of Fig. 8, A1, N1, A2
and N2 are 7-bit, 10-bit, 7-bit, and 10-bit setting data for changing the frequency of the first local oscillation signal, respectively, and data A1 and N1 are input from the integrated circuit U11 to the PLL 102.
data A2 and N2 are output to the integrated circuit U12.
The signal is output from the PLL 104 to the PLL 104. In C of FIG. 8, A3 and N3 are 7 bits and 10 bits, respectively, for changing the frequency of the third local oscillation signal.
Each bit setting data, data A3, N3
is output from the integrated circuit U13 to the PLL 131. In D of FIG. 8, A4 and N4 are respectively 7-bit and 10-bit setting data for changing the frequency of the fourth local oscillation signal,
Data A4, N4 is from integrated circuit U14 to PLL
141. Further, bit b27 of D in FIG. 8 is a bit that controls whether or not the frequency divider 145 is enabled. In the signal control circuit 29, an integrated circuit U20 is a shift register for latching 8-bit reception designation data. In addition, each three integrated circuits U
21 to 23 and U24 to 26 constitute shift register groups G5 and G6, respectively, for latching 24-bit setting data.
E and F in FIG. 8 are format diagrams showing data to be received by shift register groups G5 and G6, respectively, and serial data S1 in each E and F in FIG. 8 are 8-bit reception designation data b1 to b1. b8 and 24-bit setting data b9 to b32
It consists of Here, 8 of E and F in Figure 8
Bit setting data b9 to b16 are latched by integrated circuits U21 and U24, and 8-bit setting data b17 to b24 are latched by integrated circuits U22 and U24.
25, 8-bit setting data b25
to b32 are latched by integrated circuits U23 and U26. In E of FIG. 8, b15 and b16 are S
Switch K that changes the output signal to meter 68
This is control data for switching 14 to side a or side b, and b17 to b22 are 6-bit line output volume control data LINEG. In addition, in E of FIG. 8, b25 to b30 are 6-bit speaker output volume control data AFV,
b31 and b32 are the SSB demodulator 55 or DSB
This is control data for switching the switch K13 to the a side or the b side in order to switch and output the output of the demodulator 57 to the low frequency volume controller 62. 8th
In F of the figure, b9 to b12 are 4-bit scan stop threshold data SCANV, and b14
is control data for interlocking the switches K11 and K12 to switch to the a side or the b side to switch whether or not to insert the notch filter 52. Also, in F of Fig. 8, b15 and b16 are
This is control data for setting AGC off and AGC high speed (FAST) of AGC control, and b17 to b22 are 6-bit high frequency gain control data RFG.
It is. Furthermore, in F of FIG. 8, b25 to b28 are control data for switching switches K9 and K10 for switching the reception bandwidth, and b29 to b32 are 4-bit noise blanker control threshold data NBV. be. In the filter control circuit 30, the integrated circuit U3
0 is a shift register for latching 8-bit reception designation data. Further, two integrated circuits U31 and U32 and two integrated circuits U33 and U34 constitute shift register groups G7 and G8 for latching 16-bit setting data, respectively. G and H in FIG. 8 are format diagrams showing data to be received by shift register groups G7 and G8, respectively, and the serial data of each G and H in FIG. 8 is 8-bit reception designation data b1 to b8. and 16-bit setting data b9 to b2
Consists of 4. Here, 8-bit setting data b9 to b16 of G and H in FIG. 8 are latched by integrated circuits U31 and U33, and 8-bit setting data b17 to b24 are latched by integrated circuits U32 and U33.
It is latched at 34. In G of FIG. 8, b9 is control data for switching switches K1 and K2 in conjunction to switch whether or not to insert the attenuator 33;
11 to b15 and b17 to b22 are control data for inserting any one BPF of BPF B1 to B11 by switching switches K3 to K8, and b23 is control data for inserting any one BPF from BPF B1 to B11 by switching switches K3 to K8.
This is control data for switching whether or not to insert 4. Further, in H of FIG. 8, b21 to b16 and b20 to b24 are matching setting data for setting the inductance value by switching 10 switches in the impedance matching circuit 34. Regarding the operation of the radio receiver configured as described above, in particular, the parallel input/output port 16 and the PLL
The operation of serial data transmission between the control circuit 28, signal control circuit 29, and filter control circuit 30 will be explained. For example, when the operator rotates the tuning knob 23 to change the receiving frequency, the tuning knob 23 in FIG.
A predetermined pulse is output from the pulse output circuit to the encoder counter 18, and in response, the encoder counter 18 sends an interrupt signal IRQ to the CPU 1.
0, and also outputs data regarding the pulse to the CPU 10 via the data bus 13. At this time, the CPU 10 calculates the reception frequency corresponding to the rotation of the tuning knob 23 from the current reception frequency data stored in the RAM 15 and the input data, and calculates the reception frequency corresponding to the calculated reception frequency. Setting data A1 to A3 and N1
After calculating N3, the data is output to the parallel input/output port 16. In response to this, the parallel input/output port 16
First, along with the 27-bit clock SCK, the 8th
The 27-bit serial data S1 including the setting data A1 and N1 in the signal format A in the figure is sent to b2.
After sending out the signals in the order of 7...b1, the latch signal RCK, which is one pulse at H level, is sent out. on the other hand,
In the PLL control circuit 28, since the inverted signal of the clock SCK is input to the RCK input terminal of the integrated circuit U10 as described above, when the transmission of the serial data S1 is finished, the QH of the integrated circuit U10 is
Only the terminal becomes H level. Then the latch signal
When RCK is input to the second input terminal of the AND gate AND1, the AND gate AND1 outputs an H level signal to the ENABLE terminal of the integrated circuit U11. With this, shift register group G
The 19-bit setting data input to the integrated circuit U11 corresponding to PLL 102 is latched, and the setting data A1 and N1 included in the setting data
is output to. At this time, b1 to b7 of the serial data S1 are all "0", so
Serial data S1 input to each shift register of other shift register groups G2 to G8
is not latched. Next, the parallel input/output port 16 transfers and latches the setting data A2 and N2 in the signal format B in FIG. 8 to the integrated circuit U12, as described above, and also transfers the setting data A2 and N2 in the signal format C in FIG. Data A3 and N3 are integrated into the integrated circuit U13.
Transfer it to and latch it. This allows setting data A2 and N2 to be transferred from the integrated circuit U12 to the PLL.
104, and setting data A3 and N3 are transferred from the integrated circuit U13 to the PLL 131. As above, the setting data A1, N1, A2, N
2 and A3, N3 are each PLL102, 104, 1
31, the frequencies of the first and third local oscillation signals are changed, thereby changing the receiving frequency. Also, when setting the setting data A4 and N4, the serial data S is set in the signal format D in Fig. 8.
1, when changing the matching setting data of the impedance matching circuit 34, and when sending serial data S in the G or H signal format shown in FIG. transmits serial data S in the signal format A in FIG. 8 described above, and in response, each control circuit 28.3
0 works similarly. Furthermore, for example, in order for the operator to change the volume of the demodulated signal output from the speaker 64,
When the volume knob 25 is rotated, a DC voltage of a predetermined voltage corresponding to the rotational position of the knob 25 is transmitted from the DC voltage output circuit of the volume knob 25 in FIG. 5 to the parallel input/output port via the A/D converter 26. In response, the parallel input/output port 16 outputs 6-bit speaker output volume control data AFV, which is the A/D converted DC voltage data, to the CPU 10. In response, the CPU 10 instructs the parallel input/output port 16 to transfer the data AFV to the signal control circuit 29. In response to this, the parallel input/output port 16
First, after sending out 8-bit L-level serial data S together with the 8-bit clock SCK, a latch signal, which is one H-level pulse, is sent.
Send RCK. As a result, 8-bit data "00000000" is latched in shift register integrated circuits U10, U20, and U30, and each integrated circuit U
L level signals with data "0" are output from each QA or QH output terminal of 10, U20, and U30, and as a result, each of the control circuits 28 and 2
9 and 30 are reset. Next, the parallel input/output port 16 sends out 32-bit serial data S including the speaker output volume control data AFV in the order of b32...b1 in the signal format E in FIG. 8 along with the 32-bit clock SCK. , sends out a latch signal RCK, which is one pulse at H level. On the other hand, in the signal control circuit 29, b of the reception designation data b1 to b8
4 is "1", so at the end of sending out the serial data S1, the integrated circuit U20
Only the QD terminal becomes H level, and the H level signal is input to the RCK terminals of integrated circuits U21 to U23. As a result, the 24-bit setting data b9 to b32, excluding the above reception designation data, input to the integrated circuits U21 to U23 corresponding to the shift register group G5 are latched, and the speaker output volume control data included in the setting data is latched.
AFV is output to low frequency volume controller 62.
In response, the low frequency volume controller 62 attenuates the low frequency signal output from the common side of the switch K13 by an amount of attenuation corresponding to the input data AFV. As a result, the volume of the demodulated low frequency signal output from the speaker 64 is adjusted. Furthermore, the transfer of data other than data AFV in E of FIG. 8 and each data in F of FIG. 8 is performed in the same procedure as the above-described transfer of data AFV. As explained above, parallel input/output port 1
6 to each control circuit 28, 29, 30, the serial data S to be transmitted
includes reception designation data b1 to b8 for designating the shift register groups G1 to G8 to be received and each of the predetermined setting data, and the reception designation data is the same as the own reception designation data set in advance. When the latch signal is input, the shift registers belonging to the shift register group perform a latch operation. Therefore, as shown in FIG.
, and the latch signal RCK can be transferred from the parallel input/output port 16 to each shift register of the desired shift register groups G1 to G8 and latched using only three data lines. be. Furthermore, the operation and operation when setting the reception frequency in the above-mentioned radio receiver to the current communication frequency and the above-mentioned FGMDSS communication frequency for distress communication, etc. will be explained. Note that the data on the radio wave formats and telegraph bandwidths shown in Table 1 corresponding to the communication frequencies for each of the above-mentioned distress communications, etc. are stored in advance in the ROM 14 as preset data. (1) When setting the frequency for telephone distress communication, etc. to 2182 kHz In this case, when the 2182 kHz setting key 211 is pressed, the CPU 10 uses the method described above to set the 2182 kHz setting key 211.
Data indicating that 11 has been pressed is taken in from the key 21 in FIG. 5 via the parallel input/output port 17 and the data bus 13. At this time,
The CPU 10 uses the above setting data A1 to A3 and N1 to N corresponding to the receiving frequency of 2182kHz.
3, and outputs the data to the parallel input/output port 16. At the same time, data regarding the radio wave format and reception bandwidth corresponding to the frequency 2182kHz stored in advance in the ROM 14 is read out, and the data is output to the parallel input/output port 16. Forward. In response to this, parallel input/output port 16
First, along with the 27-bit clock SCK,
Setting data A in signal format A in Figure 8.
27-bit serial data S including 1 and N1
are sent to the PLL control circuit 28 in the order of b27...b1, and then a latch signal RCK, which is one pulse at H level, is sent to the PLL control circuit 28.
Next, the parallel input/output port 16 similarly receives setting data A2, N2, A3, and N3.
The signal is sent to the PLL control circuit 28. In response, the PLL circuit 28 transfers the received setting data A1 and N1, A2 and N2, A3 and N3 to the PLL102, PLL104, and PLL1, respectively.
Output to 31. At this time, the first local oscillator 1
The 00 and third local oscillators 130 generate first and third local oscillation signals in response to the setting data, thereby setting the reception frequency to 2182kHz. Further, the parallel input/output port 16 sends out 8-bit L-level serial data S together with an 8-bit clock SCK, and then sends out a latch signal RCK, which is one H-level pulse, to control the control circuit described above. The reset operation for 28 to 30 is performed. Next, the parallel input/output port 16 receives the 32-bit clock SCK as well as bit b31 of "1" and bit b32 of "0" in the signal format E in FIG.
After sending the serial data S1 containing the serial data S1 to the signal control circuit 29 in the order of b32...b1, the latch signal RCK, which is one pulse at H level, is sent to the signal control circuit 29. In addition, the parallel input/output port 16 receives the 32-bit clock SCK as well as the bit b25 of "1000" indicating the reception bandwidth of 6 kHz in the signal format F in FIG.
Serial data S including b28 to b3
2...After sending it to the signal control circuit 29 in the order of b1, the latch signal, which is one H level pulse, is sent to the signal control circuit 29 in the order of b1.
RCK is sent to the signal control circuit 29. The signal control circuit 29 switches the switch K13 to the b side in response to the data regarding the received radio wave format and reception bandwidth, and also switches the switch K13 to the b side.
Switches K9 and K10 are switched such that 21 is inserted between each common side of switches K9 and K10. By the above operation, the receiving frequency becomes 2182kHz.
In addition, the radio wave format and reception bandwidth are set to DSB and 6kHz, respectively, and reception is possible with the above settings. (2) When setting the frequency to 500 kHz for distress communications, etc. In this case, when the 500 kHz setting key 212 is pressed, the CPU 10 uses the above-mentioned method to set the frequency to 500 kHz.
Data indicating that 12 has been pressed is taken in from the key 21 in FIG. 5 via the parallel input/output port 17 and the data bus 13. At this time,
The CPU 10 uses the above setting data A1 to A3 and N1 to N corresponding to the reception frequency of 500kHz.
3 and outputs the data to the parallel input/output port 16, and reads out data regarding the radio wave format and reception bandwidth corresponding to the frequency of 500 kHz stored in advance in the ROM 14, and outputs the data to the parallel input/output port 16. Forward. In response to this, parallel input/output port 16
transmits the above setting data and data regarding the radio wave format and reception bandwidth to the PLL control circuit 2.
8 and the signal control circuit 29 in the same manner as described above. As a result, as described above, the receiving frequency is set to 500kHz, and the radio wave format and receiving bandwidth are set to the radio wave format and receiving bandwidth corresponding to the receiving frequency shown in Table 1. , reception is possible with the above settings. (3) When setting the frequency for distress communication, etc. for the Navitex system in FGMDSS to 518kHz In this case, after pressing the 500kHz setting key 212, pressing the Up key 219 will cause the CPU
10 sequentially takes in data indicating that the key 212 and the key 219 have been pressed from the key 21 in FIG. 5 via the parallel input/output port 17 and the data bus 13 using the method described above.
At this time, the CPU 10 stores the above setting data A1 to A4 and N corresponding to the receiving frequency of 518kHz.
1 to N4, outputs the data to the parallel input/output port 16, and also outputs the data to the parallel input/output port 16.
The data regarding the radio wave format and reception bandwidth corresponding to the frequency 518 kHz stored in advance in 4 is read out, and the data is transferred to parallel input/output port 16.
Transfer to. In response, the parallel input/output port 16 transfers the setting data and data regarding the radio wave format and reception bandwidth to the PLL control circuit 28 and signal control circuit 29 in the same manner as described above. As a result, the reception frequency is set to 518kHz, and the radio wave format and reception bandwidth are set to the radio wave format and reception bandwidth corresponding to the reception frequency shown in Table 1, as described above. , reception is possible with the above settings. (4) When setting the frequency to 490 kHz for distress communication, etc. for the ship broadcasting service system in FGMDSS In this case, after pressing the 500 kHz setting key 212, pressing the down key 217 will cause the CPU
10 sequentially takes in data indicating that the key 212 and the key 217 have been pressed from the key 21 in FIG. 5 via the parallel input/output port 17 and the data bus 13 using the method described above.
At this time, the CPU 10 stores the above setting data A1 to A4 and N corresponding to the receiving frequency of 490kHz.
1 to N4, outputs the data to the parallel input/output port 16, and also outputs the data to the parallel input/output port 16.
The data regarding the radio wave format and reception bandwidth corresponding to the frequency 490kHz stored in advance in
Transfer to. In response, the parallel input/output port 16 transfers the setting data and data regarding the radio wave format and reception bandwidth to the PLL control circuit 28 and signal control circuit 29 in the same manner as described above. As a result, the reception frequency is set to 490kHz, and the radio wave format and reception bandwidth are set to the radio wave format and reception bandwidth corresponding to the reception frequency shown in Table 1. , reception is possible with the above settings. (5) When setting the frequency to 2187.5 kHz for distress communications, etc. for distress alerts and safety calls using digital selective call (DSC) in FGMDSS.
10 sequentially takes in data indicating that the key 211 and the key 219 have been pressed from the key 21 in FIG. 5 via the parallel input/output port 17 and the data bus 13 using the method described above.
At this time, the CPU 10 has a reception frequency of 2187.5kHz.
The above setting data A1 to A4 and N1 to N4 corresponding to
The data regarding the radio wave format and reception bandwidth corresponding to the frequency 2187.5 kHz stored in advance in the 14 is read out, and the data is transferred to the parallel input/output port 16. In response, the parallel input/output port 16 transmits the above setting data and data regarding the radio wave format and reception bandwidth.
The data is transferred to the PLL control circuit 28 and signal control circuit 29 in the same manner as described above. As a result, as described above, the receiving frequency is set to 2187.5kHz, and the radio wave format and receiving bandwidth are set to the radio wave format and receiving bandwidth corresponding to the receiving frequency shown in Table 1. and can be received with the above settings. (6) When setting the frequency for distress communication, etc. to 2174.5kHz for distress communication and safety communication by radio telex (NBDP) in FGMDSS In this case, after pressing the 2182kHz setting key 211 and pressing the down key 217, the CPU
10 sequentially takes in data indicating that the key 211 and the key 217 have been pressed from the key 21 in FIG. 5 via the parallel input/output port 17 and the data bus 13 using the method described above.
At this time, the CPU 10 has a reception frequency of 2174.5kHz.
The above setting data A1 to A4 and N1 to N4 corresponding to are calculated, and the data are output to the parallel input/output port 16, and
The data regarding the radio wave format and reception bandwidth corresponding to the frequency 2174.5 kHz stored in advance in the 14 is read out, and the data is transferred to the parallel input/output port 16. In response, the parallel input/output port 16 transmits the setting data and data regarding the radio wave format and reception bandwidth.
The data is transferred to the PLL control circuit 28 and signal control circuit 29 in the same manner as described above. As a result, as described above, the receiving frequency is set to 2174.5kHz, and the radio wave format and receiving bandwidth are set to the radio wave format and receiving bandwidth corresponding to the receiving frequency shown in Table 1. and can be received with the above settings. As explained above, 500kHz setting key 21
After pressing the 2 or 2182 kHz setting key, press the up key 219 or down key 217 to set the reception frequency to the frequency for distress communication etc. established in the above FGMDSS, and set the radio wave format and reception bandwidth to the frequency specified in the above FGMDSS. It is possible to set the radio wave format and reception bandwidth corresponding to the frequency for communication, etc., and reception is possible in the above setting state. Therefore, the receiving frequency is FGMDSS
It has the advantage that it can be set immediately and with a simple operation to the frequency for distress communications etc. established in 2013.

[Table] [Effects of the Invention] As detailed above, according to the present invention, when the specific frequency setting key is pressed, the receiving frequency is set to the first frequency for distress communication, emergency communication, or safety communication. In the wireless receiver equipped with the setting means 1, when the upper frequency setting key is pressed after the specific frequency setting key is pressed, the receiving frequency is set to a value near the first frequency and the first frequency. The frequency is higher than the frequency. a second setting means for setting a second frequency for distress communication, emergency communication or safety communication, and when a lower frequency setting key is pressed after the specific frequency setting key is pressed;
third setting means for setting the reception frequency to a third frequency for distress communication, emergency communication or safety communication, which is a frequency near the first frequency and lower than the first frequency; For example, the first frequency is set to 2182kHz, which is the frequency for distress communication and safety communication, and the second frequency is set to 2182kHz, which is the frequency for distress communication and safety communication.
This is the frequency for distress alert and safety call communication.
2187.5kHz, and the third frequency is set to 2174.5kHz, which is the frequency for distress communications and safety communications, to move the receiving frequency above or below the currently set frequency for distress communications, etc. It is said that it is possible to immediately change and set the frequency for distress communication, etc., which is newly established in the FGMDSS, and the communication operation for changing the receiving frequency can be simplified compared to the conventional example. There are advantages.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a signal processing section of a radio receiver that is an embodiment of the present invention, and FIG. 3 is a block diagram of the first and second local oscillators of the radio receiver of FIG. Figure 4 is a block diagram of the third and fourth local oscillators of the radio receiver in Figure 1, and Figures 5 and 6.
Figure A: A block diagram of the control section of the radio receiver in Figure 1.
7 is a front view of the front panel of the radio receiver of FIG. 1, and FIG. 8 is a signal format diagram of data transmitted by the radio receiver of FIG. 1. 10...Central processing circuit (CPU), 14...
Read-only memory (ROM), 15...Random access memory (RAM), 16...Parallel input/output port, 18...Encoder counter, 2
2... Matsushi knob, 23... Tuning knob, 24...
RF gain knob, 25...Volume knob, 28
... PLL control circuit, 29 ... Signal control circuit, 3
0...Filter control circuit, 31...Antenna, 3
4... Impedance matching circuit, 35... Control drive circuit, 37... High frequency amplifier, 38... First mixer, 41, 48, 49, 53... Intermediate frequency amplifier, 55... SSB demodulator, 57... ...DSB demodulator,
62, 65...Low frequency volume adjuster, 63, 66...
...Low frequency amplifier, 64...Speaker, 100...
First local oscillator, 120...Second local oscillator, 1
30...Third local oscillator, 140...Fourth local oscillator, 211...2182kHz setting key, 212...
500kHz setting key, 217...Down key, 21
9...Up key, K1 or K14...Switch, U10, U20 or U26, U30, U3
1 to U34...shift register integrated circuit, U
11 to U14...Serial input PLL frequency synthesizer integrated circuit, INV1 to INV2...
...Inverter, AND1 or AND4, AND1
1, AND12...and gate.

Claims (1)

[Claims] 1. A specific frequency setting key, and a first setting means for setting the receiving frequency to a first frequency for distress communication, emergency communication, or safety communication when the specific frequency setting key is pressed. In the wireless receiver equipped with the above, when the upper frequency setting key is pressed after the upper frequency setting key, the lower frequency setting key, and the specific frequency setting key are pressed, the reception frequency is set to the first frequency. a second setting means for setting a second frequency for distress communication, emergency communication or safety communication, which is a frequency near the first frequency and higher than the first frequency; and when the specific frequency setting key is pressed. Then, when the lower frequency setting key is pressed, the reception frequency is set to a frequency that is near the first frequency and lower than the first frequency. A radio receiver comprising: third setting means for setting a third frequency for distress communication, emergency communication, or safety communication.