JPH01144674A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the area of a memory cell, and to improve the degree of integration by connecting one end side of a conductive layer to one semiconductor region in a MISFET for transfer and connecting the other end side of the conductive layer onto the top face of a gate electrode for a MISFET for drive. CONSTITUTION:A memory cell M is constituted on the main surface of a p-type well region 4B. One semiconductor region 16 in a MISFETQt for transfer and a gate electrode 10A for a MISFETQd for drive are connected, and a high- resistance load element R connected to the connecting section, interposing a conductive layer 20A is composed of a memory cell M arranged to the upper section of the MISFETQd for drive. A connecting area is reduced only by a section corresponding to the quantity of displacement of mask alignment in manufacturing processes between both one semiconductor region 16 in the MISFETQt for transfer and the gate electrode 10A for the MISFETQd for drive at the time when both the semiconductor region 16 and the gate electrode 10A are connected directly, and the degree of integration can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to an SRAM.
(Tatic Random Access Mem
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having a semiconductor integrated circuit device.

[Conventional technology]

In SRAM, memory cells are arranged at the intersections of complementary data lines and word lines. The memory cell is composed of a flip-flop circuit and two transfer MISFETs each having one semiconductor region connected to a pair of input/output terminals of the flip-flop circuit.

The flip-flop circuit is used as an information storage section, and the input/output terminal section serves as an information storage node section. The flip-flop circuit is composed of two driving MISFETs and two high resistance load elements. High resistance load elements are
It is composed of a polycrystalline silicon film in which no or a small amount of inert substance that reduces the resistance value is introduced. The high resistance load element is arranged above the gate electrode of the driving MISFET. This high resistance load element is used for driving M
Since it is arranged above the ISFET, it has the feature that the memory cell area can be reduced and the SRAM can be highly integrated.

One semiconductor region of the transfer MISFET is connected to a drive MISFET in an output terminal portion of the flip-flop circuit.
Connected to the gate electrode of ET.

This connection is made by forming a connection hole in the insulating film on one semiconductor region of the transfer MISFET, and extending one end side of the gate electrode of the drive MISFET through the connection hole to directly connect the one semiconductor region of the transfer MISFET. This is done by connecting to.

That is, the connection is performed by a so-called direct contact method.

The gate electrode of the transfer MISFET of the memory cell is connected to a word line. The other semiconductor region of the transfer MISFET is connected to the complementary data line. A complementary data line is configured to extend over the high resistance load element.

The SRAM is described, for example, in Nikkei Microdevices, August 1987 issue, pages 71 to 87, published by Nikkei McGraw-Hill.

[Problem that the invention seeks to solve]

As a result of studying the above-mentioned SRAM, the inventor found that the following problems occur.

In the memory cell of the SRAM, the transfer MISFE
The area required for connection between one semiconductor region of T and the gate electrode of the driving MISFET is large.

The following area is added to this connection area. That is,
(1) Gate electrode of transfer MISFET and driving MIS
Area for separating the FET gate electrode. The separation dimension between the gate electrodes corresponds to the processing dimension during manufacturing. (
2) Area for connecting one semiconductor region of the transfer MI 5FET and the gate electrode of the drive MISFET. (
3) One semiconductor region of the transfer MISFET and the driving M
The mask alignment margin area in the manufacturing process between the ISFET gate electrode and the ISFET gate electrode. Therefore, the memory cell area increases, and the degree of integration of the SRAM decreases.

An object of the present invention is to provide a technique that can reduce the memory cell area and improve the degree of integration in a semiconductor integrated circuit device having an SRAM.

Another object of the present invention is to provide a technique that can achieve the above object without increasing the number of conductive layers in the memory cell.

Another object of the present invention is to provide a technique that can achieve the above object and improve the dielectric strength between the memory cells.

Another object of the present invention is to provide a technique that can reduce the number of manufacturing steps required to achieve each of the above objects in a semiconductor integrated circuit device having an SRAM and a bipolar transistor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

=7- A brief overview of typical inventions disclosed in this application is as follows.

In an SRAM memory cell, one end side of the electrically sensitive layer is connected to one semiconductor region of the transfer MISFET within a region defined by the gate electrode of the transfer MISFET and the gate electrode of the drive MISFET, and the other end of the electrically conductive layer is The end side is connected to the upper surface of the gate electrode of the driving MISFET.

Further, the conductive layer is configured integrally with a high resistance load element of the memory cell.

Further, in a semiconductor integrated circuit device having an SRAM and a bipolar transistor, a step of forming a first connection hole in a region defined by a gate electrode of a transfer MISFET and a gate electrode of a driving MISFET of a memory cell of the SRAM; , and the step of forming a second connection hole in the region defined by the base electrode of the bipolar transistor are performed in the same manufacturing process.

Further, the step of connecting a conductive layer to one semiconductor region of the transfer MISFET through the first connection hole and the step of connecting an emitter electrode to the emitter region through the second connection hole are performed in the same manufacturing process.

[For production]

According to the above-mentioned means, one semiconductor region of the transfer MISFET and the gate electrode of the drive MISFET are connected with a connection area corresponding to the processing dimension between the gate electrode of the transfer MISFET and the drive MISFET. Therefore, the connection area can be reduced by at least an amount equivalent to the amount of mask misalignment in the manufacturing process when the gate electrode of the driving MI 5FET is directly connected to one semiconductor region of the transfer MISFET. S, S
The degree of integration of RAM can be improved.

Furthermore, since the connection between one semiconductor region of the transfer MISFET and the gate electrode of the drive MISFET uses a conductive layer integrated with the high resistance load element, the number of conductive layers for the connection increases. do not.

Further, since the step of forming the first connection hole of the memory cell of the SRAM can also be used as the step of forming the second connection hole of the bipolar transistor, the step of forming the first connection hole is equivalent to the step of forming the first connection hole. The number of manufacturing steps for semiconductor integrated circuit devices can be reduced.

Furthermore, since the step of forming the conductive layer of the memory cell of the SRAM can also be used as the step of forming the emitter electrode of the bipolar transistor, the process of forming the conductive layer can be used to manufacture the semiconductor integrated circuit device. The number of steps can be reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a mixed type semiconductor integrated circuit device (so-called SRAM built-in Bi-CMO 8) having an SRAM and a bipolar transistor.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

A semiconductor integrated circuit device having an SRAM memory cell and a bipolar transistor, which is an embodiment of the present invention, is shown in FIG.
It is shown in the figure (cross-sectional view of main parts).

The right side of FIG. 1 shows an SRAM memory cell M, and the left side of FIG. 1 shows a bipolar transistor Tr.

The memory cell M of the SRAM is shown in FIG. 3 (equivalent circuit diagram).
As shown in FIG.
It is located at the intersection with L.

Complementary data lines DL extend in the row direction. The word line WL extends in the column direction.

The memory cell is composed of a flip-flop circuit and two transfer MISFETs Qt1 and Qt2, each of which has one semiconductor region connected to its pair of input/output terminals.

Said transfer MISFETQt4. Each of Qt2 is configured as an n-channel type. MISF for transfer
ETQt1. The other semiconductor region of each Qt2 is connected to complementary data line DL. Transfer MISFETQ
t1. l The electrode to each gate 1 of Qt2 is the word line WL
It is connected to the.

The flip-flop circuit is used as an information storage section,
The input/output terminal section is used as an information storage node section. The flip-flop circuit includes two driving MISFETs Qd1 and Qd2 and two high resistance load elements R1 and R2. Drive MISFET Qd1 and Qd
2 is constructed of an n-channel type.

The source regions of each of the drive MISFETs Qd□ and Qd2 are connected to a reference voltage Vss. Reference voltage V
g B is, for example, the ground potential of the circuit 0 [V]. The drain region of the drive M, 15FETQd□ is connected to one end of the high resistance load element R2, one semiconductor region of the transfer MISFETQt, and the gate electrode of the drive MISFETQd2. The drain region of the drive MISFET Qd2 is connected to one end side of the high resistance load element R□, the transfer MISFET Qd2,
15FETQt, one semiconductor region and driving MIS
Connected to the gate electrode of FETQd□. The other ends of each of the high resistance load elements R1 and R2 are at the power supply voltage ■. Connected to C. Power supply voltage ■. C is, for example, the operating voltage of the circuit, 5 [v].

Capacitive elements C1 and C2 are connected to each of the input/output terminals (information storage node section) of the flip-flop circuit. One electrode of capacitive element C□ is MISF for driving
Connected to the drain region of ETQd2. One electrode of the capacitive element C2 is connected to the drain region of the driving MISFET Qd. The other electrode of each of the capacitive elements C1 and C2 has a power supply voltage of 1/2Ve, although the voltage is not limited to this.
,,It is connected to the. Power supply voltage 1. /2Vc is the power supply voltage V. C and reference voltage V. Which intermediate potential (approximately 2.5
[V]).

Each of the capacitive elements C□ and C2 is configured to increase the amount of charge stored in the information storage node portion.

Next, the specific structure of the memory cell M of the SRAM configured as described above will be briefly explained using FIG. 1 and FIG. 2 (plan view of the memory cell).

Note that the memory cell M of SRA,M shown in FIG. 1 is a cross-sectional view taken along the line II in FIG. 2.

The memory cell M of the SRAM is formed on the main surface of a p-type well region 4B, as shown in FIGS. 1 and 2. The well region 4B is formed on the main surface of the n-type epitaxial layer 4 grown on the main surface of the p"-type semiconductor substrate 1 made of single crystal silicon. Between the semiconductor substrate 1 and the well region 4B, A p' type semiconductor region (so-called buried semiconductor region layer) 3 is formed.

A field insulating film 6 (
An element isolation insulating film) and a p-type channel stopper region (not shown) are provided. The field insulating film 6 and the channel stopper region are configured to electrically isolate between memory cell layers and between each element. Further, the memory cell M and other elements such as the bipolar transistor 1 to the transistor Tr are electrically isolated by a p1 type half region 5 provided in the field insulating film 6 and the epitaxial layer 4 below the field insulating film 6.

Each of the transfer MISFETs Qt□1Qt2 of the memory cell M is surrounded by a field insulating film 6 and a channel stopper region (not shown), as shown in FIGS. 1, 2, and 4 (plan views in predetermined manufacturing steps). It is formed on the main surface of the well region 4B in the area where the grooves are formed. In other words, each of the transfer MISFETs Qt□+Qt2 mainly
Well region 4B, gate insulating film 8, gate electrode 10A,
It is composed of a pair of n-type semiconductor regions 14 and a pair of n-type semiconductor regions 16, which are a source region and a drain region.

Well region 4B is used as a channel forming region.

Gate insulating film 8 is composed of a silicon oxide film formed by oxidizing the main surface of well region 4B.

The gate electrode 10A is formed on a predetermined upper part of the gate insulating film 8. The gate electrode 10A has an n
It is composed of a polycrystalline silicon film deposited by CVD into which a type impurity (P or As) is introduced.

Further, the gate electrode 10A is made of high melting point metal silicide (MoSi2.Ta5j2.TiSi) on the top of the polycrystalline silicon film.
2゜WSi2) film or high melting point metal (Mo, Ta, Tj,
W) It may be composed of a composite film made of laminated films.

Each gate electrode 10A of the transfer MISFET Qt is connected to a word line (W L ) 10 extending in the column direction.
It is integrated with A. The word line 10A is configured to extend over the field insulating film 6.

The low impurity concentration semiconductor region 14 is formed integrally with the high impurity concentration semiconductor region 16, and is provided on the channel formation region side in the main surface portion of the well region 4B. The semiconductor region 14 with a low impurity concentration is connected to the transfer MISFET Qt1.
Each of Qt2 is so-called LDD (5jghtiydanoped
It is designed to have a rain (rain) structure. The semiconductor region 14 with a low impurity concentration is self-aligned with the gate electrode 10A.

The semiconductor region 16 with high impurity concentration is self-aligned with the sidewall spacer 15 formed on the sidewall of the gate electrode 1°A.

MI S FET Qd1 for driving memory cell M. Qd
2 are the transfer MI 5FETs Qt1. Qt2
The structure is substantially similar to each of the above. In other words, each of the drive MISFETs Qd
4 and a pair of n' type semiconductor regions 16.

Drive MI 5FETQd1. , Qd2 are each L D
It is composed of D structure.

Particularly, as shown in FIGS. 1 and 5 (plan views in predetermined manufacturing steps), one end of the gate electrode 10A of the driving MISFET Qcl is connected to the transfer MISFET Qcl with an upper conductive layer 2OA interposed therebetween. - Connected to one semiconductor region 16 of ETQt1. Similarly, the drive MISFE
One extending end of the gate electrode 10A of TQd2 is connected to one semiconductor region 16 of the transfer MISFETQt2 with an upper conductive layer 2OA interposed therebetween. These connection portions correspond to the information storage node portion of the flip-flop circuit of the memory cell M.

One end side of the conductive layer 2OA is connected to the semiconductor region 16 through a connection hole 18A, and the other end side is connected through a connection hole 19 to the gate electrode 10A of the driving MISFET Qd. The connection hole 18A is connected to the gate electrode 10A of the transfer MISFETQt and the gate electrode 10A of the drive MISFETQd in the area opened in the interlayer insulating film 17.
It is configured within a region defined by a sidewall spacer 15 formed on each side wall of one end. Transfer M
The gate electrode 10A and the conductive layer 2OA of the ISFETQt are the interlayer insulating film 11 provided on the top of the gate electrode 10A.
electrically isolated. Since the side wall spacer 15 on the side wall of the gate electrode 10A can be formed with a thickness of about several thousand [people], one end side of the conductive layer 2OA is used as a transfer M.
ISFETQt gate electrode 10A and driving MISF
E T Qd can be connected to the semiconductor region 16 with a connection area within a region defined by the processing dimensions between the E T Qd and one end of the gate electrode 10A. Moreover, the connection portion between one end side of the conductive layer 2OA and the semiconductor region 16 is connected to a transfer MIsFETQ.
The gate electrode 10A of the drive MISFET Qd and one end of the gate electrode 10A of the driving MISFET Qd can be self-aligned.

The connection hole 19 is formed in a region opened in the interlayer insulating film 17 to form the connection hole 18A.
It is formed in the interlayer insulating film 11 at one end of the gate electrode 10A of the FETQd. That is, the connection hole 19 is provided above the gate electrode 10A of the driving MISFETQd. Further, the connection hole 19 is in a region different from one end side of the conductive layer 2OA, and is connected to the transfer MISFET Qt.
It is provided on a field insulating film 6 that separates the drive MISFET Qd from the drive MISFET Qd. In other words, the area for forming the connection hole 19 can also be used as the area for forming the gate electrode 10A or the field insulating film 6, so the connection hole 19 does not contribute to an increase in the area of the memory cell M.

The conductive layer 2OA is doped with an n-type impurity (P) that reduces the resistance value.
or A s ) is formed by a polycrystalline silicon film deposited by CVD.

The other end side of the gate electrode 10A of the drive MISFET Qd1 passes through the connection hole 9 formed in the gate insulating film 8 and is connected to n4.
MISFETQd for driving with the type semiconductor region 13 interposed
1 of 2 is connected to the semiconductor region 16 which is a rain region. The semiconductor region 13 is a gate electrode (polycrystalline silicon film)
It is formed by diffusing the n-type impurity introduced into the well region 10A into the main surface of the well region 4B. This connection cannot be made using the same conductive layer as the conductive layer 2OA because it contacts the power supply voltage wiring (VCC) 20C, which will be described later.
This is done by directly connecting the other end of 0A to the semiconductor region 16. As a result, the drive MISFETQ
The gate electrode 10A of d1 is the transfer MISFET Qt1.
This constitutes one of the cross wirings of the flip-flop circuit that connects one semiconductor region 1 and the semiconductor region 16 which is the drain region of the driving MISFET Qd2.

One semiconductor region 16 of the transfer MISFET Qt2 is configured integrally with the semiconductor region 16 which is the drain region of the drive MISFET Qd1. This integration constitutes the other side of the cross wiring of the flip-flop circuit.

A complementary data line (DL) 27 is connected to the other semiconductor region 16 of each of the transfer MISFETs Qt, . . . , Qt2 through a connection hole 2G formed in an interlayer insulating film 25. Complementary data line 27 is configured to extend above interlayer insulating film 25 in the row direction. The complementary data line 27 is made of, for example, an aluminum film or an aluminum alloy film doped with Cu or S to prevent migration.

A reference voltage 58 is applied to the semiconductor region 16 which is the source region of each of the driving MISFETs Qd□ and Qdz. Although the supply of this reference voltage Vss is not shown,
This is performed by a reference voltage wiring formed of the same conductive layer as the gate electrode 10A and the word line 10A and extending in the same column direction. This reference voltage wiring is connected to the driving MISFET Qd through the connection hole 9 formed in the gate insulating film 8.
, , Qd2 are connected to the semiconductor region 16 which is the source region of each of them.

The high resistance load element (R1) 20B of the memory cell M is the first
As shown in Fig. 2 and Fig. 5, the drive MISFE
An interlayer insulating film 17 is provided above the TQd□. High resistance load element (R2) 20B is MIS for driving
It is configured above FETQd2. Specifically, the high resistance load elements (R□ and R2, respectively) 20B are arranged above the gate electrode 10A.

The high-resistance load element 20B is composed of a polycrystalline silicon film deposited by CVD, with no impurity introduced to reduce the resistance value, or with n-type or a small amount of n-type impurity introduced. . The high resistance load element 20B is a driving MISF
Since the regions of ETQd1 and Qd2 are shared, the area of the memory cell M can be reduced.

One end of the high resistance load element (R□) 20B is connected to the MIS for transfer.
One semiconductor region 16 of FETQt1 and driving MISF
A conductive layer 2O is connected to the gate electrode 10A of ETQd.
They are connected through A. Similarly, one end of the high resistance load element (R2) 20B is connected to the transfer MISFET Qt2.
One semiconductor region 16 and the driving MISFET
It is connected to the connection portion of Qd2 with the gate electrode 10A with an electrically sensitive layer 20A interposed therebetween. One end of the high resistance load element 20B is configured integrally with the conductive layer 2OA. The other end of the high resistance load element 20B is configured integrally with the power supply voltage wiring (V, c) 20G. The power supply voltage line 20C is configured to extend in the same column direction as the word line 10A. Power supply voltage wiring 2DC is n type (or P
type) is composed of a polycrystalline silicon film into which impurities are introduced.

In this way, one semiconductor region 16 of the transfer MISFET Qt and the gate electrode 10A of the drive MISFET Qd are connected, and the connected high-resistance load element R is connected to the top of the drive MISFET Qd with the conductive layer 20A interposed in this connection. A semiconductor integrated circuit device having an SRAM configured with memory cells M arranged in the transfer MISF.
ETQt gate electrode 10A and driving MISFETQd
A MISF for transfer that is self-aligned with respect to each gate electrode 10A is placed in a region defined by the gate electrode 10A.
Electrically isolated from the gate electrode 10A of the ETQt, one end side of the conductive layer 2OA is connected to one semiconductor region 16 of the transfer MISFET Qt, and the other end side of the conductive layer 20A is connected to the gate electrode of the drive MISFET Qd. By connecting to the top surface of the 10A transfer MIsFETQ
One semiconductor region 16 of the transfer MISFETQt and the gate electrode 10A of the drive MISFETQd can be connected with a connection area corresponding to the processing dimension between the gate electrode 10A of the drive MISFETQd and the gate electrode 10A of the drive MISFETQd. Therefore, the gate electrode 10 of the drive MISFETQd is placed in one semiconductor region 16 of the transfer MISFETQt.
In the case where A is directly connected, the connection area is reduced by an amount equivalent to the amount of mask misalignment in the manufacturing process between the two,
The degree of integration can be improved.

Also, one semiconductor region 16 of the transfer MISFETQt
Since the conductive layer 2OA connecting the high-resistance load element R is also used for connection with the gate electrode 10A of the drive MISFET Qd, the number of conductive layers for the connection does not increase.

On the upper part of the conductive layer 2OA, which becomes the information storage node part of the flip-flop circuit of the memory cell M,
As shown in the figure, a plate electrode layer 24 is provided with a dielectric film 23 interposed therebetween. That is, the transfer MISF
One semiconductor region 16 of ETQt□ and driving MISFE
The conductive layer 2OA, dielectric film 23, and plate electrode layer 24, one end of which is connected to the connection portion of TQd□ with the gate electrode 10A, constitute a capacitive element C□. Transfer MISFETQ
One semiconductor region 16 of t2 and driving MISFET Qd
The conductive layer 2OA, one end of which is connected to the connection portion with the second gate electrode 10A, the dielectric film 23, and the plate electrode layer 24 constitute a capacitive element C2.

The dielectric film 23 is provided above the conductive layer 2OA and the high resistance load element 20B, and is formed below the plate electrode layer 24 in the same shape. The dielectric film 23 is composed of a single layer of a silicon nitride film having a thickness of about 1.00 to 200 mm in order to increase the amount of charge stored in each of the capacitive elements C□ and C2. Further, the dielectric film 23 may be composed of a composite film in which a silicon nitride film and a silicon oxide film are stacked.

That is, the dielectric film 23 is composed of an insulating film mainly composed of a silicon nitride film.

The plate electrode layer 24 is provided on top of the dielectric film 23. The plate electrode layer 24 is configured integrally with the plates 1 to 24 of the other memory cells M, which are arranged in the same column direction as the direction in which the word line 10A extends.

The plate electrode layer 24 has a power supply voltage of 1/2 as described above.

. is applied. The plate electrode layer 24 is, for example, a CV
It is composed of a polycrystalline silicon film deposited by D.

A dielectric film 23 is interposed as an interlayer insulating film 23, and an electric field shielding layer 24 is provided above the high resistance load elements (R1 and R2, respectively) 20B. This electric field shielding layer 24 is provided between the high resistance load element 20B and the complementary data line 27. This electric field shielding layer 24 is configured to prevent the formation of a parasitic channel in the high resistance load element 20B due to the electric field effect from the complementary data line 27. That is, the electric field shielding layer 24 is configured to prevent the parasitic MO8 effect. The parasitic MO 8 is configured using the complementary data line 27 as a gate electrode, the interlayer insulating film 25 as a gate insulating film, and the high resistance load element 20B as a channel forming region.

This electric field shielding layer 24 is made of the same conductive layer as the plate electrode layer 24, and is formed integrally with the plate electrode layer 24. That is, the electric field shielding layer 24 is configured by extending the plate electrode layer 24 provided on the top of the conductive layer 2OA to the top of the high resistance load element 20B. As a result, the electric field shielding layer 24 is made of a polycrystalline silicon film and has a power supply voltage of 1/2. . is applied.

In this way, high resistance load elements (R, , . . .
Configure a memory cell M connecting each of R2) 20B,
This semiconductor integrated circuit device has an SRAM in which a complementary data line 27 extends above the high resistance load element 20B of the memory cell M, and above the conductive layer 2OA connected to the information storage node section. A capacitive element C is configured by providing a plate electrode layer 24 to which a predetermined potential is applied with a dielectric film 23 interposed therebetween, and between the high resistance load element 20B and the complementary data line 27, the complementary data By providing the electric field shielding layer 24 that shields the electric field effect from the wire 27,
Since the amount of charge stored in the information storage node section can be increased, soft errors can be prevented, and the electric field effect from the complementary data line 27 can be shielded, so that a parasitic channel is not formed in the high resistance load element 20B. The standby current amount (standby current amount)
can be reduced and power consumption can be reduced.

Further, the high resistance load element 20B and the electric field shielding layer 24=2
7- By providing the interlayer insulating film 23 mainly composed of a silicon nitride film, in addition to the above effects, the interlayer insulating film 23
This prevents hydrogen from entering the high resistance load element 20B from entering the high resistance load element 20B, prevents the crystallinity of the high resistance load element (polycrystalline silicon film) 20B from improving, and
Since it is possible to prevent the threshold voltage of the parasitic MO8 having a channel formation region from decreasing, the amount of current during standby can be reduced, and power consumption can be reduced.

Although not shown in FIG. 1, a passivation film is provided over the entire surface of the substrate including the top of the complementary data line 27. For example, the passivation film can be formed by plasma CV
It is formed from the silicon nitride film deposited in step D. This passivation film becomes a source of hydrogen generation.

The bipolar transistor Tr is formed on the main surface of the n-type well region 4A, as shown on the left side of FIG. The well region 4A is formed on the main surface of the epitaxial layer 4 (or in the epitaxial layer 4 itself). Between the semiconductor substrate 1 and the well region 4A is an n-type semiconductor region (
A buried semi-floating body region layer) 2 is provided. The semiconductor region 2 is configured to reduce the collector resistance of the bipolar transistor Tr.

A field insulating film 6 is provided between the bipolar transistors Tr.
and a semiconductor region 5 are provided, and are configured to electrically isolate the bipolar transistors Tr. The bipolar transistor Tr is of an npn type and includes a collector region, a base region, and an emitter region.

The collector region includes a well region 4A, an n+ type semiconductor region 7 for raising the potential, and a buried semiconductor region 2. The semiconductor region 7 for raising the potential is formed on the main surface of the well region 4A, and is configured to reach the buried semiconductor region 2 from the main surface of the well region 4A. Semiconductor area 7
A collector wiring 27 is connected to the collector wiring 27 through a connection hole 26 formed in the interlayer insulating film 25.

The base region is composed of a p'' semiconductor region 12 as an extrinsic base region and a P type semiconductor region 21 as an active base region.Semiconductor region 1 as an extrinsic base region
2 has a rectangular ring shape defined by the field insulating film 6. The semiconductor region 21 serving as an active base region is provided in the central portion of the semiconductor region 12 serving as an external base region.

A base electrode 10B is connected to the base region through a connection hole 9. The base electrode 10B is formed by introducing an n-type impurity (B or BF2) into a polycrystalline silicon film formed of the same conductive layer as the gate electrode 10A. The semiconductor region 12 as an external base region is formed by diffusing n-type impurities introduced into the base electrode 10B into the main surface of the well region 4A. In other words,
The semiconductor region 12 as an external base region is self-aligned with the base electrode 10B. Although not shown, a base wiring formed of the same conductive layer as the collector wiring 27 is connected to the base electrode 10B.

The emitter region is composed of an n-type semiconductor region 22. This semiconductor region 22 is provided on the main surface of the semiconductor region 21 serving as the active base region.

An emitter electrode 20D is connected to the emitter region through a connection hole 18B. The connection hole 18B is formed within the opening formed in the interlayer insulating film 17 in a region defined by the sidewall spacer 15 formed on the side wall of the base electrode 10B. That is, the SRA, M
The connection hole 18A has substantially the same structure as the connection hole 18A formed in the memory cell M.

The emitter electrode 20D includes the conductive layer 2OA of the memory cell M of the SRAM, the high resistance load element 20B, and the power supply voltage line 2.
n-type and said n-type formed of the same conductive layer as each of 0C
It is composed of a polycrystalline silicon film into which an n-type impurity having a lower concentration than the type is introduced. The emitter region (semiconductor region 22) is formed on the main surface of the semiconductor region 21 by heat-treating the n-type impurity (As or P) introduced into the polycrystalline silicon film of the emitter electrode 20D. Furthermore, the semiconductor region 21 as the active base region can be formed by a similar method. The emitter electrode 20D has an interlayer insulating film 2
5 through the connection hole 26 formed in the emitter wiring 2.
7 is connected.

Next, a specific method of manufacturing the above-described semiconductor integrated circuit device will be briefly explained using FIGS. 6 to 14 (cross-sectional views of main parts shown for each manufacturing process).

First, a P-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, n-type impurities are introduced into the main surface of the semiconductor substrate 1 in the bipolar 1-transistor Tr formation region. Further, n-type impurities are introduced into the main surface of the semiconductor substrate 1 in the memory cell M formation region and the element isolation region of the SRAM. These impurities are adapted to form a buried semiconductor region layer.

Next, a square-shaped epitaxial layer 4 is grown on the main surface of the semiconductor substrate 1. Through the same manufacturing process as the process of forming the epitaxial layer 4, each of the introduced n-type impurities and n-type impurities is stretched and diffused, and the n" type semiconductor is formed at the interface between the semiconductor substrate 1 and the epitaxial layer 4. Region 2 and p' type semiconductor region 3 are each formed.

Next, as shown in FIG. 6, an n-type well region 4A, a p-type well region 4B, a p'-type semiconductor region 5, and a field insulating film 6 are formed on the main surface of the epitaxial layer 4. The well region 4A is formed in a region where a bipolar transistor Tr and an n-channel MISFET (not shown) are formed. Well region 4B is formed in the formation region of memory cell M and n-channel MISFET (not shown). The semiconductor region 5 is mainly formed between the formation regions of the bipolar transistors Tr. A field insulating film 6 is formed between each element.

Furthermore, in the main surface of the well region 4B, p-type channels 1 to brim regions are formed under the field insulating film 6. Note that the element isolation region includes a p-type well region 4B and a p-type channel layer 1-instead of the p-type semiconductor region 5.
It may also be configured with a brim area.

Next, in the bipolar transistor Tr formation region,
An n-type semiconductor region 7 for raising the potential is formed.

Next, as shown in FIG. 7, a gate insulating film 8 is formed on the main surface of the well region 4B. This gate insulating film 8 is similarly formed on the main surface of the well region 4A. The gate insulating film 8 is formed of a silicon oxide film obtained by oxidizing the main surface of the well region 4B (4A), for example, and is formed to have a thickness of about 100 to 300 [layers].

Next, as shown in FIG. 8, a gate electrode 10A and an interlayer insulating film 11 are formed in the memory cell M forming region, and a base electrode 10B and an interlayer insulating film 11 are formed in the bipolar transistor Tr forming region.

The gate electrode 10A is provided with C on a predetermined upper part of the gate insulating film 8.
It is formed of a polycrystalline silicon film deposited by VD. An n-type impurity such as P is introduced into the polycrystalline silicon film. The gate electrode 10A is formed to have a thickness of about 3000 to 4000 [in], for example.

The other end side of the gate electrode 10A of the driving MISFET Qd1 is directly connected to the main surface of the well region 4B through a connection hole 9 formed in the gate insulating film 8.

The interlayer insulating film 11 is formed of, for example, a silicon oxide film deposited by CVD in order to electrically isolate the gate electrode 10A and the conductive layer above it, and is formed to have a thickness of about 3000 to 4000 [layers]. The interlayer insulating film 11 is connected to the gate electrode 10A.
At the same time, patterning is performed by anisotropic etching such as RIE.

The base electrode 10B is formed by introducing a p-type impurity, such as BF, into a polycrystalline silicon film deposited in the same manufacturing process as the gate electrode 10A. The base electrode 10B is directly connected to the main surface of the well region 4A through a connection hole 9 formed by removing the gate insulating film 8. Interlayer insulation II above the base electrode 10B! All is formed in the same manufacturing process as the interlayer insulating film 11 above the gate electrode 10A.

Next, as shown in FIG. 9, in the memory cell M formation region, an n-type semiconductor region 14 is formed on the main surface of the well region 4B. The n-type semiconductor region 14 contains an n-type impurity such as P.
is formed by introducing into the main surface portion of the well region 4B by ion implantation. When introducing the n-type impurity, the gate electrode 10A and the interlayer insulating film 11 are mainly used as a mask for impurity introduction. Therefore, the semiconductor region 14 is formed in self-alignment with the gate electrode 10A.

By the same manufacturing process as a part of the heat treatment process in the process of forming this semiconductor region 14, an n-type semiconductor region 13 is formed on the main surface of the well region 4B in the memory cell M formation region, and an external A p-type semiconductor region 12 is formed to serve as a base region. The semiconductor region 13 has n introduced into the gate electrode 10A.
It is formed by diffusion of type impurities. Semiconductor region 12 is formed by diffusing p-type impurities introduced into base electrode 10B.

Next, sidewall spacers 15 are formed on the sidewalls of the gate electrode 10A and the base electrode 10B, respectively. The sidewall spacer 15 is formed by forming a silicon oxide film deposited by CVD on the entire surface of the substrate including the upper part of the interlayer insulating film 11.
It can be formed by subjecting this silicon oxide film to anisotropic etching such as RIE. This sidewall spacer 15 can be formed with a thin film thickness of about several thousand [people] from the sidewall of the gate electrode 10A and the sidewall of the base electrode 10B, respectively. The sidewall spacer 15 is formed in self-alignment with the gate electrode 10A or the base electrode 10B.

Next, as shown in FIG. 10, in the memory cell M formation region, an n+ type semiconductor region 1 is formed on the main surface of the well region 4B.
form 6. The semiconductor region 16 is filled with an n-type impurity such as A
It is formed by introducing s into the main surface of the well region 4B by ion implantation. When introducing n-type impurities, the gate electrode 10A, interlayer insulating film 11, and sidewall spacer 15 are mainly used as impurity introduction masks. Therefore, the semiconductor region 16 is connected to the gate electrode 1
It is formed in self-alignment with respect to 0A.

By the process of forming the semiconductor region 16, the transfer M I S F E T Qtl, Qt2 of the memory cell M is
and drive MI 5FETQd1. Each of Qd, , is completed.

Next, an interlayer insulating film 17 is formed over the entire surface of the substrate including the upper part of the interlayer insulating film 11. The interlayer insulating film 17 is made of, for example, C.
Formed with a silicon oxide film deposited by VD,
00 [Form to have a film thickness comparable to that of a human.

Next, as shown in FIG. 11, connection holes 18A and 18B
form. The connection hole 18A is for transfer MISFETQt.
within the area defined by the gate electrode 10A of the drive MISFET Qd and the drive MISFET Qd.
Interlayer insulating film 1 on a predetermined upper part of gate electrode 10A of TQd
It is formed by removing 7. The connection hole 18A is an opening formed in the interlayer insulating film 17 and the sidewall spacer 15.
Within the area defined by the transfer MIsFETQ
It is formed so as to expose the main surface of the semiconductor region 16, which is one of the semiconductor regions of each of t□ and Qtz. Connection hole 18
A is formed using an etching mask shown by dotted lines in FIG. The dimensions of the opening formed in the interlayer insulating film 17 to form the connection hole 18A are the dimensions within the area defined by the gate electrode 10A (actually, the sidewall spacer 15) and the predetermined distance of the electrode 10A to the gate 1. (the dimension of the connection hole 19) by at least an amount corresponding to the amount of mask misalignment in the manufacturing process. Furthermore, when forming the connection hole 18A, the interlayer insulating film 11 above the gate electrode 10A is not substantially removed.

The connection hole 18B is formed by removing the interlayer insulating film 17 within the region defined by the base electrode 10B. The connection hole 18B is formed within a region defined by the opening formed in the interlayer insulating film 17 and the sidewall spacer 15.
The main surface of the well region 4A is exposed. The dimensions of the connection hole 18B are larger than the dimensions of the area defined by the sidewall spacer 15 by at least an amount corresponding to the amount of mask misalignment in the manufacturing process. This connection hole 18B is formed in the same manufacturing process as the connection hole 18A.

Next, as shown in FIG. 12, in the area opened in the interlayer insulating film 17 to form the connection hole 18A,
Drive MISFETQd1. Two parts of the interlayer insulating film 11 of each gate electrode 10A of Qd2 are removed, and a connection hole 19 is formed.
form. This connection hole 19 is formed using an etching mask shown by dotted lines in FIG.

Next, as shown in FIG. 13, in the memory cell M formation region, a conductive layer 2OA and a high resistance load element (R□) are formed.

R2) 20B and power supply voltage wiring 20C are formed, and an emitter electrode 20D is formed in the bipolar transistor Tr formation region.

The conductive layer 2OA has one end connected to one semiconductor region 16 of each of the transfer MI 5FETQt, Qt2 through the connection hole 18A, and the other end connected to the drive MIS FETQd1. It is formed on the upper part of the interlayer insulating film 17 so as to be connected to the surface of each gate electrode 10A of Qd2. The conductive layer 2OA is made of, for example, an n-type impurity (
P) is formed of a polycrystalline silicon film introduced with 2000 ~
It is formed with a film thickness of about 3000 [people].

The high resistance load element 20B has one end formed integrally with the other end of the conductive layer 20A, and the other end connected to the power supply voltage wiring 20C.
It is constructed integrally with. In other words, the high resistance load element 20
B is formed in the same manufacturing process as the conductive layer 2OA. Is there any impurity introduced into the high resistance load element 20B?
Alternatively, it is formed of an n-type or an i-type polycrystalline silicon film into which some n-type impurities are introduced.

The power supply voltage wiring 20G is formed of a polycrystalline silicon film into which n-type impurities are introduced in the same manufacturing process as the conductive layer 2OA.

The emitter electrode 20D is formed in the interlayer insulating film 17 so as to be directly connected to the main surface of the well region 4A through the connection hole 18B.
is located at the top of the. The emitter electrode 20D is formed of an n-type polycrystalline silicon film formed in the same manufacturing process as the conductive layer 2OA and the power supply voltage wiring 20C. On the main surface of the well region 4A below the emitter electrode 20D,
As shown in FIG. 13, after a polycrystalline silicon film is deposited by CVD, n-type impurities and n-type impurities are introduced into the polycrystalline silicon film, and heat treatment is performed to form a p-type active base region. A type semiconductor region 21 and an n''' type semiconductor region 22 serving as an emitter region are formed.

That is, the semiconductor region 21 is formed by diffusing an n-type impurity such as boron (B) introduced into the polycrystalline silicon film of the emitter electrode 20D. In addition, semiconductor region 2
2 is n introduced into the polycrystalline silicon film of the emitter electrode 20D.
It is formed by diffusing a type impurity such as arsenic (As). Since the diffusion coefficient of boron (B) in the substrate is larger than that of arsenic (As), the semiconductor region 21
is formed deeper in the substrate than the semiconductor region 22. Since the concentration of arsenic (As) is sufficiently higher than the concentration of boron (B), the semiconductor region 22 and the emitter electrode 2
The 0D polycrystalline silicon film exhibits n-type. The emitter electrode 20
D. By forming semiconductor regions 21 and 22,
Bipolar transistor Tr is completed.

In this way, one semiconductor region 16 of the transfer MIsFETQt and the gate electrode 10A of the drive MISFETQd are connected, and the high resistance load elements (R□, R2) are connected to each other with the conductive layer 20A interposed in this connection part. A semiconductor integrated circuit device comprising an SRAM composed of a memory cell M in which 20B is placed above a driving MISFET Qd, and a bipolar transistor Tr connecting an emitter electrode 20D within a region defined by a base electrode 10B, The gate electrode 10A of the transfer MISFETQt, the gate electrode 10A of the drive MISFETQd, and the base electrode 10 of the bipolar transistor Tr of the memory cell M of the SRAM.
A step of forming an interlayer insulating film 11 (first insulating film) on top of each of the gate electrode 10A and base electrode 10B, and forming a sidewall of each of the gate electrode 10A and base electrode 10B. side wall spacer 1
5, forming an interlayer insulating film 17 (second insulating film) on the entire surface of the substrate including the upper part of the interlayer insulating film 11, and forming the gate electrode 10A of the transfer MISFET Qt.
The interlayer insulating film 17 in a region defined by the gate electrode 10A of the driving MISFET Qd and a predetermined upper part of the gate electrode 10A of the driving MISFET Qd is removed to form a connection hole defined by the interlayer insulating film 17 and the sidewall spacer 15. 18A (first connection hole) is formed, and the interlayer insulating film 17 in the area defined by the base electrode 10B is removed, and the interlayer insulating film 17 and side wall spacer 15 are removed.
The step of forming the connection hole 18B (second connection hole) defined by One end side is connected to one semiconductor region of the transfer MISFET Qt through the connection hole 18A, and the other end side is connected to the gate electrode 10A of the drive MISFET Qd through the connection hole 19.
The conductive layer 2OA connected to the conductive layer 2OA and the high resistance load element 20B integrally formed therewith are formed on the interlayer insulating film 17, and the well region 4 is connected to the conductive layer 2OA through the connection hole 18B.
A (emitter region) of the bipolar transistor Tr. Since it can be used also in the process of forming the connection hole 18B, it is possible to reduce the manufacturing process of the semiconductor integrated circuit device by the amount corresponding to the process of forming the connection hole 18A.

Furthermore, the process of forming the conductive layer 20A and the high resistance load element 20B of the memory cell M of the SRAM can also be used as the process of forming the emitter electrode 20D of the bipolar transistor Tr. The manufacturing process of the semiconductor integrated circuit device can be reduced by an amount corresponding to the process of forming the element 20B.

Next, as shown in FIG. 14, in the memory cell M formation region, a plate electrode layer 24 is formed on top of the conductive layer 2OA with a dielectric film 23 interposed therebetween, and capacitive elements C□ and C2 are formed. The high resistance load elements (R□, R2 each) 20
An electric field shielding layer 24 is formed on top of B with a dielectric film 23 interposed as an interlayer insulating film 23.

The dielectric film 23 and the interlayer insulating film 23 are each formed by the same manufacturing process. The dielectric film 23 is formed of a single layer silicon nitride film deposited by CVD, for example, in order to improve the dielectric constant, and is formed to have a film thickness of about 100 to 200 cm. The dielectric film 23 and the interlayer insulating film 23 are patterned using the plate electrode layer 24 and the electric field shielding layer 24 as etching masks.

The plate electrode layer 24 and the electric field shielding layer 24 are each formed by the same manufacturing process. The plate electrode layer 24 and the electric field shielding layer 24 are formed of, for example, a polycrystalline silicon film deposited by CVD, and are formed to have a thickness of about 1,500 to 3,000 mm. An n-type impurity is introduced into this polycrystalline silicon film.

Next, an interlayer insulating film 25 is formed over the entire surface of the substrate including the upper part of the plate electrode layer 24 and the upper part of the electric field shielding layer 24. The interlayer insulating film 25 is, for example, a 100-50% film deposited by CVD.
On top of a silicon oxide film with a thickness of about 0 [person], a BP with a thickness of about 4,000 to 6,000 [:person] was deposited by CVD.
It is formed from a composite film made by stacking SG films. The BPSG film is configured to alleviate the step shape caused by the multilayer wiring structure and improve the step coverage of the upper layer wiring. The silicon oxide film is formed to prevent B or P from leaking from the BPSG film.

Next, the transfer MISFETQt of the memory cell M.

The upper part of the other semiconductor region 16 of Qt2, the upper part of the semiconductor region 7 for raising the potential of the bipolar transistor Tr, the interlayer insulating film 25 and the like on the upper part of the emitter electrode 20D are removed, and a connection hole 26 is formed.

Next, as shown in FIGS. 1 and 2, a complementary data line (DL) 27, a collector wiring 27, an emitter wiring 27, and a base wiring are formed on the interlayer insulating film 25. . These wirings 27 are connected to each region through the connection holes 26.

Next, although not shown, a passivation film is formed over the entire surface of the substrate including the upper part of the wiring 27. The passivation film is formed of a silicon nitride film deposited by plasma CVD.

By performing these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed.

In this way, high resistance load elements (R, , R
2) A semiconductor integrated circuit device having an SRAM in which a complementary data line 27 extends above a high-resistance load element 20B of the memory cell M, and a complementary data line 27 extends above a high-resistance load element 20B of the memory cell M. A plate electrode layer 24 to which a predetermined potential is applied is formed on the conductive layer 2OA connected to the node portion with a dielectric film 23 interposed therebetween, and the capacitive element C
An electric field shielding layer 24 is formed between the high resistance load element 20B and the complementary data line 27 by the same manufacturing process as that for forming the complementary data line 27. Accordingly, the step of forming the electric field shielding layer 24 can also be used as the step of forming the plate electrode layer 24, so that the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the electric field shielding layer 24. can be reduced.

Furthermore, a high resistance load element (R□
, R2) 20B, the step of forming the interlayer insulating film 23 can also be used as the step of forming the dielectric film 23. The number of manufacturing steps for the semiconductor integrated circuit device can be reduced by an amount equivalent to the number of steps.

Further, as shown in FIG. 15 (a cross-sectional view of the main part taken along the xv-xv section line in FIG. 2), the transfer MISFETs of the two memory cells M adjacent in the column direction of the S RAM are
The dielectric breakdown voltage between Qt□ and Qtl and between Qt2 and Qt2 is high.

In other words, the transfer M I S F E T Qtl, Qt
One of the semiconductor regions 16 of each of the semiconductor regions 16 is made of n-type impurities introduced by ion implantation, and the driving MISFE
Semiconductor region 1 forming part of the train region of TQd2
This is because the semiconductor region 16 is not formed by thermal diffusion as in No. 3, so the pn junction depth of the semiconductor region 16 can be formed shallow, and it is possible to prevent the semiconductor region 16 from going around to the lower part of the field insulating film 6. Therefore, the dimensions between adjacent memory cell layers in the column direction can be reduced, so that the degree of integration of the SRAM can be further improved.

Furthermore, as shown in FIGS. 16 and 17 (reproduction cross-sectional views showing the high resistance load element and capacitive element portions of the memory cell), the high resistance load elements (R1, R
An interlayer insulating film 23 having a thickness thicker than the dielectric film 23 may be formed between each of 2) 20B and the electric field shielding layer 24. The interlayer insulating film 23 is formed of a composite film in which a silicon nitride film 23A and a silicon oxide film 23B, which are formed in the same manufacturing process as the dielectric film 23, are laminated. This interlayer insulating film 23 reduces the parasitic capacitance added to the high resistance load element 20B and the power supply voltage wiring 20C, and also reduces the parasitic capacitance added to the high resistance load element 20B and the power supply voltage wiring 20C.
The electric field shielding layer 24 is configured to improve the dielectric strength between the electric field shielding layer 24 and the power supply voltage wiring 20C.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects that can be obtained by typical ones are as follows.

In a semiconductor integrated circuit device having SRAM, SRA
Since the memory cell area of M can be reduced, the degree of integration can be improved.

In addition to the above effects, the number of conductive layers on the memory cell can be reduced.

Further, in a semiconductor integrated circuit device having an SRAM and a bipolar transistor, the number of manufacturing steps for obtaining the above effects can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device having an SRAM memory cell and a bipolar transistor, which is an embodiment of the present invention. FIG. 2 is a plan view of the SRAM memory cell. , an equivalent circuit diagram of the memory cell of the SRAM, FIGS. 4 and 5 are plan views of the memory cell of the SRAM in a predetermined manufacturing process, and FIGS. 6 to 14 show the memory cells of the SRAM, respectively. FIG. 15 is a sectional view of the main part shown for each manufacturing process, and FIG. 15 is a sectional view of the main part taken along the line xv-xv in FIG. Some S
FIG. 2 is a schematic cross-sectional view showing the structure of a memory cell of a RAM. In the figure, M...memory cell, Tr...bipolar transistor, Qt□+Qjz...transfer MISFET, Q
d□, Qd2...Drive MISFET, C1, C2...
Capacitive element, 7.12, 13, 14, 16, 21.22・
... Semiconductor region, 8... Gate insulating film, 9, 18A,
18B, 19... Connection hole, IOA... Gate electrode,
IOB...Base electrode, 15...Side wall spacer, 11.1? , 23.25... interlayer insulating film, 2
OA... Conductive layer, 20B, R□, R2... High resistance load element, 20G... Power supply voltage wiring, 20D... Emitter electrode, 23... Dielectric film, 24... Plate electrode layer or electric field shielding layer, 27°DL...complementary data line.

Claims (1)

[Claims] 1. One semiconductor region of the transfer MISFET and the driving M
The memory cell is connected to the gate electrode of the ISFET, and a high-resistance load element integrated with the conductive layer is connected to the connection portion with a conductive layer interposed therebetween, and is disposed above the driving MISFET. A semiconductor integrated circuit device having an SRAM, wherein the gate of the transfer MISFET is self-aligned with respect to the respective gate electrodes in a region defined by the gate electrode of the transfer MISFET and the drive MISFET. One end of the conductive layer is connected to one semiconductor region of the transfer MISFET, electrically separated from the electrode, and the other end of the conductive layer is connected to the drive MISFET.
A semiconductor integrated circuit device, characterized in that it is connected to the upper surface of a gate electrode of an SFET. 2. One end side of the conductive layer is defined by a sidewall spacer formed on each sidewall of the gate electrode of the transfer MISFET and the gate electrode of the drive MISFET, and is connected to one semiconductor region of the transfer MISFET. A semiconductor integrated circuit device according to claim 1, characterized in that: 3. The other end side of the conductive layer is characterized in that the gate electrode of the driving MISFET is extended to the top of the field insulating film, and is connected to the gate electrode of the driving MISFET within this extended region. A semiconductor integrated circuit device according to claim 1 or 2. 4. Claim 1, wherein the conductive layer and the high resistance load element are made of a polycrystalline silicon film.
Each of the semiconductor integrated circuit devices described in Items 1 to 3. 5. One semiconductor region of the transfer MISFET contains impurities introduced by ion implantation into a region defined by the gate electrode of the transfer MISFET and the gate electrode of the drive MISFET, and the sidewalls of each of the gate electrodes. Claims 2 to 4 are characterized in that the impurity is formed by stretching and diffusing impurities introduced by ion implantation into a region defined by a sidewall spacer formed in Each semiconductor integrated circuit device described in . 6. One semiconductor region of transfer MISFET and drive M
The gate electrode of the ISFET is connected to the M for driving a high resistance load element connected with a conductive layer interposed in this connection part.
S consisting of memory cells placed above the ISFET
A method for manufacturing a semiconductor integrated circuit device having a RAM and a bipolar transistor having an emitter electrode connected within a region defined by a base electrode, the gate electrode of a transfer MISFET of a memory cell of the SRAM and a driving MISFET.
forming a gate electrode of an SFET and a base electrode of a bipolar transistor, and forming a first insulating film on top of each of the gate electrode and base electrode; a step of forming a wall spacer, a step of forming a second insulating film over the entire surface of the substrate including the upper layer of the first insulating film, and a region defined by the gate electrode of the transfer MISFET and the gate electrode of the drive MISFET. The second insulating film at a predetermined upper part of the gate electrode of the internal and driving MISFET is removed to form a first connection hole defined by the second insulating film and the sidewall spacer, and the second insulating film is removed within the region defined by the base electrode. forming a second contact hole defined by the second insulating film and a sidewall spacer; A step of removing the insulating film to form a third connection hole, and connecting one end side to the transfer MISF through the first connection hole.
The second insulating film connects a conductive layer connected to one semiconductor region of the ET and whose other end is connected to the gate electrode of the driving MISFET through the third connection hole, and the high resistance load element integrally formed therewith. forming an emitter electrode on the second insulating film and connecting to the emitter region through the second connection hole.