JPH01144630A - Etching of compound semiconductor substrate and device therefor - Google Patents
Etching of compound semiconductor substrate and device thereforInfo
- Publication number
- JPH01144630A JPH01144630A JP30353787A JP30353787A JPH01144630A JP H01144630 A JPH01144630 A JP H01144630A JP 30353787 A JP30353787 A JP 30353787A JP 30353787 A JP30353787 A JP 30353787A JP H01144630 A JPH01144630 A JP H01144630A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- etching
- compound semiconductor
- semiconductor substrate
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 238000005530 etching Methods 0.000 title claims abstract description 37
- 150000001875 compounds Chemical class 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910021478 group 5 element Inorganic materials 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 28
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 8
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 abstract description 6
- 239000007787 solid Substances 0.000 abstract description 4
- 229910052799 carbon Inorganic materials 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 15
- 239000012535 impurity Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000006557 surface reaction Methods 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- -1 InP and AffGaAs Chemical class 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007688 edging Methods 0.000 description 1
- 238000002003 electron diffraction Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は化合物半導体基板のエツチング方法およびその
エツチング装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus for etching a compound semiconductor substrate.
近年、ＩＩ −Ｖ族化合物半導体を用いた高速デバイス
、ヘテロ接合デバイス、光デバイスの開発か急速に発展
し、それに伴う素子製作プロセスも高度化してきている
。In recent years, the development of high-speed devices, heterojunction devices, and optical devices using II-V group compound semiconductors has progressed rapidly, and the associated device manufacturing processes have also become more sophisticated.
トライエッヂング技術は、デバイスの高性能化、高集積
化に欠かせぬ基本プロセス技術であるか、最近ては結晶
加工のみならず、清浄な界面形成技術としても注目され
てきている。Tri-edging technology is a basic process technology that is indispensable for improving the performance and integration of devices, and recently it has been attracting attention not only for crystal processing but also as a technology for forming clean interfaces.
特に基板とエピタキシャル成長層界面、ヘテロ接合界面
、再成長界面の清浄化は、デバイス特性の向上に直接結
びつくため、従来様々な方法が用いられてきた。In particular, various methods have been used to clean the interface between the substrate and the epitaxially grown layer, the heterojunction interface, and the regrowth interface, since this is directly linked to improving device characteristics.
通常の分子線エピタキシャル法（ＭＢＥ法）ではジャパ
ン、ジャーナル、オフ、アプライド、フイジックス（Ｊ
ａｐａｎ Ｊｏｕｒｎａｌ ｏｆ Ａｐｐｌｉｅｄ Ｐ
ｈｙｓｉｃｓ）Ｖｏｌ、２５ １２１６頁＜１９８６年
）に発表されているように、基板を７００℃以上に加熱
して表面の結晶を熱により蒸発させる方法で界面の不純
物を除去している。Conventional molecular beam epitaxial method (MBE method) is used by Japan, Journal, Off, Applied, and Physics (J
apan Journal of Applied P
(1986), impurities at the interface are removed by heating the substrate to 700° C. or higher to evaporate the crystals on the surface.
また反応性イオンヒームエッチング（ＲＴＢ Ｅ法）に
おいては、高真空下でＥ ＣＲイオン源を用いてラジカ
ル化した反応性ガスにより、基板表面をエツチングする
方法が桟用らにより応用物理第５４巻 第１１号（１９
８５年）に報告されている。In addition, in reactive ion beam etching (RTB E method), a method in which the substrate surface is etched using a reactive gas radicalized using an ECR ion source under high vacuum is described by Junyo et al. in Applied Physics Vol. 54. No. 11 (19
It was reported in 1985).
また気相成長法（ＶＩＰ法）では、装置内にあらかしめ
塩酸などの反応性ガスを流し、結晶表面をわずかにエツ
チングした後、結晶を成長する方法がとられている。In the vapor phase growth method (VIP method), a reactive gas such as hydrochloric acid is flowed through the apparatus to slightly etch the surface of the crystal, and then the crystal is grown.
しかし」−述したこれらの方法は以下のような問題があ
る。However, these methods described above have the following problems.
ます、ＭＢＥ法て行われている高温で熱により結晶表面
を蒸発させる方法（サーマルエツチンク′法）では、高
温によりテハイス中の不純物の再分布が生し、ＨＥＭＴ
では移動度の低下、ＭＥＳＦＥＴではしきい値電圧の変
動、Ｉ−Ｉ Ｂ Ｔてはベース層中のＰ型不純物かエミ
ツタ層へ拡散するための電流増幅率βの大幅な減少をそ
れぞれ生しさせる。まなこの方法では、炭素系の不純物
を完全に除去できない。First, in the MBE method, in which the crystal surface is evaporated by heat at high temperatures (thermal etching' method), the high temperature causes redistribution of impurities in the THS, causing HEMT
In MESFETs, this causes a decrease in mobility, a fluctuation in threshold voltage in MESFETs, and a significant decrease in current amplification factor β due to diffusion of P-type impurities in the base layer to the emitter layer. . Manako's method cannot completely remove carbon-based impurities.
次にＲＩ Ｂ Ｅ法によるラジカルエツチング法では、
分子の持つ高いエネルキーにより、基板表面にダメージ
が与えられ欠陥が生じる。さらにイオンやラジカルにス
パッタされた周囲からの不純物をとり込みやすくなり、
清浄な界面を得ることは困難である。Next, in the radical etching method using the RIBE method,
The high energy of the molecules damages the substrate surface and causes defects. Furthermore, impurities sputtered by ions and radicals from the surroundings are easily taken in,
Obtaining a clean interface is difficult.
この中で、Ｖ Ｐ Ｅ法で行われている反応性ガスによ
るエツチングは、基板の表面反応を利用しているのでダ
メージがなく、表面をクリーニングする方法としてはす
ぐれているが、エツチング速度がガス流量、基板温度等
の条件に敏感であるため、制御性が十分と言えず、また
ＭＢＥ等他の真空装置に接続するのも困難である。Among these, etching using reactive gas, which is performed in the VPE method, does not cause damage because it utilizes the surface reaction of the substrate, and is an excellent method for cleaning the surface. Since it is sensitive to conditions such as flow rate and substrate temperature, controllability is not sufficient, and it is also difficult to connect to other vacuum equipment such as MBE.
従って、超高真空中でガスエツチングを行うのが清浄な
界面を得る最適な方法になるが、前述したように基板の
表面反応を利用しているので、初期の表面状態に敏感で
あるという新たな問題か生しる。即ち、基板表面に酸化
膜が残っていると、基板面内でエツチング速度か異なる
ため、完全に平坦な面を得ることができない。Therefore, gas etching in an ultra-high vacuum is the optimal method to obtain a clean interface, but as mentioned above, it uses the surface reaction of the substrate, so it is a new technique that is sensitive to the initial surface condition. There are some problems. That is, if an oxide film remains on the substrate surface, the etching rate will vary within the substrate surface, making it impossible to obtain a completely flat surface.
本発明の目的は、エツチング゛による欠陥や汚染がなく
、平坦な基板表面を形成することのできる化合物半導体
基板のエツチング室１内及びそのエツチング装置を提供
することにある。An object of the present invention is to provide an etching chamber 1 for compound semiconductor substrates and an etching apparatus therefor, which can form a flat substrate surface without defects or contamination caused by etching.
第１の発明の化合物半導体基板のエツチング方法は、真
空容器内の基板ボルタ′にセットした化合物半導体基板
をＶ族元素の分子線照射雰囲気中で加熱して基板表面の
酸化膜を除去する工程と、酸化膜が除去された前記基板
表面に反応性ガスを導入し基板表面をエツチングする工
程とを含んで構成される。The method for etching a compound semiconductor substrate according to the first invention includes the step of heating a compound semiconductor substrate set on a substrate voltage ' in a vacuum container in an atmosphere of molecular beam irradiation of group V elements to remove an oxide film on the surface of the substrate. , and a step of etching the substrate surface by introducing a reactive gas into the substrate surface from which the oxide film has been removed.
第２の発明の化合物半導体基板のエツチング装−５＝
置は、真空容器と、該真空容器内に設けられ化合物半導
体基板を保持しかつ加熱する基板ホルダと、前記真空容
器内にＶ族元素の分子線を照射する分子線源と、反応性
ガスを前記真空容器内に導入するガス導入管とを含んで
構成される。Etching apparatus-5 for compound semiconductor substrates according to the second invention includes a vacuum vessel, a substrate holder provided in the vacuum vessel to hold and heat the compound semiconductor substrate, and a group V element in the vacuum vessel. It is configured to include a molecular beam source that irradiates molecular beams and a gas introduction tube that introduces a reactive gas into the vacuum container.
本発明によれば、化合物半導体基板表面の酸化膜を除去
した後、反応性ガスにより基板表面をエツチングするの
で、完全に平坦で、汚染やダメージのない清浄な基板表
面が形成される。According to the present invention, after removing the oxide film on the surface of a compound semiconductor substrate, the surface of the substrate is etched with a reactive gas, so that a completely flat, clean substrate surface free from contamination and damage is formed.
次に本発明について図面を用いて説明する。 Next, the present invention will be explained using the drawings.
第１図は本発明の化合物半導体基板のエツチング装置の
一実施例の構成図である。FIG. 1 is a block diagram of an embodiment of an etching apparatus for a compound semiconductor substrate according to the present invention.
第１図において超高真空に保持できる真空容器からなる
エツチング室１にはエツチング室を排気する排気装置２
Ａが接続されている。そしてこのエツチング室１内には
半導体基板を保持し、加熱可能な基板ホルダー３が設け
られており、またこのエツチング室１にはマスフローコ
ントローラを有し反応性ガスを導入するガス導入管４と
Ｖ族元素の分子線を照射する分子線源６とが設けられて
いる。尚７はクー１〜ハルフ１０によりエツチング室１
に接続する基板交換室、９は基板を移動させる移動機構
である。In FIG. 1, an etching chamber 1 consisting of a vacuum container capable of maintaining an ultra-high vacuum is equipped with an exhaust device 2 for evacuating the etching chamber.
A is connected. In this etching chamber 1, there is provided a substrate holder 3 which can hold a semiconductor substrate and which can be heated.The etching chamber 1 also has a mass flow controller and a gas inlet pipe 4 for introducing a reactive gas, and a V. A molecular beam source 6 that irradiates a molecular beam of a group element is provided. In addition, 7 is the etching chamber 1 with Ku 1 to Half 10.
9 is a moving mechanism for moving the board.
次にこのように構成されたエツチング装置を用いて化合
物半導体基板をエツチングする方法についての実施例を
説明する。本実施例ではＧ ａ Ａ ３基板を用いた場
合について説明する。Next, an embodiment of a method for etching a compound semiconductor substrate using the etching apparatus configured as described above will be described. In this embodiment, a case will be described in which a G a A 3 substrate is used.
まずＧ ａ Ａ、 ｓ基板を基板交換室７に入れて５×
１０’−”Ｔｏｒｒまで排気装置２Ｂにより排気する。First, put the G a A, s board into the board exchange chamber 7 and
The exhaust device 2B evacuates to 10'-'' Torr.
次にケートバルブ１０を開け、移動機１１１１９により
、ＧａＡｓ基板をエツチング室１に導入し、基板ホルダ
゛−３にセットする。Next, the gate valve 10 is opened, and the GaAs substrate is introduced into the etching chamber 1 by the moving device 11119 and set in the substrate holder 3.
エツチング室］はあらかじめ排気装置２Ａにより、２Ｘ
１０−８Ｔｏｒｒ以下に排気されている。ここて固体Ａ
ｓを入れたＶ族元素の分子線源６を２００℃に加熱して
Ａｓ分子線を発生させ、分圧］、 Ｘ １０−６Ｔ ｏ
、ｒｒのＡｓ雰囲気にして基板を６３０℃に加熱する。Etching chamber] is heated to 2X by exhaust device 2A in advance.
The exhaust pressure is 10-8 Torr or less. Here solid A
A molecular beam source 6 of group V element containing s is heated to 200°C to generate an As molecular beam, partial pressure], X 10-6T o
, rr, and the substrate is heated to 630°C.
この工程を約１０分開校（うることによりＧａＡｓ基板
からのＡｓ抜けを防止しながら、表面の酸化膜を除去て
きる。This process is continued for about 10 minutes to remove the oxide film on the surface while preventing As from being removed from the GaAs substrate.
次に分子線源６の温度と基板温度を下けてＡｓ分子線の
発生を止めたのち、反応性ガスとして塩素ガス（Ｃｒ２
）を、マスフローコントローラ５を介して、ガス導入管
４よりエツチング室１に導入する。塩素ガスの分圧は５
Ｘ１０−’Ｔｏｒｒである。次いでＧａＡｓ基板を３０
０℃に加熱することにより、ＧａＡｓ結晶表面は塩素ガ
スと化学反応をおこしエツチングされる。本実施例では
基板を２０００人エツチングした。Next, after lowering the temperature of the molecular beam source 6 and the substrate temperature to stop the generation of As molecular beams, chlorine gas (Cr2
) is introduced into the etching chamber 1 from the gas introduction pipe 4 via the mass flow controller 5. The partial pressure of chlorine gas is 5
X10-'Torr. Next, the GaAs substrate was
By heating to 0° C., the surface of the GaAs crystal undergoes a chemical reaction with chlorine gas and is etched. In this example, 2000 people etched the substrate.
第２図は本実施例の方法でエツチングした直後のＧａＡ
ｓ基板を反射型高速電子線回折（ＲＨＥＥＤ）により観
察した写真である。このＲＨＥ ＥＤ像は、ストリーク
の超構造パターンを示し、損傷のない平坦な表面が形成
されていることかわかる。Figure 2 shows GaA immediately after etching using the method of this example.
This is a photograph of the s-substrate observed by reflection high-speed electron diffraction (RHEED). This RHE ED image shows a superstructured pattern of streaks, indicating the formation of a damage-free and flat surface.
第３図は比較のため通常のＲＩＢＥ法で、塩素ガスを用
いてエツチングした場合のＧａＡｓ基板表面のＲ，ＨＥ
Ｅ Ｄ像の写真である。第３図においては像はスポラ
ティなパターンとなり、細かな凹凸か存在していること
を示している。またハローが見えており、表面にダメー
ジを受けていることがわかる。For comparison, Figure 3 shows the R and HE of the GaAs substrate surface when etched using chlorine gas using the normal RIBE method.
This is a photograph of the ED statue. In FIG. 3, the image has a sporaty pattern, indicating the presence of fine irregularities. A halo is also visible, indicating that the surface has been damaged.
なお、上記実施例では基板としてＧａＡｓを用いた場合
について説明したが、他にＩｎＰ、ＡｆｆＧａＡｓのよ
うな他の■−■化合物あるいは、その混晶でも同様の効
果か得られた。さらに反応性ガスとして塩素（Ｃ１２）
だけでなく、塩酸（ＨＣｆｆ）、塩化炭素（ＣＣＡ？４
）など化合物半導体と反応するガスはずぺて使用可能で
ある。またＶ族元素の分子線源のソースとしては通常固
体Ａｓが用いられるが、アルシン（ＡＳＨ３）のような
Ｖ族元素を含むガスでも使用可能である。基板がＩｎＰ
の場合は、固体Ｐあるいはボスフィン（ＰＨ３）でもか
まわない。In the above embodiments, the case where GaAs was used as the substrate was explained, but similar effects could be obtained using other 1-2 compounds such as InP and AffGaAs, or mixed crystals thereof. Furthermore, chlorine (C12) is used as a reactive gas.
as well as hydrochloric acid (HCff), carbon chloride (CCA?4
) and other gases that react with compound semiconductors can be used. Furthermore, although solid As is normally used as a molecular beam source for group V elements, gases containing group V elements such as arsine (ASH3) can also be used. The substrate is InP
In this case, solid P or boss fin (PH3) may be used.
以上述へたように本発明によれは、化合物半導体基板に
汚染や欠陥を導入することなく表面を平坦にエツチング
でき、清浄な界面を形成できる化金物半導体基板のエツ
チング方法およびそのエツチング装置が得られる。従っ
て化合物半導体を用いたデバイスの特性は向」ニする。As described above, the present invention provides an etching method and an etching apparatus for a compound semiconductor substrate, which can flatten the surface of the compound semiconductor substrate without introducing contamination or defects, and can form a clean interface. It will be done. Therefore, the characteristics of devices using compound semiconductors will improve.
第１図は本発明の化合物半導体基板のエツチング装置の
構成図、第２図は本発明のエツチング方法によりエツチ
ングされたＧａＡｓ基板表面のＲＨＥ Ｅ Ｄ像の写真
、第３図は従来法によるＧａＡｓ基板のＲＨＥ Ｅ Ｄ
像の写真である。
１・・エツチング室、２Ａ、２Ｂ・排気装置、３・・・
基板ホルダ−１４・・・ガス導入管、５・マスフローコ
ン１〜ローラ、６・・・分子線源、７・・基板交換室、
９ ・移動ａ構、１０・・ケートバルブ。Fig. 1 is a block diagram of an etching apparatus for a compound semiconductor substrate of the present invention, Fig. 2 is a photograph of a RHEED image of the surface of a GaAs substrate etched by the etching method of the present invention, and Fig. 3 is a photograph of a GaAs substrate etched by the conventional method. RHE E D
This is a photo of the statue. 1... Etching chamber, 2A, 2B, exhaust system, 3...
Substrate holder - 14... Gas introduction pipe, 5. Mass flow controller 1 to roller, 6... Molecular beam source, 7... Substrate exchange room,
9. Moving a structure, 10. Kate valve.
Claims (2)
体基板をＶ族元素の分子線照射雰囲気中で加熱して基板
表面の酸化膜を除去する工程と、酸化膜が除去された前
記基板表面に反応性ガスを導入し基板表面をエッチング
する工程とを含むことを特徴とする化合物半導体基板の
エッチング方法。(1) A step of heating a compound semiconductor substrate set in a substrate holder in a vacuum container in an atmosphere of molecular beam irradiation of group V elements to remove an oxide film on the substrate surface, and 1. A method for etching a compound semiconductor substrate, the method comprising the step of etching the surface of the substrate by introducing a reactive gas.
体基板を保持しかつ加熱する基板ホルダと、前記真空容
器内にＶ族元素の分子線を照射する分子線源と、反応性
ガスを前記真空容器内に導入するガス導入管とを含むこ
とを特徴とする化合物半導体基板のエッチング装置。(2) a vacuum container, a substrate holder provided in the vacuum container to hold and heat a compound semiconductor substrate, a molecular beam source to irradiate a molecular beam of a group V element into the vacuum container, and a reactive gas An etching apparatus for a compound semiconductor substrate, comprising: a gas introduction pipe introduced into the vacuum container.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30353787A JPH01144630A (en) | 1987-11-30 | 1987-11-30 | Etching of compound semiconductor substrate and device therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30353787A JPH01144630A (en) | 1987-11-30 | 1987-11-30 | Etching of compound semiconductor substrate and device therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01144630A true JPH01144630A (en) | 1989-06-06 |
Family
ID=17922186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30353787A Pending JPH01144630A (en) | 1987-11-30 | 1987-11-30 | Etching of compound semiconductor substrate and device therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01144630A (en) |
-
1987
- 1987-11-30 JP JP30353787A patent/JPH01144630A/en active Pending
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