JPH01143566U - - Google Patents
Info
- Publication number
- JPH01143566U JPH01143566U JP3834388U JP3834388U JPH01143566U JP H01143566 U JPH01143566 U JP H01143566U JP 3834388 U JP3834388 U JP 3834388U JP 3834388 U JP3834388 U JP 3834388U JP H01143566 U JPH01143566 U JP H01143566U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- voltage
- circuit
- video signal
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
- Picture Signal Circuits (AREA)
Description
第１図は本考案に係る同期分離回路の一実施例
を示すブロツク図、第２図は第１図に示す実施例
の具体的回路の一例を示す回路図、第３図は第２
図の回路の動作を説明するための波形図、第４図
は従来の同期分離回路の構成を示す回路図、第５
図は第４図に示す回路の動作を説明するための波
形図、第６図はその拡大図である。
１１，１３……第１、第２のクランプ回路、１
２……増幅器、１４……スライス回路、１５，２
８……コンデンサ、１７，１８……抵抗、１９，
３０，３４……ダイオード、２２，２５，３６…
…トランジスタ、３３……ツエナーダイオード。
FIG. 1 is a block diagram showing an embodiment of the synchronous separation circuit according to the present invention, FIG. 2 is a circuit diagram showing an example of a specific circuit of the embodiment shown in FIG.
Figure 4 is a waveform diagram to explain the operation of the circuit shown in Figure 4. Figure 4 is a circuit diagram showing the configuration of a conventional synchronous separation circuit.
This figure is a waveform diagram for explaining the operation of the circuit shown in FIG. 4, and FIG. 6 is an enlarged view thereof. 11, 13...first and second clamp circuits, 1
2...Amplifier, 14...Slice circuit, 15,2
8... Capacitor, 17, 18... Resistor, 19,
30, 34...diode, 22, 25, 36...
...Transistor, 33...Zener diode.
Claims (1)
クランプする第１のクランプ回路と、 前記第１の電圧に基づいて動作点が決定され前
記第１のクランプ回路からの映像信号を非飽和領
域で増幅出力するトランジスタと、 このトランジスタから供給される映像信号の同
期信号先端レベルを第２の電圧でクランプする第
２のクランプ回路と、 この第２のクランプ回路からの信号を所定レベ
ルでスライスして同期信号部分のみを出力するス
ライス回路とを具備したことを特徴とする同期分
離回路。[Claims for Utility Model Registration] A first clamp circuit that clamps the leading edge level of a synchronizing signal of a video signal to a first voltage; and an operating point determined based on the first voltage; a transistor that amplifies and outputs a video signal in a non-saturation region; a second clamp circuit that clamps the synchronization signal tip level of the video signal supplied from this transistor with a second voltage; 1. A sync separation circuit comprising: a slicing circuit that slices a signal at a predetermined level and outputs only a sync signal portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3834388U JPH01143566U (en) | 1988-03-25 | 1988-03-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3834388U JPH01143566U (en) | 1988-03-25 | 1988-03-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01143566U true JPH01143566U (en) | 1989-10-02 |
Family
ID=31264898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3834388U Pending JPH01143566U (en) | 1988-03-25 | 1988-03-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01143566U (en) |
-
1988
- 1988-03-25 JP JP3834388U patent/JPH01143566U/ja active Pending
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