JPH01143264A - Field effect semiconductor element - Google Patents

Abstract

PURPOSE:To assure high speed travelling of electrons in both weak and strong electric fields by providing a first semiconductor layer where an active layer has a high mobility in a weak electric field and a second semiconductor layer where an active layer has a high traveling speed, and further allowing an actual space transition of carriers by hot electrons. CONSTITUTION:A high concentration InGaAs layer 32 of thickness of 0.2-1mum is first formed on a semi-insulating InP substrate 33 by lattice-maching. The crystal layer is preferably highly purified for increasing the operation speed of the device. Next, an InP layer 31 of thickness less than 1000Angstrom is formed. Electrons induced in the semiconductor layer 32 near a source 36 are accelerated in the semiconductor layer and traveled, but they changes to hot electrons as the electric field is increased. The electrons make actual space transition to the adjacent semiconductor layer 31 in the vicinity of the electric field intensity Ep1. Thereafter, the electrons travel in the semiconductor layer 31 and reach a drain region 37.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a field effect semiconductor device, and in particular to a field effect semiconductor device having an active layer formed by laminating a plurality of ■-■ compound semiconductor layers. It relates to conductive elements.

``Prior art'' ■- Group V compound semiconductors outperform silicon semiconductors in terms of high speed, so the development of electronic devices using them is currently being actively carried out.The one that is currently being put into practical use is a Schottky semiconductor using GaAs. Although gate-type field effect transistors (hereinafter abbreviated as FETs) are used in the fields of ultra-high-speed information processing and communication, it is desired to improve the device characteristics of the negative layer, and new device structures and new materials are being proposed.

[Problems to be solved by the invention] In FET type devices, electrons (or holes) that carry signals are appropriately induced in the channel region by gate voltage, and furthermore, by the electric field applied between the source and drain electrodes. is accelerated and travels along the channel, forming an electric current. It is known that the traveling speed V of electrons, which determines the operating speed of the device, depends on the electric field E. That is, when electrons are accelerated in III-V compounds, they are accelerated near point F at the conduction band edge of the energy band, but under a high electric field, as the energy increases, they become hot electrons, and finally r-L
This causes a transition, and the 10-line speed actually decreases. Therefore, in order to realize high-speed operation of the device, it is effective to consider the v-E relationship specific to the material and adopt a device structure that overcomes the speed reduction, especially in the high electric field region.

The present invention has been made based on these viewpoints, and an object of the present invention is to provide a field effect semiconductor device capable of high-speed operation.

[Means for Solving the Problems] The present invention relates to a field effect semiconductor device in which an active layer formed by stacking a plurality of IV compound semiconductor layers is combined.

The active layer includes a first semiconductor layer that has high mobility in a low electric field and a second semiconductor layer that has a high traveling speed in a high electric field, and hot electrons are generated between the first and second semiconductor layers. The carrier is made to perform real space transition.

[Function] The active layer includes a first semiconductor layer having high mobility in a low electric field and a second semiconductor layer having a high traveling speed in a high electric field, and hot electrons are transferred between the first and second semiconductor layers. Since the real space transition of carriers is caused by , electrons can travel at high speed in both low and high electric field regions.

[Example] FIG. 1 is a diagram for explaining the present invention in detail. 1st
In the figure, the upper diagram shows the lateral electric field strength distribution in the channel of the FET. As is well known, there is a relatively low electric field (<10 kV/cm) on the source side, whereas a high electric field (>10 kV/cm) exists near the drain. In FIG. 1, the lower diagram illustrates how electrons travel from the source to the drain in an active layer made up of two stacked semiconductor layers. Electrons induced in the semiconductor layer 11 near the source are accelerated and travel in the semiconductor layer 1, but as the electric field increases, they become hotter and transfer to the adjacent semiconductor layer 12 in real space near the electric field strength Epl. do. Thereafter, it travels through the semiconductor layer 12 and reaches the drain region. In the figure, Ep+ + Ep2 is
The electric field strength when the electron velocity in the first and second semiconductors reaches its peak is shown.

One of the preferred embodiments of the semiconductor stack constituting the above active layer can be constructed using InGaAs and InP. FIG. 2 is an explanatory diagram thereof. GaAs has a higher electron mobility than GaAs in a low electric field region, and is used for the semiconductor layer 11 in FIG. Next, InP has a higher traveling speed than GaAs in the high electric field region,
This is used for the semiconductor layer 12 in FIG.

Several device structures can be constructed using the operating principles described above. We will discuss them below.

FIG. 3 is a sectional view showing a metal/insulating film/semiconductor type transistor (MISFET) according to an embodiment of the present invention. In the figure, 33 is a semi-insulating InP substrate, 32 is InP
Lattice matching 1 nI-X Ga provided on the substrate 33
x As semiconductor layer (X-0°47), 31 is an InP semiconductor layer, 34 is a gate insulating layer, 35 is a gate electrode, 36 is a source electrode, and 37 is a drain electrode.

Next, FIG. 4 shows an energy band diagram of this semiconductor element when a positive voltage is applied to the gate electrode 35. At this time, InP is 1.35 eV and InGaAs is 0.8 eV.
, both layers have different energy gap values.

When the gate voltage is vG, an electric field approximately expressed by the following equation is applied to the InP layer 31.

In the above equation, ε+, d+ (or ε2+d2) represent the dielectric constant and thickness of the gate insulating film (or InP layer). When the electric field in the lateral direction (source/drain direction) is weak,
The device is configured such that the channel is formed on the InGaAs surface in contact with InP. At this time, in order to prevent a new channel from being formed on the InP surface in contact with the gate insulating film, it is desirable that the condition E2d2<ΔEc be satisfied.

Here, ΔE is the c between InGaAs and InP.

production band discont
Represents intuitiveness.

Sunaitsuchi, It is.

As is clear from equation (1), the thickness of the InP layer 31 according to this embodiment depends on the operating voltage, but is preferably about 1000 at most. When an electric field as shown in Figure 1 is applied between the source and drain of this device, electrons travel through the InGaAs channel layer from the source to the drain, but the peak value of the electron velocity with respect to InGaAs is Near the position of the applied electric field strength (El) , InP is attracted by the gate electric field.
/transitions to the gate insulating film interface, flows there toward the drain, and contributes to the signal current. At this time, although the speed decreases in an electric field region larger than that of InP El)2, the effect is much smaller than that of the InGaASnGaAs layer.

The manufacturing method of the FET of this example will be explained with reference to FIG.

First, an InGaAs layer 32 with a thickness of 0.2 to 1 μm is lattice-matched to the InP substrate 33 and formed on the semi-insulating InP substrate 33 using a method capable of high-purity crystal growth such as MOCVD or halide VPE. . This crystal layer should be as pure as possible, preferably n
<101s to 10110l6' is desirable.

Next, an InP layer with a thickness <100 OA is subsequently formed. Next, the gate insulating film 34 is formed by using a low-temperature insulating film forming method with low radiation damage, such as photo-CVD or ECR plasma CVD, to form S to 2, Si N, or PON.

A film of PAsO or a composite film thereof is formed. Next, the gate electrode 35 is formed using Al using the EB dilution method or W using the sputtering method, and further processed into a shape having a predetermined element dimension L/W using photolithography. The source/drain portions 36 and 37 of this device are preferably doped with impurities by a method such as Si+ ion implantation, as indicated by dotted lines 38 in FIG.
The corresponding portion of 4 is removed by etching, and an electrode made of AuGe or the like is formed by a combination of vacuum evaporation method and lift-off method to complete the device.

Although an amorphous film is used as the gate insulating film in this embodiment, it is also possible to use a wide-gap compound semiconductor such as InA (LP, GaAllAs, etc.).

Next, FIGS. 5, 6, and 7 show band profiles of other embodiments of the present invention (provided that no gate voltage is applied). Figure 5 shows MISF as in Figure 3.
Although it has an ETfM structure, InAQAsnGa which lattice matches the InGaAs layer 52 and the InP layer 51 is placed between the InGaAs layer 52 and the InP layer 51.
There is an As layer 53. In this layer, especially when the device is operated at a high gate voltage, the unhot electrons become In
It functions as a barrier layer that transitions from the GaAs layer to the InP layer and prevents the formation of a new channel layer. 6th
The figure shows an InGaAs layer 6 in a structure similar to that in FIG.
2 is a quantum well with an InAQAsnGaAs layer 63, and the subband level is determined by the well width.
Controls transition to nP layer 61.

FIG. 7 shows a layer of InAl1 that is lattice-matched to the laminated active layer consisting of an InGaAs layer 72 and an InP layer 71.
It has an As layer 73 and a metal electrode 75 on its surface to form a Schottky structure, which avoids the instability of the gate insulating film/semiconductor active layer interface, which is a problem in MISFETs, and enables stable operation. It is characterized by the fact that

In addition, in this example, 1nP, InGaAs.

Although a lattice-matched system such as InA or As has been described, it is of course possible to construct an element using a mismatched semiconductor thin layer such as a strained superlattice.

[Effects of the Invention] As explained above, the field effect semiconductor device according to the present invention has a semiconductor active layer formed by stacking a plurality of ■-■ compounds with different energy gaps, and hot electrons are generated between these semiconductors. By creating a real space transition due to Therefore, conventional GaAsFE
High-speed operation is possible compared to T and the like. Furthermore, high-speed devices with large voltage amplitude, high driving ability, or large output can be constructed. Furthermore, by combining a plurality of 1-2 compounds with different energy gaps Eg, it is possible to form a high-performance transistor using a two-dimensional electron gas suitable for ultra-high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the present invention in detail. Second
The figure is a diagram illustrating the dependence of electron velocity on electric field strength in various semiconductor devices. FIG. 3 shows MI of an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the structure of an S-type field effect transistor. FIG. 4 shows an energy band diagram when a positive voltage is applied to the gate electrode. 5 to 7 show energy band diagrams of field effect transistors according to other embodiments of the present invention. In the figure, 11.32 is a first semiconductor layer that has high mobility in a low electric field, and 12.31 is a second semiconductor layer that has a high traveling speed in a high electric field. Collection 10 Volume 20 Arithmetic 34 Volume 40 II, 32: (%Electrification y+=s=t4uzTh&t*
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Claims (1)

[Claims] (1) A field effect semiconductor device having an active layer formed by laminating a plurality of III-V compound semiconductor layers, the active layer comprising a first semiconductor layer having high mobility in a low electric field and a first semiconductor layer having high mobility in a high electric field. a second semiconductor layer having a high traveling speed in the field-effect semiconductor device, wherein real space transition of carriers by hot electrons is performed between the first and second semiconductor layers.