JPH01140876A - Picture information transmitter - Google Patents

Abstract

PURPOSE:To prevent the generation of encoding distortion even for a block containing a boundary by performing encoding by considering both a dynamic range and the statistic distribution of picture elements in the block. CONSTITUTION:An NTSC television signal after being made into the block by a blocking circuit 12 is impressed to a minimum value detector 14, a maximum value detector 16, an intra-block means value detector 18 and delay circuits 20, 22, 24, 26. The output of the maximum value detector 16 and the output of the minimum value detector 14 are impressed to a subtracter 28. The outputs of the minimum value detector 14, the subtracter 28, the maximum value detector 16 and the means value detector 18 are impressed to encoders 34, 36 through the delay circuits 30-33 respectively. Besides, the outputs of the delay circuits 22, 24 are impressed to the encoders 34, 36 through selection circuits 42, 44 and the means value detectors 48, 50, and the output of the delay circuit 26 is impressed to the encoder 36. An index signal is outputted from the encoder 36, and the encoded television signal is outputted from the encoder 34.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image information transmission device that encodes and transmits image data in blocks.

[Conventional technology]

As a method for narrowing the transmission band of television signals, an encoding method is known in which the sampling frequency or the average number of bits per pixel is reduced. In the former encoding method, the image data is thinned out to 172 by subsampling, and the subsampling point and the position of the subsampling point used during interpolation are indicated (i.e., which subsampling point above, below or to the left or right of the interpolation point is indicated). A flag indicating whether the data is used is transmitted.

On the other hand, as one of the latter encoding methods, there is a block encoding method in which the screen within the l field is subdivided into minute blocks and encoded. In this encoding method, for example, the block of interest is quantized linearly or non-linearly between its minimum value and maximum value, an index indicating which quantization level each pixel belongs to is transmitted, and furthermore, as a scale component, The minimum value and maximum value are transmitted.

[Problem that the invention seeks to solve]

In this conventional block encoding method, encoding is performed according to the dynamic range of pixel values within a block, but for example, when there is extreme brightness or darkness within a block, or when a block contains a boundary, etc. , when the distribution of pixel values is significantly different from the expected state, large distortion occurs in the decoded signal.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image information transmission device that causes less decoding distortion when transmitting image information.

[Means for solving problems]

An image information transmission apparatus according to the present invention includes: a blocking circuit that divides digital image data into blocks each consisting of a predetermined number of samples; and a first data forming means that forms at least two reference values regarding a dynamic range for each block. , a second data forming means for forming distribution status data indicating the distribution status of the sample values within the block, and a first encoding mode for encoding the samples within the block based on two reference values of the first data forming means; The second encoding mode encodes samples within a block based on the two reference values of the first data forming means and the distribution situation data of the second data forming means, and both types of encoding are performed according to the dynamic range of each block. encoding means for encoding each sample in one of the modes to form encoded data;
In the encoding mode, the two reference values and the encoded data of each sample by the first data forming means are the transmission unit, and the second
In the encoding mode, the present invention is characterized by comprising transmission data forming means for forming a transmission data string using two reference values, distribution situation data, and encoded data of each sample by the first data forming means as transmission units.

[Effect]

With the above means, appropriate encoding can be performed according to the dynamic range within the block. Furthermore, it becomes possible to appropriately deal with cases where boundaries exist within blocks.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of a television signal encoding apparatus as an embodiment of the present invention. In Figure 1,
10 is an input terminal for a digital image signal. In this embodiment, an NTSC television signal in which one sample is quantized to 8 bits is input. The blocking circuit 12 is
The signal applied from the input terminal 10 in units of horizontal scanning lines is
Edit and output the scanning order for each horizontal scanning line within a block. In the illustrated embodiment, there are 4 samples horizontally and 4 samples vertically.
A line is defined as one block. The sample sequence rearranged by the blocking circuit 12 is processed by a minimum value detector 14, a maximum value detector 16, an intra-block average value detector 18 and a delay circuit 2.
Applied to 0, 22, 24.26. The subtractor 28 calculates the difference between the maximum value MAχ detected by the maximum value detector 16 and the minimum value MIN detected by the minimum value detector 14.

Output MIN of minimum value detector 14, output O of subtractor 28
R (= MAX - old N), output MAX of maximum value detector 16
, and the output m0 of the average value detector 18 are applied to the encoders 34 and 36 via delay circuits 30, 31, 32, and 33, respectively.

The comparator 38 compares each sample in the block delayed by the delay circuit 20 with the average value m0 from the average value detector 18, and outputs 1 when it is greater than mo, and outputs O when it is less than m0. Reference numeral 40 denotes a cluster ring memory having a capacity of 16 bits, which stores the comparison results of the comparator 38 for one block with l bits per l sample, and outputs them as gate pulses to the selection circuits 42 and 44. 1"
When it is "0", rHJ is output, and when it is "0", rLJ is output. A signal inverted by an inverter 46 is applied to the selection circuit 42 . That is, the selection circuit 42 passes only the samples of m0 or less (subblock 1) among the outputs of the delay circuit 22, and the selection circuit 44 passes only the samples of the output of the delay circuit 24,
Only samples larger than mo (subblock 2) are passed. The mean value detector 48 detects the mean value m1 of the samples in sub-block 1 and applies it to the encoder 34.36, and the mean value detector 50 detects the mean value m2 of the samples in sub-block 2 and applies it to the encoder 34.36. applied to encoders 34 and 36.

The output DT of the delay circuit 26 is applied to the encoder 36 as is. Note that the delay circuits 20 to 26 and 30 to 33 are connected for the purpose of timing adjustment.

The encoder 36 receives each input signal mo+m++mz+MI
N. MAX.

An index 10 of 3 bits per sample is formed from DR and DT and applied to the encoder 34.

The encoder 34 outputs a code, which will be described later, from an output terminal 52 to a transmission path (not shown).

FIG. 2 shows a specific example of the configuration of the encoder 36.

Sample values DT input from input terminal 54 are applied to encoders 56, 58, and 60. The MIN and MAX input manually from the input terminals 61, 62 are input to the encoders 56, 58.
60 and input from the input terminal 63 is applied to the encoder 58.60, and m, . . . mt input from the input terminal 64.65 are applied to the encoder 60. In this embodiment, the encoder 56 encodes the DT in an operation mode (stage O) that equally divides the dynamic range into eight, and the encoder 58 divides the dynamic range into four equal parts, The encoder 60 encodes DT in an operation mode (stage 1)' in which the space between mo and MAX is divided into four equal parts (total of eight parts), and the encoder 60 equally divides the space between MIN and signal into two parts, m, and mo
The DT is encoded in an operation mode (stage 2) in which the space between m and m is divided into two equal parts (total of eight parts). 'Stage 0. 1. An example of 2 divisions is shown in FIG.

Each encoder 56, 58, 60 outputs an index of 10 with 3 bits per sample.

The selector 68 selects the dynamic range OR of the intra-block sample values from the input terminal 66 as two dark values T)11. TH2 (THI<TH2), when DR<TRI, the output of the encoder 56 is selected, when THI≦DR<TH2, the output of the encoder 58 is selected, and when TI2≦DR, the output of the encoder 58 is selected. Select the output of encoder 60. Index I selected by selection circuit 68
D is supplied to the encoder 34 via the output terminal 70.

FIG. 3 shows a specific example of the encoder 56. The subtracter 72 is M
MIN is subtracted from AX and a signal indicating the dynamic range DR is output. This dynamic range is divided into 178 by divider 74 and then fed directly to comparator 81 and via multipliers 75-80 to comparators 82-87. Multipliers 75 to 80 multiply the input signal by 2 and 3, respectively.
Multiply - Multiply by 7.

The subtracter 88 subtracts MIN from the sample value DT in the block, and applies the subtraction result DT'' to the comparators 81 to 87. Each comparator 81 to 87 outputs the comparison result C1 to C7.
is supplied to the priority encoder 90. Depending on the output DT' of the subtractor 88, 01 to C7 are as follows.

(1) 0≦DT"< (1/8) DRCI・C2・C
3・C4=C5=C6=C7・0(2) (1/8)
DR≦DT” < (2/8) DRC1=1.C2
・C3=C4・C3=C6=C7=0(3) (2/
8) OR≦DT'<(3/8)ORC1=C2=1
, C3=C4=C5=C6=C7=0(4)
(3/8) OR≦DT″ < (4/8) DRCbC
2・C3=1. C4=C5=C6=C7=0(5)
(4/8)OR≦DT'<(5/8)ORC1=
C2=13・C4=1, C3=C6・C7・0
(6) (5/8)DR:5DT'<(6/8)O
RC1・C2・C3, C4・C5・1. C6・C7=0
(7) (6/8)DR6DT” < (7/8)D
RC1=C2=C3=C4=C5=C6・1. C7・0
(8) (7/8) DR≦DT'<DRC1=C
2・C3=C4・C5・C6・C7・1 The priority encoder 90 is (000) in the above (1), (
2) (001), (3) (010),
When +41 (011), (When 51 (work 00),
(6) (101), (7) (110),
(81), a 3-bit code of (111) is output. This output is applied to the selection circuit 68 (FIG. 2).

FIG. 4 shows details of encoder 58. A subtracter 100 subtracts MIN from the sample value DT, and a subtracter 102 subtracts MIN from the sample value DT.
MIN is subtracted from MAX, and the subtracter 104 subtracts m6 from MAX. The output (mo-MIN) of the subtracter 102 is divided into 1/4 by the divider 106, and then the multiplier 107.10
8 and comparator 110. Multiplier 107.10
8 is a comparator 111 which doubles and triples the input signal, respectively.
．． 112. Output of subtracter 104 (MAX-m
o) is divided into 174 by the divider 114, and then the multiplier 115
, 116 and an adder 117. Multiplier 115
．． 116 doubles and triples the input signal, respectively, and adds adder 1.
18,119. Adder 117, 118.11
The output of the subtracter 102 is applied to 9, and the addition result is applied to one input of comparators 120, 121, 122, and 123. Comparator 110-112.120-1
The other input of 23 is the output DT' (
=DT-MIN) is supplied.

The outputs of comparators 110-112, 120-123 are 01-
C7, the following 01 to C7 are input to the priority encoder 124 in each case. That is, (1) 0≦DT'<(1/4)(mo-MIN)C1
, C2=C3=C4, C3=C6=C7-0(21(1
/4)(Ilo-MIN)≦DT'<(2/4)(a+
o-MIN)C1=1. C2=C3=C4=C5=C
6=C7=0(3) (2/4)(IIIo-MIN
)≦DT'<(3/4) axis. -MIN)C1=C2=1
, C3=C4-C5, C6=C7=0(4) (
3/4) (mo-MIN)≦DT'<mo-MINC
l, C2・C3=1. C4・C3=C6・C7-0(
5) m (1-M I N≦DT'< (1/4)
(MAX-mo) + (me-MIN)C1=C2
=C3=C4=1, C5・C6・C7・0(6)
(1/4) (MAX-mo) + (mo-MIN)
≦DT'<(2/4)(MAX-mo)+(mo-M
IN) C1=C2 tonnage C3=C4=C5=1. C6=C7・0
(7) (2/4)(MAX-mo)+(IIIo-M
IN) ≦DT'<(3/4)(MAX-mo)+(m
o-MIN) C1=C2=C3=C4=C5=C6=1, C7=
0 (8) (3/4) (MAX-116) + (11
10-MIN) ≦DT'<MAX-old Ncl=
c2=c3=c4=c5=c6=c7.1 Priority encoder 124 encodes encoder 56 in each case.
Outputs the same 3-bit index 10 as in the case of
This output is applied to selection circuit 68 in FIG.

FIG. 5 shows details of the encoder 60. The subtracter 130 subtracts MIN from the sample value DT, and the subtracter 132 subtracts ll
MIN is subtracted from 1l, and the subtracter 134 subtracts l from mo.
subtractor 136 subtracts MIN from mo, subtractor 138 subtracts mo from m, subtractor 140 subtracts m
! MIN is subtracted from MAX, and the subtracter 142 subtracts J from MAX. Dividers 144, 145, 146.147 respectively set the outputs of subtracters 132, 134°138.142 to 172, adder 148 adds the output of subtracter 132 to the output of divider 145, and adder 149 Divider 14
The output of the subtracter 136 is added to the output of the adder 150.
adds the output of the subtracter 140 to the output of the divider 147.

One of the inputs of the comparator circuits 151 to 157 has, respectively,
Output of divider 144 (1/2) (m+ -MIN)
, the output of the subtracter 132 (m+-old N), the output of the adder 148 (m+-MIN)+(1/2) (n+o-m+)
, the output of the subtracter 136 (mo-MIN), the adder 14
Output of 9 (mo-MIN) + (1/2) (mz-
m. ), the output of the subtracter 140 (llz-MIN) and the output of the adder 150 (mz-old N) + (1/2) (MA
X-mz) is applied, and the other input is a subtracter 130
The output DT' (=DT-MIN) is applied.

Assuming that the outputs of the comparators 151 to 157 are 01 to C7, the results are as follows depending on each case.

(1) 0≦DT”<(1/2)(m+-MIN)C1
・C2'=C3=C4=C5=C6・C7・0(2)
(1/2) (o++-MIN)≦DT'<m, -MI
NCI=1. C2, C3=C4=C5・C6,C7=
0(3) m+-MIN≦DT'< (1/2) (
m. -1+)+(m+-MIN)C1-C2=1,
C3・C4=C5・C6=C7,0(4) (1/2
)(1116-111)+(1111-MIN)≦DT
'<no-MINC1=C2-C3=1. C4・C5
・C6=C7・0(5) mo-MIN 5DT'<(
1/2) (mz-mo)+(me-MIN)C1=C2
=C3=C4=1, C5,C6=C7,0(6)
(1/2Xtz-IIIo)+(mo-MIN)≦D
T'<m, -MINCI=C2=C3・C4=C5・
1. C6・C7=0(71mz-MIN≦DT'
<(1/2) (MAX-mz) + (mz-MIN
)C1=C2=C3=C4=C5=C6・1,
C7=0(81(1/2)(MAXlg)+(mz-M
IN) ≦DT'<MAX-MINCl・C2=C
The priority encoder 158 outputs in each case a 3-bit index ID similar to that of the encoder 56.58, and this output is used by the selection circuit of FIG. 68.

FIG. 6 shows details of the encoder 34. Selection circuit 16
0 is the dynamic range DR and the predetermined darkness values THI, T
Depending on the relationship with H2, nothing is output when OR<TI (1) (stage O), mo is output when TH1≦DR<TI2 (stage 1), and when TH2≦DR (Stage 2) outputs mo+ml+Il!.The blocking circuit 162 serially outputs each manually input code string as a code string shown in FIG. In stage 1, each input code string is serially output as the code string shown in FIG. 7(b), and in stage 2, each input code string is output as shown in FIG. 7(c).
Output serially as the code string shown in .

FIG. 9 shows a schematic configuration of a digital television signal decoding apparatus to which the present invention is applied, which corresponds to the encoding apparatus shown in FIG. A digital random revision signal input from a transmission line (not shown) is applied from an input terminal 200 to a MIN/MAX separation circuit 202 and a data separation circuit 204. M.E.
The N/MAX separation circuit 202 separates the additional codes MIN and MAX.
X is separated, and the subtracter 206 separates MAX and MIN
(7) Find the difference DR (-MAX-MIN) and apply it to the decoder 208 and data separation circuit 204. According to DR, the data separation circuit 204 extracts llo+m from the input code string.
++mz+ID is separated and supplied to decoder 208.

The decoder 208 is also supplied with MAX and MIN from the MIN/MAX separation circuit 202 . Since the output of the decoder 208 is obtained by removing the MIN level as will be described later, by adding the old N in the adder 210, the digital television signal is restored and output from the output terminal 212. Note that the delay device 214 is for time adjustment.

FIG. 10 shows the detailed configuration of decoder 20B.

220 is a decoder for stage 0, 221 is a decoder for stage 1, and 222 is a decoder for stage 2. Old N, MAX, IO are applied to the decoder 220, MIN, MAX+ID+mo are applied to the decoder 221, and MIN+MAX+ID+f is applied to the decoder 222.
f1O+ mu + mz is applied. Selection circuit 22
4 is an OR and a predetermined threshold value THI, TI(2(THI<T
I2), one of the outputs of the decoders 220, 221, and 222 is selected and output. This output is provided to adder 210.

FIG. 11 shows the detailed structure of the decoder 220 for stage 0. The subtracter 226 ORs the old N and MAX (・MA
X-MIN) and supplies it to the divider 228.

The divider 228 divides the input into 1/8 and divides the input into multipliers 230-2.
36 and selection circuit 238. Multiplier 230-2
36 respectively doubles, triples, quadruples, fives, and six times the input signals.
The result is multiplied by 7 times and applied to the selection circuit 238. Selection circuit 23
8 is "0", r (1/8) according to the index ID
DRJ, r (2/8) ORJ, “(3/8) DRJ, r
(4/8) DRJ, r (5/8) DRJ, "(678)
DRJ and r(7/8)DI? Select one of J.

The divider 240 and the adder 242 are for setting a representative value.The divider 240 halves the output of the divider 228, and the adder 242 divides the selected output of the selection circuit 238 into the divider 2.
Add the outputs of 40. The output of adder 242 is supplied to selection circuit 224 (FIG. 10).

FIG. 12 shows a detailed configuration of the decoder 221 for stage 1. The subtractor 244 is m. and MIN, and the subtracter 246 calculates the difference between MAX and mo.

Divider 248 outputs the output of subtracter 244 (ffi.-MIN
) is set to 178 and supplied to multipliers 249, 250, 251 and selection circuit 252. Multiplier 249, 250°2
51 multiply the input signal by three times, five times, and seven times, respectively, and supply the multiplied signals to the selection circuit 252. Divider 254 sets the output (MAX-m,) of subtracter 246 to 178, and multiplier 255.2
56, 257 and an adder 258. Multiplier 25
5, 256, and 257 multiply the input signals by 3, 5, and 7, respectively, and apply them to adders 259, 260, and 261.

Each adder 258 to 261 receives the output of the subtracter 244 (IQ-
MIN) is added and supplied to the selection circuit 252. The selection circuit 252 selects r (1/8) according to the encoding code ID.
(mo-MIN)' J, "(378) (mo-MI
N) J, r (5/8) (mo-MIN) J, r
(7/8) (rao-MIN) J, r (1/8)
(MAX-mo) + (no-MIN) J, r (
3/8) (MAX-me)+ (mo-MIN) J
, r (5/8) (MAX-mo)+(ms-MIN
) J and r (5/8) (MAX-mo)+(mo
-MIN) Select and output one of J. This selection output is applied to selection circuit 224 (FIG. 10).

FIG. 13 shows the detailed configuration of the decoder 222 for stage 2. The subtracter 270 subtracts the old N from m, and subtracter 2
71 subtracts m from mo, subtracter 272 subtracts MIN from mo, subtracter 273 subtracts mo from mt, subtracter 274 subtracts MIN from mt, subtracter 27
5 subtracts the town from MAX. Divider 276 is subtracter 2
The output (mt-MIN) of 70 is set to 174, and the divider 27
7 becomes 3/4. The divider 278 makes the output (no-mt) of the subtracter 271 174, and the divider 279 makes it 3/4. The adder 280 connects the subtracter 27 to the output of the divider 278.
The adder 281 adds the output of the subtracter 270 to the output of the divider 279. The divider 282 sets the output (mz-me) of the subtracter 273 to 174 and divides the output (mz-me) of the subtracter 273 to 174.
83 becomes 3/4.

The adder 284 adds the output (Ilo-MIN) of the subtractor 272 to the output of the divider 282, and the adder 285 adds the output of the subtracter 272 to the output of the divider 283.

Furthermore, the divider 286 outputs the output (MAX-m
t) is set to 174, and the divider 287 is set to 3/4. The adder 288 adds the output of the subtracter 274 to the output of the divider 286 (
mz-MIN), and the adder 289 adds the divider 287
The output of the subtracter 274 is added to the output of the subtracter 274.

The selection circuit 290 follows the index 10 and the divider 27
6.277 and adders 280, 281, 284.285
, 288, 289. Specifically, the output of the selection circuit 290 is r 1/4(mt-MI
N) J, r3/4 (mt-MIN) J, rl/4 (
m.

-mt)+(mt-MIN) J, r3/4(me-m
t) + (mt-old N) J, r 1/4 (mz-mo)
+(mo-MIN) J, r3/4(mz-mo)+(
me-MIN) J, [1/4 (MAX-vz) +
(mz-MIN) J and r 3/4 (MAX-m
z) + (+112-MIN) J.

This output is applied to selection circuit 224 (FIG. 10).

As explained above, in this embodiment, an appropriate operation mode is selected according to the level distribution of each sample value in a divided block, and a digital television signal is encoded and transmitted based on the operation mode. By doing so,
Even a small amount of information can be encoded and transmitted in a state with little deterioration in image quality, etc., and it is also possible to reliably determine in which operation mode the transmitted data string was transmitted, and to check the original signal. can be restored.

In addition, in this embodiment, the index ID, MIN, MA
The configuration was configured to send out X, mo, m, mz, but MIN,
Instead of MAX, one of them and the dynamic range DR may be sent. Also, the number of average values is m
It is not limited to the three types o+ff1l+mt. “0+
ffl++ll1z may be determined based on a histogram of sample values within the block.

〔Effect of the invention〕

As can be easily understood from the above explanation, according to the present invention, encoding is performed taking into consideration not only the dynamic range but also the statistical distribution of pixels within the block, so even if the block includes a boundary, the encoding No distortion occurs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an encoding device as an embodiment of the present invention, FIG. 2 is a detailed diagram of the encoder 36 in FIG. 1,
3, 4 and 5 are detailed views of the encoder 56, 58, 60 of FIG. 2, FIG. 6 is a detailed view of the encoder 34 of FIG. 1, and FIG. 34 output code strings, FIG. 8 is an example of coding division in this embodiment, and FIG.
The figure shows an example of the configuration of a decoding device, and FIG. 10 shows the decoder 2 in FIG.
08, FIG. 11, FIG. 12, and FIG. 13 are detailed examples of the decoders 220, 221, and 222 of FIG. 10, respectively. 14.--Minimum value detector 16.--Maximum value detector 1
8--Block average value detector 34.36-Encoder 38--Comparator 42, 44-Selection circuit
48.50-・Average value detector patent applicant Canon Co., Ltd. 2-ζ Representative patent attorney Tsuneo Naka "Pa□' 11-,. ゛・Kuyuni 11, drawing of drawing (no change in content) Figure 1 Figure 3 Figure 4 Figure 5 Figure 9 To 210 Figure 10 Figure 11 Figure 12 Figure 13 Procedure Nefu Seisho (Method) January 22, 1988

Claims (1)

[Claims] blocking means for dividing digital image data into blocks each consisting of a predetermined number of samples; first data forming means for forming at least two reference values regarding dynamic range for each block; a second data forming means for forming distribution status data; a first encoding mode for coding samples within a block based on two reference values of the first data forming means; and two reference values of the first data forming means; and a second encoding mode for encoding the samples within the block based on the distribution status data of the second data forming means, and each sample is encoded by either of the two encoding modes depending on the dynamic range of each block. and encoding means for converting into encoded data to form encoded data; in the first encoding mode, two reference values and the encoded data of each sample by the first data forming means are used as a transmission unit, and in the second encoding mode, the first data An image information transmitting apparatus comprising: a transmission data forming means for forming a transmission data string using two reference values, distribution status data, and encoded data of each sample as transmission units.