JPH01140812A - Signal demodulation system - Google Patents

Abstract

PURPOSE:To improve the precision of signal demodulation by decoding the decision of a bit interval in minimum bit data through the use of a programmable logic device or a ROM. CONSTITUTION:When the minimum bit interval of data is set to To, a signal which has been MFM modulated is constituted by three kinds of bit intervals of To, 1.5To and 2To. A high frequency clock which is several- ten times as much as the minimum bit interval is inputted to a high frequency clock input 13 and is counted in counters 9 and 11. Furthermore, the counted value is decoded by using the programmable logic device 10 or the ROM. As a result, the demodulation output signal appears in the output terminal 7 of FF6 and a demodulation clock in the output terminal 12 of FF15.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention converts an encoded pulse time series signal into an original pulse time series signal from a pulse signal converted according to a certain rule (MFM modulation, FM modulation). This relates to a signal demodulation method for demodulating.

[Conventional technology]

FIG. 5 shows a conventional MFM (Modified Frequen
2 is a block diagram of a signal demodulation circuit that implements a signal demodulation method for demodulating a cy Modu-1ation signal; in the figure, 28 is a data input terminal; 29 is a time constant of 1.2;
5TO one-shot multi-buy break, 30.31
is a one-shot multipipe rake with a time constant of 0.5TO, 32.41 is a delay line with a delay time of 0.5TO, 33°3
4.35.36, 39.45 are AND circuits,
37, 40, 42, 46 are OR circuits, 38 is T
type flip-flop, 43 is a NOR (N0R) circuit, 44
47 is a high frequency oscillator, 48 is a D flip-flop, 49 is a demodulated clock output terminal, and 50 is a demodulated data output terminal.

FIG. 6 is a signal waveform diagram of each part of FIG. 5.

Next, the operation will be explained. The modulation signal a input to the data input terminal 28 is the one-shot multi-by-break 2
9, 30, and 31 to become -1 delayed pulse signals S, c, and d. On the other hand, the modulated signal a enters the AND circuit 34 with the delayed pulse signal C, and the output voltage is 1.5 T.

A signal e is obtained by removing the interval pulses. Further, the modulated signal a enters the AND circuit 33 with the delayed pulse signal d, and the 2
A signal f is obtained by extracting the To interval pulses. The output signal of the T-type flip-flop 38 is inverted every time a pulse is input to the input. 2T.

When there is no interval modulation signal f, the output of the AND circuit 36 becomes a low level, and the signal e passes through the OR circuit 37 and becomes the signal g, which alternately inverts the output polarity of the T-type flip-flop 38. When the signal f is low, the signal f, which is the Q output of the T-type flip-flop 38, goes high (H
(high) level, a high-level pulse is applied to the output of the AND circuit 36, passes through the OR circuit 37, and becomes T.
This becomes an input pulse to the T-type flip-flop 38, and the output signal of the T-type flip-flop 38 changes to a low level. At this time, if it is assumed that the output of the T-type flip-flop 38 is at a low level, the output of the AND circuit 36 will be at a low level, and no pulse will appear in the output of the T-type flip-flop 38. The signal remains at low level. In this way, the first discrimination signal, which is the output signal of the T-type flip-flop 38, is the signal e
Although the polarity is alternately inverted, the polarity when the signal f is generated is always at a low level. Modulated signal a passes through delay line 32 and becomes signal 1 in FIG. 0.5T of modulation signal a,
The delayed signal i enters the first discrimination signal and the AND circuit 35,
AND circuit 3 only when the first discrimination signal is at a high level.
The output appears at 5.

On the other hand, the modulation signal a enters the AND circuit 39 with the 100 output signal of the T-type flip-flop 3 which is the polarity inversion signal of the first judgment multiplier, and only when the first judgment multiplier is at a low level, the AND circuit The output appears at 39. AND circuits 35 and 39
The output of is input to the OR circuit 40, and the first
When the discrimination signal is at a high level, a first pseudo clock signal j is obtained, which is a signal replaced with a modulation signal delayed by 0 and s'ro. The first pseudo clock signal j enters the delay line 41 and becomes a second pseudo clock signal which is a 0.5T (1 delay signal) of the first pseudo clock signal j. The signals j and k are
The signals are added by an OR circuit 42 and become a signal l.

On the other hand, the counter 44 counts N output pulses of the high-frequency oscillator 47, and is inputted to the reset terminal R via the OR circuit 43, forming a free-running oscillator with an oscillation period of N pinto. On the other hand, the aforementioned signal I is input to the NOR circuit 43, and the counter 44 is reset by the output signal m of the NOR circuit 43. Therefore, N of the counter 44
A pulse signal n is obtained at the bit output terminal. This signal n and the second pseudo clock signal are added by an OR circuit 46 to become a demodulated clock 0, which is outputted from an output terminal 49 and inputted to the clock of a D-type flip-flop 48. A modulation signal i delayed by 0.5TO with respect to the modulation signal a described above is input to the D input terminal of the D-type flip-flop 48.
The modulated data P is obtained at the output point Q of 8, and the output terminal 5
Output from 0.

[Problem that the invention seeks to solve]

Since the conventional signal demodulation method is implemented as described above, there are problems in that there are many one-shot multi-byte breaks, many delay lines, and a large number of parts. Furthermore, since the time constants of these components are determined in an analog manner using CR or the like, there is a problem in that they are greatly influenced by surrounding conditions such as temperature and humidity.

This invention was made to solve the above-mentioned problems, and it improves signal demodulation accuracy by processing everything digitally without using any analog operating parts such as one-shot multi-by-break or delay lines. The purpose of this invention is to obtain a signal demodulation method that can be performed more accurately.

[Means for solving problems]

The signal demodulation method according to the present invention, when demodulating MFM modulation or FM modulated data, uses a counter and a programmable logic device (hereinafter referred to as , PLO) or read-only memory (hereinafter referred to as ROM), and demodulation is performed purely digitally.

[Effect]

The data bit interval in this invention is determined by counting using a high frequency clock several tens of times the minimum bit interval.
This is done by decoding the counter value in PLO or ROM.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is an input terminal for MFM modulated data;
2.4 is an edge detection circuit, 3 is a J-type flip-flop, 5 is a negative logic NOR circuit, 6.15 is a D-type flip-flop, 7 is a demodulated data output terminal, 8 is an AND circuit, and 13 is a High frequency clock input terminal for counter operation, 9
, 11 is a counter, 10 is a PLD, 12 is a demodulated clock output terminal, and 14 is a reference clock input terminal for sending out the demodulated clock.

FIG. 2 shows waveforms of various parts of FIG. 1.

Next, the operation will be explained. The edges of the MFM modulated data A inputted from the input terminal 1 are detected by the edge detection circuit 2 and become the signal B. Signal B is input to the reset R terminal of counter 9. Counter 9 is input terminal 1
It operates with a high frequency clock for counter operation which is manually input from 3. The output of counter 9 is input to PLDIO. M
The FM modulated signal has a minimum bit spacing of data of To
In this case, there are only three combinations of bit intervals: T, 1.5 T, and 2T. Also, MFM
Modulation methods are generally used for recording on magnetic disks, magnetic tapes, etc., but the reproduced data includes time fluctuations such as jitter.

Therefore, in the present invention, in order to reliably detect three types of signals: TO, 1, 5T, and 2T, To is detected when the value of the counter 9 is between 0.5T and 1.25T. 1,
5 To is detected when the value of counter 9 is 1.25T, ~1
．． During 75T0, 2To is detected when the value of counter 9 is 1.
If a signal appears at 75T0 or higher, it is determined that it is the respective signal. The output of PLDIO is 1.75TO signal C21, 25To signal D, 0,5T in Fig. 2.
There are four types of signals: 0 signal E, (0,5T, +1.75TO") signal J. The signal is the load L of the counter 11.
input to the terminal. When the counter 11 receives a signal, it counts from 221 to 255, and then stops. The output F of the CO terminal of the counter 11 becomes high level only when the counter 11 is in the counting state. This signal F is input to the input terminal J of the J-type flip-flop 3. The output C of PLDIO is input to the reset terminal R of the J- type flip-flop 3. J-
In the flip-flop 3, the outputs Q and Q are inverted only when the signal F is at a high level and the signal B is input. J
-signals G and PL of the output page terminal of the type flip-flop 3
The output E of DIO is input to an AND circuit 8. The output M of the AND circuit is input to the D terminal of the D-type flip-flop 6. On the other hand, the Q terminal output of the J-type flip-flop 3 is input to the edge detection circuit 4 and becomes a signal H.

The signal H is input to the NOR circuit 5 together with the output J of PLDIO. The output of the NOR circuit 5 is input to the clock T terminal of the D-type flip-flop 6. The output N of the D-type flip-flop 6 is output from the demodulated signal output terminal 7.

On the other hand, the output of the NOR circuit 5 is connected to the D-type flip-flop 1.
The set S terminal of No. 5 is also manually operated. The D terminal of the D-type flip-flop 15 is always grounded. Further, the clock T terminal of the D-type flip-flop 15 is connected to the clock T terminal.

A reference clock for sending out a demodulated clock is manually inputted from the input terminal 14. Then, demodulated clock 0 is applied to demodulated clock output terminal 12 in synchronization with this demodulated clock sending reference clock.

In the above embodiment, the signals C, D, in FIGS. 1 and 2 are
PLDIO is used to generate E and J, but this
A ROM having an operation speed equivalent to that of an LD may also be used.

Further, in the above embodiment, the case of the MFM demodulation method has been described, but this method can also be applied to a demodulation method of an FM modulated signal. Application examples will be explained below.

FIG. 3 is a block diagram of an FM demodulation circuit implementing an FM demodulation method which is an application example of the present invention.
6 is an input terminal for FM modulated data, 17 is an edge detection circuit, 18, 20.27 is a counter, 19 is a PLD,
21 is a NAND circuit, 22 is a D-type flip-flop, 23
is a demodulated clock output terminal, 24 is a reference clock input terminal for sending out a demodulated clock, 25 is a demodulated data output terminal, and 26 is a demodulated clock output terminal.
is a high frequency clock input terminal for counter operation.

FIG. 4 shows waveforms at various parts in FIG. 3.

Next, the operation will be explained. An edge of the FM modulated signal A inputted from the input terminal 16 is detected by the edge detection circuit 17 and becomes a signal B, which is inputted to the reset R terminal of the counter 18 . The counter 18 is operated by a high frequency clock inputted from a high frequency clock input terminal 26 for counter operation, and its output is inputted to the PLD 19. PLD
19 is 0, 5T, and signals C and T based on the value of the counter 18.

Generates a signal. The T0 signal is input to the reset R terminal of the counter 27. The counter 27 is configured to count for a period of To when the T0 signal arrives, and then stop counting. Demodulated data E is taken out from the CO terminal of this counter 27. Also, PLD1
The T0 signal of 9 is also input to the load LOAD terminal of the counter 20. The counter 20 is counted by a high frequency clock input from a high frequency clock input terminal 26 for counter operation, is loaded with preset data by the T0 signal, and generates a signal F at the T0 period. 0 and 5T generated by this signal F and PLD19.

The signal C is input to the NAND circuit 21. The output of the NAND circuit 21 is input to the D terminal of the D-type flip-flop 22. A demodulated clock sending reference clock (2) is input to the 'r terminal of the D-type flip-flop 22, and a demodulated clock H is outputted to the demodulated clock output terminal 23 in synchronization with this reference clock I.

As described above, by applying the present invention, highly accurate demodulation can be performed in the FM demodulation circuit as well, since data intervals are digitally counted and determined.

〔Effect of the invention〕

As described above, according to the present invention, since the bit interval of data is determined using a counter and a PLD or ROM, a signal demodulation circuit with high signal demodulation accuracy (and a small number of parts) can be obtained. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an MFM signal demodulation circuit implementing a signal demodulation method according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, and FIG. 3 is another embodiment of the present invention. A block diagram showing the FM signal demodulation circuit shown in FIG.
FIG. 5 is a block diagram showing a conventional signal demodulation circuit, and FIG. 6 is a waveform diagram of each part in FIG. 1 is a data input terminal, 2 is an edge detection circuit, 3 is a J-type flip-flop, 4 is an edge detection circuit, 5 is a negative logic NOR circuit, 6 is a D-type flip-flop, 7 is a data output terminal, and 8 is an AND circuit, 9 is a counter, 10 is a PLD,
11 is a counter, 12 is a demodulated clock output terminal, 3 is a high frequency clock input terminal, 14 is a reference clock input terminal for sending out the demodulated clock, and 15 is a D-type flip-flop. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.゛! , 1-Applicant Mitsubishi Electric Corporation (2 others) 1゜Figure 6 ρ・

Claims (1)

[Claims] In a signal demodulation method that demodulates an encoded pulse time series signal from MFM modulation or FM modulated data, when the minimum bit inversion interval of the data is T_0, T_0, 1.5T_0 , 2T_
In order to determine the data interval of 0, the data interval is counted by a counter using a clock whose frequency is several tens of times the frequency of the T_0, and the output of the counter is processed using a programmable logic device or a read-only memory. A signal demodulation method characterized in that the data interval is determined by decoding the pulse time-series signal, and the pulse time-series signal is digitally demodulated.