JPH01139437U - - Google Patents
Info
- Publication number
- JPH01139437U JPH01139437U JP1988036218U JP3621888U JPH01139437U JP H01139437 U JPH01139437 U JP H01139437U JP 1988036218 U JP1988036218 U JP 1988036218U JP 3621888 U JP3621888 U JP 3621888U JP H01139437 U JPH01139437 U JP H01139437U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- corner
- power line
- lsi
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988036218U JPH01139437U (US20030199744A1-20031023-C00003.png) | 1988-03-18 | 1988-03-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988036218U JPH01139437U (US20030199744A1-20031023-C00003.png) | 1988-03-18 | 1988-03-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01139437U true JPH01139437U (US20030199744A1-20031023-C00003.png) | 1989-09-22 |
Family
ID=31262834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988036218U Pending JPH01139437U (US20030199744A1-20031023-C00003.png) | 1988-03-18 | 1988-03-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01139437U (US20030199744A1-20031023-C00003.png) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59149033A (ja) * | 1983-02-16 | 1984-08-25 | Hitachi Ltd | 半導体集積回路装置 |
| JPS59193046A (ja) * | 1983-04-15 | 1984-11-01 | Hitachi Ltd | 半導体集積回路装置 |
| JPS60143647A (ja) * | 1983-09-09 | 1985-07-29 | フエアチアイルド カメラ アンド インストルメント コ−ポレ−シヨン | 回路のインダクタンスを減少させ且つ制御した電圧勾配を与える集積回路チツプ配線構成 |
| JPS63179560A (ja) * | 1987-01-21 | 1988-07-23 | Nec Ic Microcomput Syst Ltd | 集積回路記憶装置 |
-
1988
- 1988-03-18 JP JP1988036218U patent/JPH01139437U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59149033A (ja) * | 1983-02-16 | 1984-08-25 | Hitachi Ltd | 半導体集積回路装置 |
| JPS59193046A (ja) * | 1983-04-15 | 1984-11-01 | Hitachi Ltd | 半導体集積回路装置 |
| JPS60143647A (ja) * | 1983-09-09 | 1985-07-29 | フエアチアイルド カメラ アンド インストルメント コ−ポレ−シヨン | 回路のインダクタンスを減少させ且つ制御した電圧勾配を与える集積回路チツプ配線構成 |
| JPS63179560A (ja) * | 1987-01-21 | 1988-07-23 | Nec Ic Microcomput Syst Ltd | 集積回路記憶装置 |
