JPH01137814A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To decrease a through-current between power supplies flowing at switching by employing a P-channel transistor(TR) and an N-channel TR for a part connecting to an output of a comparator. CONSTITUTION:Each gate of the P-channel TR 6 and the N-channel TR 7 is connected to an output of a high potential comparator 4 and an output of a low potential comparator 5. Since the output of the inverter comprising the P-channel TR 6 and the N-channel TR 7 changes from a low level (or high level) to a high level (or low level) via a high impedance state where both the P-channel TR 6 and the N-channel TR 7 are turned off, even when the inverter 8 driven by the output employs CMOS structure, both the P-channel and the N-channel TRs connected in series between power supplies are not turned on. Thus, no large through-current is caused in the inverter 8. Furthermore, since the output change in the inverter 8 is steep, no through-current is caused in an inverter 10.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an oscillation circuit.

[Conventional technology]

Conventionally, this type of oscillation circuit has generally been the circuit shown in FIG. Group L formed by reference resistors 1 to 3 (
Conventionally, in order to control the signal commonly input to the two comparators 1.5 so that negative feedback is applied by the combination of the output signal of the high potential side comparator 4 receiving the fi lightning voltage and the output signal of the low potential side comparator 5, the third R-S consists of NAND gates 16 and 17 including inverter 18 as shown in the figure.
While outputting to the output terminal 14 via the inverter 10 using a flip-flop, the N-channel transistor 11 was driven to control discharging of the charging/discharging capacitor 13 charged by the charging resistor 12.

[Problem that the invention seeks to solve]

In the conventional oscillation circuit described above, points A and B shown in FIG.
At the point, the inverter 18 in Fig. 3 and the two-man NAND
Since gates 16 and 17 are made with 0MO3 configuration,
These have the disadvantage that a through current flows between the power supplies during switching. In addition, in order to suppress this through current, if the drive capacity of the two comparators 4 and 5 is increased and the switching time is shortened, then the comparators 4 and 5
The disadvantage is that the current flowing inside increases.

[Means for solving problems]

According to the present invention, the second reference potential generating means generates the first reference potential, the second reference potential generating means generates the second reference potential lower than the first reference potential, and the fixed potential an output means connected between the output means, which compares the first reference potential and the second reference potential with a control potential, and when the control potential is higher than the first reference potential, the output means is provided with a control potential; A first output signal is output to the output side connection point of the output means, and when the control potential is lower than the first reference potential and higher than the second reference potential, the control potential is between the fixed potentials of the output means or the fixed potential. and the output side connection point, and the output side connection point is in a high impedance state, and when the control potential is lower than the second reference potential, a second voltage is applied to the output side connection point. a comparison means for outputting an output signal, a latch means connected to the output side connection point, an output terminal for outputting a predetermined signal in accordance with the output of the latch means, and a first output signal output from the latch circuit. The control signal is set to a value lower than the second reference potential in response to an output signal of the latch circuit, and the control signal is set to a value higher than the first reference potential in response to the second output signal output from the latch circuit. An oscillation circuit having a control means is obtained.

[Actual travel example]

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Reference resistors 1 to 3 create a reference potential for RA and R11 in FIG. 4. 4 and 5 are comparators with V.

The determination is made by comparing the potential of RA or RB with the potential of RA or RB. 6 is P
7 is an Nch transistor, the gates of which are connected to the outputs of the high-potential side comparator 4 and the low-potential side comparator 5, respectively. 8-1
0 is an inverter circuit, and the inverter circuit 9 is fed back between the input and output of the inverter circuit 8 to form a data latch circuit. Reference numeral 11 denotes an N-channel transistor, which performs switching operation (on/off operation) based on the output of the inverter circuit 1°. Reference numerals 12 and 13 are a charging resistor and a charging/discharging capacitor, respectively, which are charged and discharged by the on/off operation of the N-channel transistor 11 to change the potential of vc.

The process from area C to area d in FIG. 4 will be explained following the operation of each part. In the C region, the high potential side comparator 4,
The low potential side comparators 5 are both [High
Due to the output of
2 is also "low". Therefore, the N-channel transistor 11 is in an off state and the voltage is V. The potential increases with a time constant determined by the charging resistor 12 and the charging/discharging capacitor I3. Next, in region b, the high potential side comparator 4 is “high”
, since the low potential side comparator 6 outputs "low", the P channel transistor 6 and the N channel transistor 7
Both are in the off state, but since the latch circuit using inverter 9 is connected to vl, the v1 potential is "low"
The potential v2 of the output terminal 14 also remains at low J.

In the C region, the output of the high potential side comparator 4 changes to "low", so the P channel transistor 6 is turned on, and V
1 potential rises to "high" and the potential v2 of the output terminal 14 also becomes "high", so the N-channel transistor 11 is turned on and the potential V2 rises to "high". The potential is drawn toward the GND side. Furthermore, in the d region, the same operation as in the b region is performed and the P channel transistor 6 and the N channel transistor 7 are turned off, but the latch circuit j■1 using the inverter 9
The potentials of vl and V2 are “high” because they are connected to
As it is, the N-channel transistor 11 continues to be turned on, and the state returns to region a, and the above-mentioned cycle is repeated to perform oscillation. In this way, P channel transistor 6
, N-channel transistor 7 are both turned off in the transition state, so that a through current can be prevented from flowing.

In this way, the inverter composed of the P-channel transistor 6 and the N-channel transistor 7 changes the output from the low level (or high level) to both transistors 6.7.
Both change to a high level (or low level) through a high impedance state in which they are off, so even if the inverter 8 driven by the output is a CMO8TJ structure, it is a P channel and an N channel that are connected in series between the power supplies. Both transistors never turn on.

Therefore, a large through current does not occur in the inverter 8. Since the output change of the inverter 8 is steep, a through current also occurs in the inverter 10.A Schmitt circuit 15 is used in place of the inverter circuit 8 used in the embodiment described above. In this embodiment, by using the Schmitt circuit 15, the P-channel transistor 6 and the N-channel transistor 7 rise, and when the fall is slow,
It has the advantage that stable oscillation operation is performed, while the through current is further reduced.

〔Effect of the invention〕

As described above, the present invention has the advantage that by using a P-channel transistor and an N-channel transistor in the portion connected to the output of the humparator, the power supply through-current flowing during switching can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, FIG. 3 is a conventional circuit diagram, and FIG. 4 is a V. FIG. 1 to 3...Reference resistance, 4...
High potential side comparator, 5...Low potential side comparator, 6...P channel transistor, 7
...N-channel transistor, 8 to 10...
... Inverter circuit, 11 ... N-channel transistor, 12 ... Charging resistor, 13.
...Charge/discharge capacitor, 14...Output terminal, 15...Schmitt circuit, 16.17.
...Two-man power NAND gate, 18...Inverter circuit. Agent Patent Attorney Susumu Uchihara VDD VDD 4-11 Takaden I Tachishin I Koshipa I, -2 5.
--- Ishihar Taro bribe 71-N + Manertrayun 7. Ri/Z -- Numi 1 Jin 1 H4 Mr. Sta 13 -- One charge scissor electric 14- Output nishikiyo j ~ 3 --- Sofa and Sis Gourd 4th 4, - Takaoki I Stand Ai Giant 11 Koshibareta 5 .2 Mr. Den & Associate Koshiharu Tawo, -1o, -Elevator C75 & yy-N channel transistor 12- Charging capacitor 13- Charging/discharging capacitor 14- Output terminal f5- Shu ξ, Toro drop 1 to 3-. -Reference bz nail pile 411. Takadensa's Koshibarator 71-tq-5-Missing O/I/U Runshizuta IZ--Charging J Saimaru 13-Charging and discharging capacitor 14-Output terminal f, /'7-2 Manual NAND game Each part 18 and in part 18

Claims (1)

[Claims] a first reference potential generating means for generating a first reference potential;
a second reference potential generating means for generating a second reference potential lower than the first reference potential; and an output means connected between the fixed potential, the first reference potential and the second reference potential being connected to each other. The potential and the control potential are compared, and when the control potential is higher than the first reference potential, a first output signal is output to an output side connection point provided in the output means, and the control potential is higher than the first reference potential. When the potential is lower than the reference potential and higher than the second reference potential, the output connection point is set to high impedance without flowing a current between the fixed potential of the output means or between the fixed potential and the output connection point. and when the control potential is lower than the second reference potential, a comparison means outputting a second output signal to the output connection point; a latch means connected to the output connection point; an output terminal that outputs a predetermined signal according to the latch means; and an output terminal that sets the control signal to a value lower than the second reference according to the first output signal output from the latch circuit, and outputs the control signal from the latch circuit. and control means for setting the control signal to a value higher than the first reference potential in accordance with the second output signal.