JPH0113678B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-frequency signal receiver suitable for fabrication into a digital/analog mixed large-scale integrated circuit (LSI) using a MOS process.

FIG. 1 is a block diagram showing the circuit configuration of a conventionally used receiver for multi-frequency signals such as push-button dial signals, and FIG. 2 is an operational waveform diagram of each part of FIG. 1. In Figure 1, IN is an input terminal, 1 is an amplifier that amplifies a multi-frequency signal, and 2 is an amplifier that amplifies a multi-frequency signal.
3 is a high frequency canceler that extracts a low group frequency signal from a multifrequency signal, 3 is a low frequency canceler that extracts a high group frequency signal from a multifrequency signal, and 4 and 4' are constant filters for a sinusoidal multifrequency signal. This is a limiter circuit that shapes the waveform into a square wave with amplitude. Reference numeral 5 denotes a detection circuit group, which includes frequency signal detection circuits (hereinafter simply referred to as detection circuits) 51 to 58 each consisting of a bandpass wave device, a detector, and a pulse conversion circuit.
When each single frequency signal is detected from the multifrequency signal converted into a square wave by the limiter circuits 4 and 4', a "1" level detection signal is output. 6 is a holding logic circuit equipped with a timer circuit 7, 601 to 625 are NAND gates, 626 and 627 are 4-input OR gates, and 628 is an AND gate. The outputs of the detection circuits 51 to 58 are applied to one input terminal of the NAND gates 601 to 608, respectively, and a signal obtained by inverting the output signal of the timer circuit 7 by the NAND gate 625 is applied to the other input terminal of the common signal line 629. NAND gates 609 to 616
The above NAND gate 601 is connected to one input terminal of
The outputs of NAND gates 617 to 608 are applied to the other input terminals, and the outputs of NAND gates 617 to 624 are fed back and applied to the other input terminal.
The outputs of the NAND gates 609-616 are applied to one input terminal of the NAND gates 617-624, respectively, and the output of the timer circuit 7 is applied to the other input terminal via a common signal line 630. The outputs of NAND gates 609 to 612 are input to each input terminal of the 4-input OR gate 626, and the outputs of NAND gates 613 to 616 are input to each input terminal of the 4-input OR gate 627, and their outputs are ANDed. gate 62
8 and a 4-input AND gate 77, which will be described later, to the timer circuit 7. L1~L4, H1
~H4 is an output terminal for each frequency signal, and is held at the "1" level when there is no signal. The timer circuit 7 includes a recovery monitoring timer 71, a minimum input signal duration monitoring timer 72, an output time setting timer 73, a flip-flop 74, NAND gates 75 and 76, and a 4-input AND gate 77. The output of the AND gate 628 is inverted by the NAND gate 75 and is input to the recovery monitoring timer 71.
The output held for a certain period of time from the end of the output signal of the AND gate 628 is input to the R terminal of the flip-flop 74 to prevent the multi-frequency signal receiver from immediately recovering when the input signal is interrupted or impulsive noise is superimposed. Then, the multi-frequency signal receiver is restored after a restoration time tp after the output signal from the AND gate 628 disappears. The minimum input signal duration monitoring timer 72 monitors the minimum duration tg of a regular signal, and its output is normally at the "1" level.
After a time tg after receiving the output signal from the AND gate 628, the output is set to the "0" level, and at the same time as the output signal from the AND gate 628 ends, the output returns to the "1" level. The flip-flop 74 inputs the output of the recovery monitoring timer 71 to the R terminal and the output of the minimum input signal duration monitoring timer 72 to the S terminal, and inputs the output of the minimum input signal duration monitoring timer 72 from the output terminal "0".
When the output signal of the recovery monitoring timer 71 falls, it changes from "1" level to "0" level, and when the output signal of recovery monitoring timer 71 falls, it changes from "0" level to "1" again.
A signal that is inverted to the level is output to the NAND gate 76, and a signal that is inverted from the signal from the output terminal ``0'' is output from the output terminal ``1'' to the 4-input AND
Output to gate 77. The NAND gate 76 inverts the signal from the output terminal "O" of the flip-flop 74 and inputs it to the output time setting timer 73. The output time setting timer 73 sets an output duration time to with a constant time width after the minimum input signal duration time tg. The 4-input AND gate 77 is configured to logically AND the output signals from the output time setting timer 73, the 4-input OR gates 626, 627, and the output terminal "1" of the flip-flop 74, and outputs the result to the common signal line 630.

Next, the operation will be described with reference to FIG. The multi-frequency signal ○a input to the input terminal IN is appropriately amplified by the amplifier 1, separated into a low group frequency signal and a high group frequency signal by the high frequency canceler 2 and the low frequency canceler 3, and further The limiter circuits 4 and 4' each shape the waveform into a square wave with a constant amplitude. Each frequency component of the multi-frequency signal whose waveform has been shaped by the limiter circuits 4 and 4' is detected by each of the detection circuits 51 to 58 of the detection circuit group 5. The detection circuits 51 to 58 output a "1" level when detecting a corresponding frequency signal. The output of the timer circuit 7 is initially at the "0" level, and therefore a "1" level signal is applied to the common signal line 629. NAND gate 6
Among the circuits 01 to 608, those which receive the output of the "1" level from the detection circuits 51 to 58 have two inputs of the "1" level and output the "0" level. Furthermore, among NAND gates 609 to 616
Those receiving the "0" level output from the NAND gates 601 to 608 output "1" level.
The outputs of NAND gates 609 to 612 and NAND gates 613 to 616 are logically summed by 4-input OR gates 626 and 627, and further 4
The outputs of the input OR gates 626 and 627 are logically ANDed by an AND gate 628 to check for the simultaneous presence of detection signals in both the low group and the high group, and output a signal ○. The above signal ○B is inputted to the recovery monitoring timer 71 via the NAND gate 75, and inputted as it is to the minimum input signal duration timer 72, the recovery monitoring timer 71 receives the signal ○C, and the minimum input signal duration timer 72 receives the signal ◯ and d are respectively input to the flip-flop 74. The output of the "O" terminal of the flip-flop 74 is inverted by the NAND gate 76 and inputted to the output time setting timer 73, which inputs the signal ○ho to the 4-input AND gate 77. The 4-input AND gate 77 takes the logical sum of the signal ○H, the output of the "1" terminal of the flip-flop 74, and the outputs of the 4-input OR gates 626 and 627, and outputs the signal ○. The signal ○ is connected to NAND gates 617 to 62 via a common signal line 630.
4 and the NAND gate 625, and during the period when the signal ○ is at the “1” level, the NAND gates 617 to 625
624, the other input is at “1” level,
In other words, the gate where the frequency signal is detected outputs the "0" level detection signal to the output terminals L1 to L4,
Output to H1 to H4. At the same time, the detection signal
The outputs of the NAND gates 609 to 616 can be maintained at the "1" level even when the input signal ○a is returned to the NAND gates 609 to 616 and the output of the detection circuit group 5 is restored to the "0" level. Also
The inverted signal to the signal ○ applied to the NAND gates 601 to 608 via the NAND gate 625 and the common signal line 629 will remain in the NAND gate 601 even if the detection circuit group 5 malfunctions due to a pseudo signal such as audio.
- Prevent the output of 608 from changing. When the signal ○ is completed, the NAND gates 601 to 608 are restored, and the recovery monitoring timer 71 enters a recovery operation, and the flip-flop 74 is returned to the initial reception standby state at the end of the signal ○.

The multi-frequency signal receiver described above is equipped with a limiter circuit 4, to prevent it from malfunctioning due to pseudo signals such as voices.
4' and a minimum input signal duration monitoring timer 72 are provided, and the limiter circuits 4 and 4' prevent other frequency components from being included at the same time even if there are two frequency components belonging to the high group and the low group in the pseudo signal. Therefore, the normal frequency component signal is weakened by the capture effect, and the detection circuit group 5 does not operate. Further, by limiting the reception frequency bandwidth and detection threshold of the bandpass waveform generator and detector that constitute the detection circuit group 5, malfunctions due to pseudo signals are prevented.

In this way, the conventional multi-frequency signal receiver operates after recognizing the regular input signal as valid, but it has three timers in its timer circuit, and the timer is a digital integrated circuit. The disadvantage is that the area occupied by the circuit is large, and the circuit as a whole becomes large.

In view of the above drawbacks of the conventional multi-frequency signal receiver, the present invention minimizes the area occupied by a timer circuit in a digital integrated circuit, and provides a multi-frequency signal receiver suitable for digital/analog mixed large-scale integrated circuit (LSI) using a MOS process. The purpose of the present invention is to provide a signal receiver that sequentially counts the minimum input signal duration time, output duration time, and recovery time, and outputs a signal representing each timing.
A counter that is reset when a reset signal is input, a controllable input polarity inversion circuit that inverts the polarity of an input signal and outputs an inverted input signal, and a timing signal that represents at least the above-mentioned minimum input signal duration is input. A controllable first gate circuit that performs a predetermined logical operation and outputs a first output signal, and at least a timing signal representing the recovery time are inputted,
a controllable second gate circuit that performs a predetermined logical operation and outputs a second output signal; at least a timing signal representing the output duration time; an inverted input signal; a first output signal; and a second output. A third gate circuit receives a signal, performs a predetermined logical operation, and outputs the reset signal; and a third gate circuit receives at least the input signal, performs a predetermined logical operation, and outputs the reset signal. a controllable fourth gate circuit that outputs a signal;
The output signal, the second output signal, and the third output signal are input, and a fourth output signal and A first temporary storage circuit that outputs a fifth output signal, and at least the second output signal, the fifth output signal, and a timing signal representing an output duration time are input, and performs a predetermined logical operation. a second temporary memory for outputting a sixth output signal for controlling the input polarity inversion circuit and the second gate circuit, and a seventh output signal for controlling the fourth gate circuit; a fifth gate circuit to which at least the fifth output signal and the seventh output signal are input, and which performs a predetermined logical operation and outputs a desired control signal;
Only when the input signal continues to be detected until the minimum input signal duration time elapses from the point of time when the input signal is detected, the first temporary storage circuit is set and the "1" level control is performed during the output duration time. A signal is output, and after the output duration time has elapsed, the second temporary storage circuit is set, and the input polarity inversion circuit is controlled by the sixth output signal, and if there is no input signal during the recovery time, the above A multi-frequency signal receiver is provided, comprising a timer circuit configured to reset the first and second temporary storage circuits in response to a timing signal from a counter. The drawings will be described in detail below.

Fig. 3 is a block diagram of an embodiment of the timer circuit in the multi-frequency signal receiver of the present invention, Fig. 4 is a detailed configuration diagram thereof, and Fig. 5 is a waveform diagram of each part of Figs. 3 and 4. shows. In FIGS. 3 and 4, 81 is a counter, 82 is an input polarity inversion circuit,
83, 84, 85, 86 and 87 are the 4th, 3rd,
The second, first and fifth gate circuits (hereinafter simply referred to as gate circuits), 88 and 89 are the first and second gate circuits.
This is a temporary storage circuit (hereinafter simply referred to as a temporary storage circuit). Note that other circuits not shown are the same as those in the conventional example. The counter 81 divides the frequency of a clock pulse from an oscillator (not shown) and is reset by a signal from a gate circuit 84, and has a recovery time tp, a minimum input signal duration tg, and an output duration time.
Outputs to timing signals sequentially. The input polarity inversion circuit 82 has a 1 negative input NAND gate 82a,
82b and a NAND gate 82c, and the NAND gate 6 in the circuit diagram of FIG.
The output signals ○ and 28 and the inverted output of the temporary storage circuit 89 are respectively input, and the other input terminals are respectively input with outputs opposite to the above, and the outputs of the 1 negative input NAND gates 82a and 82b are as follows.
The logical product is negated by the NAND gate 82c and inputted to the gate circuit 84. The gate circuit 83 is 1
It consists of a negative input NAND gate, and its negative input terminal receives the output signal ○○ of the AND gate 628,
In addition, the outputs of the temporary memory circuits 89 are respectively applied to the other input terminals, and the outputs of the temporary memory circuits 89
8 is input. Gate circuit 84 has 4 inputs
Consisting of a NAND gate, an input polarity inversion circuit 82,
The logical product of the outputs of the gate circuits 85 and 86 and the timing signal of the output duration to from the counter 81 is negated and inputted to the reset terminal of the counter 81. The gate circuit 85 consists of a NAND gate,
The logical product of the inverted output of the temporary storage circuit 89 and the timing signal of the recovery time tp of the counter 81 is negated and input to the gate circuit 84 and the temporary storage circuits 88 and 89. The gate circuit 86 is composed of a NAND gate, performs a logical AND operation between the timing signal of the minimum input signal duration tg of the counter 81 and the inverted output of the temporary storage circuit 88, and inputs the result to the gate circuit 84 and the temporary storage circuit 88. The gate circuit 87
It consists of a NAND gate 87a and an inverter 87b, and performs the logical product of temporary storage circuits 88 and 89 and outputs the result. Temporary memory circuit 88 is NAND gate 8
8a and 1 negative input NAND gate 88b and
It consists of a flip-flop constituted by a NAND gate 88c, and performs an inverting operation based on the timing signal of the minimum input signal duration time tg input from the gate circuit 86 and the timing signal of the recovery time tp input from the gate circuit 85. Temporary memory circuit 89
is a flip-flop composed of a NAND gate 89a, a 1-input NAND gate 89b, and a NAND gate 89c, and receives a timing signal of output duration to input from the counter 81 and a timing signal of recovery time tp input from the gate circuit 85. The inversion operation is performed by

Next, the operation will be explained. First, assuming that the inverted output of the output ○I of the temporary storage circuit 89 is at the "0" level when the input signal ○A is in the reception standby state with no signal, the signal ○B is "0" like the input signal ○A. Therefore, the output of the input polarity inversion circuit 82 is at the "0" level, and the output of the input polarity inverting circuit 82 is at the "0" level.
The output of 4 becomes “1” level and counter 81
is maintained in a reset state, and each timing signal of the recovery time tp, minimum input signal duration tg, and output duration time to of the counter 81 is set to "0", respectively.
It is held at the "0" and "1" levels. Also, since the output ○l of the temporary storage circuit 89 is at the "1" level, the output ○chi of the gate circuit 83 is at the "0" level, and the outputs of the gate circuits 85 and 86 are also at the "1" level, so the temporary storage circuit The output ○nu of 88 is at "0" level, and its inverted output is at "1" level. The inverted output of the output ○nu holds the other input terminal of the gate circuit 86 at the "1" level, and the output ○nu holds one input terminal of the NAND gate 89a of the temporary storage circuit 89 at the "0" level. , Therefore, the output of the temporary memory circuit is “1” level, and its inverted output is “0”
level is maintained. Due to the above outputs ○nu and ○ru, the output ○of the gate circuit 87 becomes the "0" level. If the inverted output of the output ○ of the temporary memory circuit 89 is held at the "1" level when the power is turned on, the output ○ of the input polarity inversion circuit 82 becomes the "1" level, and The output of the gate circuit 84 goes to the "0" level, the reset of the counter 81 is released, and the counter 81 starts counting. When the count reaches the recovery time tp, the gate circuit 85
Both inputs of the gate circuit 84 become "1" level, and their output becomes "0" level, inverting the output of the gate circuit 84 to "1" level and resetting the counter 81, as well as temporarily storing circuits 88 and 89. The signal is reversed to restore the stable state when there is no signal.

Next, when the signal ○a shown in Fig. 5 is input,
The output ◯ of the AND gate 628 becomes the "1" level, and therefore the output ◯ of the input polarity inversion circuit 82 and the output ○ of the gate circuit 83 become the "1" level. Due to the output ◯ of the input polarity inverting circuit 82, the output ◯ of the gate circuit 84 becomes the “0” level, and the reset of the counter 81 is released. As a result, the counter 81 starts counting and first sets the timing signal of the recovery time tp to "1" level, but the gate circuit 81
Since the other input terminal of 5 is at the "0" level, its output does not change, and it is subsequently counted, and if the output ○○ is longer than the minimum input signal duration tg, the minimum input signal duration tg The timing signal of “1”
It is output to the gate circuit 86 as a level. Since the other input terminal of the gate circuit 86 is at the "1" level, the output of the gate circuit 86 changes to the "0" level, and this output inverts the output of the temporary storage circuit 88 to the "1" level. Moreover, the inverted output of the output ○/nu is also inverted to the "0" level, and the counter 81 is reset via the gate circuit 84. Furthermore, the output of the gate circuit 86 returns to the "1" level due to the inverted output of the output ○/nu of the temporary storage circuit 88. The output ○H of the gate circuit 87 is inverted to the "1" level as the output ○N of the temporary storage circuit 88 becomes the "1" level, and is output to the common signal line 630 in FIG.
Once the "1" level output ○ is output, the input signal ○a ends and even if the output of the detection circuit group 5 returns to the "0" level, the signal ○b maintains the "1" level and is input. Since the output of the polarity inversion circuit 82 maintains the "1" level, when the output of the gate circuit 86 returns to the "1" level, the output of the gate circuit 84 becomes the "0" level again and the counter 81 is reset. It is released and counting starts again.

Since one input terminal of the gate circuits 85 and 86 is at the "0" level, the counter 81 counts up to the output duration time to, and inverts the timing signal of the output duration time to to the "0" level. The counter 8
The output of 1 is sent to the counter 81 via the gate circuit 84.
At the same time, the output ○ of the temporary memory circuit 89 is inverted to the "0" level, and the output ○ of the gate circuit 87 is thereby inverted to the "0" level, and the output ○ of the gate circuit 87 is inverted to the "0" level. Only the width becomes a “1” level signal. Further, the output ○l of the "0" level holds the output ○chi of the gate circuit 83 at the "1" level, so that the temporary storage circuits 88 and 89 are not restored even when the signal ○ro ends. On the other hand, the inverted output of the output ○ of the temporary storage circuit 89 becomes "1" level, and this output is connected to one input terminal of the gate circuit 85 and the 1 negative input NAND gate 82a, 8 of the input polarity inversion circuit 82.
2b, and the output of the input polarity inversion circuit 82 is at the "0" level when the signal (○) is at the "1" level, and when the signal (○) is at the "0" level. Inverted to “1” level.
If the input signal ○a is long, the input polarity inversion circuit 82
The output of the gate circuit 84 maintains the "0" level, and the output of the gate circuit 84 also maintains the "1" level due to the signal O, and the counter 81 maintains the reset state.

When the input signal ○a ends, the signal ○b goes to "0" level, and the output ○g of the input polarity inversion circuit 82 goes to "1".
Flip to level. Gate circuit 8 is activated by the output
The output of No. 4 becomes "0" level, the reset of the counter 81 is canceled again, and counting starts. After counting the recovery time tp, the counter 81 inverts the timing signal to the "1" level and sends it to the gate circuit 8.
Output to 5. Since the other input terminal of the gate circuit 85 is at the "1" level, its output is at the "0" level, and this output causes the temporary storage circuits 88, 89
The outputs ○nu and ○ are restored to the "0" level and the "1" level, respectively. At the same time, the output of the gate circuit 85 inverts the output of the gate circuit 84 to the "1" level, resets the counter 81, and restores the initial signal waiting state.

As explained above, according to the present invention, the minimum input signal duration time, the output duration time, and the recovery time are sequentially counted, a signal representing each timing is outputted, and the counter is reset by inputting a reset signal. and a controllable input polarity inversion circuit that inverts the polarity of an input signal and outputs an inverted input signal, and a timing signal representing at least the minimum input signal duration time as input, and performs a predetermined logical operation. A controllable first gate circuit that outputs a first output signal and at least a timing signal representing the recovery time are input, and is controllable to perform a predetermined logical operation and output a second output signal. A second gate circuit is inputted with at least a timing signal representing the output duration time, an inverted input signal, a first output signal, and a second output signal, and performs a predetermined logical operation to output the reset signal. a third gate circuit that outputs a third gate circuit, and at least the above input signal is inputted;
A controllable fourth gate circuit that performs a predetermined logical operation and outputs a third output signal, and at least the first output signal, the second output signal, and the third output signal are inputted thereto. , a first temporary storage circuit that performs a predetermined logical operation, holds the state, and outputs a fourth output signal and a fifth output signal that control the first gate circuit; An output signal, a fifth output signal, and a timing signal representing the output duration time are inputted, and a predetermined logical operation is performed to maintain the state and control the input polarity inversion circuit and the second gate circuit. a second temporary storage circuit that outputs a sixth output signal to control the fourth gate circuit, and a seventh output signal to control the fourth gate circuit; and at least the fifth output signal and the seventh output signal are input. and a fifth gate circuit that performs a predetermined logical operation and outputs a desired control signal, and the input signal continues to be detected from the time of detection of the input signal until the minimum input signal duration time elapses. Only in this case, the first temporary memory circuit is set and a control signal of "1" level is output during the above output duration time, and after the output duration time has elapsed, the second temporary memory circuit is set and the above A timer configured to control the input polarity inversion circuit by the sixth output signal, and reset the first and second temporary storage circuits by the timing signal of the counter if there is no input signal during the recovery time. By providing this circuit, the timer circuit of a multi-frequency signal receiver, which conventionally required three timers: a minimum input signal duration timer, an output time setting timer, and a recovery time timer, can be reduced to a single counter and logic circuit group. MOS
It has the advantage of being able to provide a multi-frequency signal receiver suitable for digital/analog mixed large-scale integrated circuit (LSI) processing.

[Brief explanation of drawings]

The drawings serve to explain the present invention; FIG. 1 is a block diagram showing the circuit configuration of a conventional multi-frequency signal receiver, FIG. 2 is a waveform diagram of each part of FIG. 1, and FIGS. 3 to 5. 3 shows one embodiment of the present invention.
4 is a block diagram of a timer circuit of a multi-frequency signal receiver, FIG. 4 is a detailed configuration diagram of the timer circuit of FIG. 3, and FIG. 5 is a waveform diagram of each part of FIGS. 3 and 4. 81... Counter, 82... Input polarity inversion circuit, 83, 84, 85, 86, 87... Gate circuit, 88, 89... Temporary storage circuit.

Claims (1)

[Claims] 1. A counter that sequentially counts the minimum input signal duration time, output duration time, and recovery time, outputs a signal representing each timing, and is reset when a reset signal is input; a controllable input polarity inversion circuit that inverts the polarity of the input signal and outputs an inverted input signal; and a timing signal representing at least the above-mentioned minimum input signal duration time. a controllable first gate circuit that outputs a signal; and a controllable second gate circuit that receives at least the timing signal representing the recovery time and that performs a predetermined logical operation and outputs a second output signal. A gate circuit, to which at least a timing signal representing the output duration time, an inverted input signal, a first output signal, and a second output signal are input, and a gate circuit that performs a predetermined logical operation and outputs the reset signal. a controllable fourth gate circuit to which at least the input signal is input and which performs a predetermined logical operation and outputs a third output signal; at least the first output signal; A second output signal and a third output signal are inputted, and a fourth output signal and a fifth output that perform a predetermined logical operation and hold the state, and control the first gate circuit. A first temporary memory circuit that outputs a signal, at least the second output signal, the fifth output signal, and a timing signal representing an output duration time are inputted, and a predetermined logical operation is performed to determine the state thereof. a second temporary storage circuit that outputs a sixth output signal that holds and controls the input polarity inversion circuit and the second gate circuit, and a seventh output signal that controls the fourth gate circuit; a fifth gate circuit to which the fifth output signal and the seventh output signal are input, performs a predetermined logical operation and outputs a desired control signal, and from the time of detection of the input signal, Only when the input signal continues to be detected until the minimum input signal duration time elapses, the first temporary storage circuit is set, and a "1" level control signal is output during the output duration time, and the output signal is After the duration time has elapsed, the second temporary storage circuit is set, and the input polarity inversion circuit is controlled by the sixth output signal, and if there is no input signal during the recovery time, the timing signal of the counter is used to control the input polarity inversion circuit. A multi-frequency signal receiver comprising a timer circuit configured to reset the first and second temporary storage circuits.