JPH01135530U - - Google Patents

Info

Publication number
JPH01135530U
JPH01135530U JP3112888U JP3112888U JPH01135530U JP H01135530 U JPH01135530 U JP H01135530U JP 3112888 U JP3112888 U JP 3112888U JP 3112888 U JP3112888 U JP 3112888U JP H01135530 U JPH01135530 U JP H01135530U
Authority
JP
Japan
Prior art keywords
clock
flip
flops
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3112888U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3112888U priority Critical patent/JPH01135530U/ja
Publication of JPH01135530U publication Critical patent/JPH01135530U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP3112888U 1988-03-08 1988-03-08 Pending JPH01135530U (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3112888U JPH01135530U (enrdf_load_stackoverflow) 1988-03-08 1988-03-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3112888U JPH01135530U (enrdf_load_stackoverflow) 1988-03-08 1988-03-08

Publications (1)

Publication Number Publication Date
JPH01135530U true JPH01135530U (enrdf_load_stackoverflow) 1989-09-18

Family

ID=31256754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3112888U Pending JPH01135530U (enrdf_load_stackoverflow) 1988-03-08 1988-03-08

Country Status (1)

Country Link
JP (1) JPH01135530U (enrdf_load_stackoverflow)

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