JPH01135125A - Code converting circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit arrangement and the wiring area efficiently as the array structure with the circuit constitution by an LSI by constituting a compression conversion section and an expansion conversion section of a pulse code modulation PCM code by a program logic array PLA. CONSTITUTION:A circuit converting (compressing) a linear PCM code A into a nonlinear PCM code AA and a circuit converting (expanding) a nonlinear PCM code B into a linear PCM code BB are constituted by one program logic array PLA 2 and a selection signal SEL representing which circuit is to be used is utilized to apply the compression conversion and the expansion conversion by time division. Thus, the chip occupied area is less and the circuit by the LSI constitution is realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to code conversion between a linear PCM (pulse code modulation) code and a nonlinear PCM code, particularly a code using a PLA (program logic array). This relates to conversion circuits.

[Prior Art] Conventionally, this type of device includes, for example, the Japanese Patent Publication No. 60-742
As disclosed in Publication No. 0, a plurality of read-only memories (generally referred to as ROMs) are used as code converters for converting linear PCM codes into non-linear PCM codes, and the output from a first read-only memory circuit is Code conversion is realized by a method of selecting the outputs of the second and third read-only memories according to the values of the segment bits.

In general, PCM systems targeting audio frequencies employ nonlinear codes that perform fine quantization in small amplitude regions and coarse quantization in large amplitude regions. Also C, C.

1, T, T, (The International
Telegraph and Telegraph
one Con5ultative Comm1tte
e) recommends using a μ-law or A-law polyline companding code to convert this linear PCM code into a nonlinear PCM code.

In this way, the correspondence between the polygonal companding valve linear PCM code and the linear PCM code is mathematically accurately defined. For example, a theoretical description of this PCM code conversion is given in 5.4 Code Conversion Processing, page 140 of "Applications of Digital Signal Processing" edited and published by the Institute of Electronics and Communication Engineers on May 20, 1980. In particular, in the fold linear compression law, two laws are shown, one for the μ law and the other for the A law, and the correspondence between linear PCM codes and nonlinear PCM codes is explained in detail.

In this way, the compression conversion from a linear PCM code to a nonlinear PCM code and the expansion conversion from a nonlinear PCM code to a linear PCM code can be easily performed by digital signal processing.

However, in conventional code conversion circuits, read-only memories (ROMs) are used as circuit elements due to the trend toward shorter code conversion times and lower prices of semiconductor devices.

[Problems to be Solved by the Invention] However, with the above circuit configuration, it is necessary to configure separate conversion circuits for compression and decompression of PCM codes, and a large number of read-only memories are required for compression and decompression. (R
OM), the chip area would be too large to realize an LSI configuration circuit with this configuration, and it could not be technically adopted.

The present invention has been made to solve these problems, and an object of the present invention is to provide a conversion circuit that can be employed as an LSI configuration circuit and that can perform both compression and expansion conversion of PCM codes.

[Means for Solving the Problems] The present invention provides a circuit for converting (compressing) a linear PCM code into a nonlinear PCM code, and a circuit for converting (compressing) a linear PCM code into a nonlinear PCM code in mutual conversion between a linear PCM code and a nonlinear PCM code. A circuit for converting (decompressing) into a code is configured with one program logic array (hereinafter abbreviated as PLA),
By utilizing a selection signal indicating which circuit is to be used, the compression conversion and expansion conversion are performed in a time-division manner.

Furthermore, since the circuit is constructed using PLA, the chip occupancy area is small, and this conversion circuit can be implemented using an LSI.

[Operations] According to the present invention, a circuit capable of selectively executing compression conversion and decompression conversion of a PCM code is configured in one PLA, so that a circuit having an LSI configuration with a small chip area can be realized. Therefore, the above-mentioned problem can be eliminated.

[Embodiment] Fig. 1 is a circuit diagram showing an embodiment of the present invention, in which 1 is a selection circuit, 2 is a PCM code compression/expansion circuit including both a PCM code compression circuit and a PCM code expansion circuit configured by a PLA. , 3 is a data holding register A, 4 is a data holding register B, 5 is an SEL signal receiving terminal in the selection circuit 1, and 6 is an SE in the PCM code compression/expansion conversion circuit 2.
This is an L signal receiving terminal. A is P input to selection circuit 1
CM linear code, B is the PCM nonlinear code input to the selection circuit 1, C is either the PCM linear code A or the PCM nonlinear code, and AA is the PCM output after compression conversion.
The nonlinear code BB is a PCM linear code output after expansion conversion, and SEL is a selection signal for selecting either compression conversion or expansion conversion.

Further, FIG. 2 is a timing diagram for explaining the operation of FIG. 1. The operation of the circuit shown in FIG. 1 will be explained with reference to FIG. In the case of conversion based on the μ law, a PCM linear code A, which has been preprocessed with +33 correction, and a PCM nonlinear code are input to the selection circuit 1 as input codes. A selection signal SEL is input to the SEL signal receiving terminal 6 of the selection circuit 1, which selects either the code A or B, and outputs the output code C from the PCM code compression/expansion conversion circuit 2.
supply to. In FIG. 2, the selection signal SEL is currently controlled from the outside so that the first half is at a low level for compression conversion, and the second half is at a high level for expansion conversion. Therefore, the output code C of the selection circuit 1 is also the selection signal SEL.
Correspondingly, the first half shows a state in which the PCM linear code A is output, and the second half shows a state in which the PCM nonlinear code is output.

The PCM code compression/expansion conversion circuit 2 has its signal receiving terminal 6.
Since the selection signal SEL is similarly inputted from the selection signal SEL, the compression conversion circuit is selected when the selection signal SEL is at a low level, and the expansion conversion circuit is selected when it is at a high level, and either one of the codes is converted. Since this conversion circuit is composed of PAL, the processing time required for conversion is only the gate delay time of PAL, and conversion is performed at extremely high speed. Therefore, by using this one PAL in a time-division manner, compression conversion and expansion conversion can be performed seemingly simultaneously. The code converted at high speed as described above is
When a certain period of time (τ) has elapsed after the state change of the selection signal SEL occurs, data is set in registers A and B, indicated by 3 and 4, which hold these code data. That is, when the converted code is a PCM non-linear code AA, the converted code data is set in register A indicated by 3, and when it is a PcM linear code BB, the converted code data is set in register B indicated by 4. The states of the codes set in registers A and B are shown in REGA in FIG.
It is shown as BB in REGB. Further, the PCM linear code BB set in the register B indicated by 4 is then subjected to a -33 correction operation in a correction circuit (not shown), and becomes a completely expanded code.

Figure 3 shows PA and L of the PCM code compression/expansion conversion circuit.
This is a configuration example. In the figure, 10 is a unit including 13 input signal terminals, and each terminal has an input signal terminal 1.
.about.112 and a selection signal SEL are input. 11 is 13
The unit includes two input signal amplifiers, and outputs the power amplified in-phase and anti-phase logic signals corresponding to the respective input signals. Reference numeral 12 denotes an AND array, which has a matrix structure of column lines consisting of signal lines in phase and opposite phase to the output signal line of the input signal amplifier 11, that is, the input signal, and row lines consisting of AND signal lines. . By connecting the intersection points of this matrix as shown by the X marks in the figure, an arbitrary logical product operation between the input signal and this anti-phase signal can be performed. Reference numeral 13 denotes a unit that incorporates intermediate signal amplifiers between the AND array 12 and the OR array 14 in the number of AND signal lines. Reference numeral 14 denotes an OR array, which has a matrix structure of row lines composed of AND signal lines, which are the output signals of the intermediate signal amplifier 13, and column lines composed of OR signal lines. By connecting the intersection points of this matrix as shown by the X marks in the figure, an arbitrary OR operation is performed between the signals subjected to the AND operation. 15 is a unit including 13 output signal amplifiers. 16 is a unit including 13 output signal terminals, each terminal has an output signal of 0□~013.
is extracted.

Since the circuit shown in FIG. 3 is configured in this manner, a signal is output which is the result of an AND operation between the input signal and this negative phase signal, and an OR operation between the signals on which this AND operation has been performed. That will happen. -8 = In other words, since the output signal is expressed by a logical formula in the sum-of-products form of the input signals, P
If the conversion logic of CM code compression conversion and expansion conversion is expressed in a product-sum form, both conversion circuits can be realized by a PLA. Now, if we perform logical operations for compressing and expanding PCM codes using the μ law, we can realize this conversion using 99 product terms, 13 input lines excluding the sine code, and 13 output lines. The conversion circuit can be constructed from PLA.

In FIG. 3, a PCM linear code A (excluding the sine code) is input from input lines 11 to 112, and is input to an AND array 12 via an input signal amplifier unit 11. In addition, PCM nonlinear codes (excluding the sine code) are input from input lines 11 to I7. That is, two codes A,
B is input from a common input signal line. Separate selection signal S
EL is similarly input to AND array 12 via input signal amplifier unit 11. When compression conversion is performed, a connection is made within the AND array 12 to perform an AND operation with the opposite phase signal of the selection signal SEL (i.e., SEL=O), and when expansion conversion is performed, the selection signal SEL is The AND array 12 is internally connected to perform an AND operation with the in-phase signal (ie, 5EL=1). Of course, these connections are unnecessary for logical product operations unrelated to the selection signal. In FIG. 3, the upper part of the AND array 12 is this SEL'-
The lower part shows an example of the connection for 5EL-1.

Therefore, depending on whether this selection signal SEL is set to a low level (SEL-0) or a high level (SEL-1), one PLA can select whether to perform compression conversion or expansion conversion, thereby achieving high-speed conversion. The specified code conversion can be performed.

In the above embodiment, an example based on the μ law is shown, but a code conversion circuit based on the A law can be similarly realized.

[Effects of the Invention] As described in detail above, according to the present invention, the compression conversion section and expansion conversion section of the PCM code are configured in one PLA, thereby improving the circuit layout and the circuit configuration when the circuit is configured with an LSI. The area of wiring can be efficiently reduced by forming an array structure.

This can be made sufficiently smaller than when an equivalent conversion circuit is realized using a conventional read-only memory or a general gate circuit, so effective use of the LSI chip area can be expected.

Further, by making the code conversion circuit smaller, it becomes easier to incorporate this circuit into an audio device or the like in terms of space.

[Brief explanation of the drawing]

FIG. 1 is a code conversion circuit according to the present invention, FIG. 2 is a timing diagram for explaining the operation of FIG. 1, and FIG. 3 is a PCM
FIG. 2 is a PLA configuration diagram of a code compression/expansion conversion circuit. In the figure, 1 is a selection circuit, 2 is a PCM code compression/expansion conversion circuit, 3 is a register A, 4 is a register B, 5 is an SEL signal receiving terminal in the selection circuit 1, and 6 is a PCM code compression/expansion conversion circuit. SEL signal receiving terminal, 10 is an input signal terminal unit, 11 is an input signal amplifier unit, 12 is an AND array, 13 is a center-open signal amplifier unit, 14 is an OR array, 15 is an output signal amplifier unit, 16 is an output signal terminal unit, A is PCM linear code input, B is PC
M nonlinear code input, C is PCM linear code A or PC
M nonlinear code B, AA is the PCM nonlinear code after compression conversion, BB is the PCM linear code after expansion conversion, SEL is the selection signal, l-112 is the input signal, 0 to 0□
3 is an output signal. ■

Claims (1)

[Claims] A conversion circuit that performs mutual conversion between a linear PCM code and a nonlinear PCM code, comprising: a selection signal for selecting one of the mutual conversions;
The linear P selected in accordance with the signal state of the selection signal
a signal input section that internally inputs a CM code or a nonlinear PCM code; and when a linear PCM code is input to the signal input section,
a conversion unit that performs compression conversion corresponding to the signal state of the selection signal and outputs a nonlinear PCM code; and a conversion unit that performs expansion conversion corresponding to the signal state of the selection signal when the nonlinear PCM code is input to the signal input unit. A conversion unit that outputs a linear PCM and a signal output unit that outputs to the outside the nonlinear PCM code output after compression conversion or the linear PCM code output after expansion conversion are integrated into one program logic array (PLA). 1. A code conversion circuit characterized in that: