JPH01135124A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the dispersion in full scale output current values between respective D/A converters by arranging decentralizingly each single current source of the plural D/A converters so that the adjacent single current sources close to each other are used for different D/A converters. CONSTITUTION:The single current sources 12R-15R, 12G-15G and 12B-15B of each D/A converter having the same current are arranged decentralizingly so that they are located closely to each other and cyclicly. Let each current of four current sources 12R-13R, 13G-14G and 14B-15B from the left each be respectively I1, I2 and I3, then the constant current at the full scale output is 4(2I1+I2+I3) for an R signal D/A converter, 4(I1+2I2+I3) for a G signal D/A converter, and 4(I1+I2+I3) for a B signal D/A converter. Since each output current includes terms I1, I2, and I3, the dispersion of the currents I1, I2, I3 is reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor integrated circuit with a plurality of built-in D/A converters, the purpose is to reduce variations in full-scale output current values between each D/A converter. In a semiconductor integrated circuit incorporating a plurality of D/A converters each having a plurality of single current sources with The current sources are arranged in a distributed manner so that they are for different D/A converters.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit incorporating a plurality of D/A converters.

[Conventional technology]

In recent years, red (R) and blue (B) have been retrieved from image memory.
), and green (G), respectively, into analog video signals (primary color signals) and supplying the converted signals to a color monitor. being developed.

In the above semiconductor integrated circuit, as shown in FIG. 3, a D/A converter 2 for a red signal (R signal), a D/A inverter 3 for a green signal (G signal), and a D
The /A converter 4 is arranged in a concentrated manner in a part of the semiconductor integrated circuit 1 in order to prevent non-uniformity of ion implantation concentration depending on the location during semiconductor manufacturing and to obtain as uniform characteristics as possible.

On the other hand, the D/A converters 2 to 4 described above are required to be high-speed in order to supply three primary color signals to the color monitor in parallel.
Therefore, a current output type D/A converter is usually used. This current output type D/A converter has a configuration in which single current sources 12 to 15 having the same current value are arranged in parallel, as shown in FIG. 4, in order to ensure accuracy such as linearity error. .

That is, FIG. 4 shows an example of a 2-bit D/A converter, in which 2-bit digital signals input in parallel from terminals 6a and 6b are supplied to a decoder 7, where four types of digital signals are output according to the 2-bit values. is converted into a switching signal to control the switching of switches 8 to 11.

The switches 8 to 11 are switches that pass or cut off the output currents of four single current sources 12 to 15, each having the same current value, and when the switches 8 to 11 are on, the corresponding current sources are sent to the output terminal 16. Output the current from. This results in
An analog current having a level corresponding to the value of the input digital signal at the input terminals 6a and 6b is outputted to the output terminal 16 as a digital-to-analog (D/A) conversion signal.

Therefore, as can be seen from FIGS. 3 and 4, in the conventional semiconductor integrated circuit, the current sources of the D/A converters 2 to 4 are arranged in a part of the semiconductor integrated circuit as shown in FIG. close to each other and each D/A converter 2, 3 and 4
were placed in each.

[Problem that the invention seeks to solve]

However, in the conventional circuit shown in FIG.
Current source 12R to 15R1G signal D in At converter 2
The current values of current sources 12G to 15G in the /A converter 3 and current sources 12B to 15B in the B signal D/A converter 4 should be the same, but due to manufacturing variations, There is a problem in that simply arranging the A converters 2 to 4 close to each other does not necessarily mean that they are the same, and that it is difficult to ensure a constant current value at full scale output.

The present invention has been made in view of the above points, and each D/AD
An object of the present invention is to provide a semiconductor integrated circuit that can reduce variations in full-scale output current values between inverters.

[Means for solving problems]

FIG. 1 shows a principle configuration diagram of the main part of the present invention. The present invention is D
/AI] In a semiconductor integrated circuit with multiple built-in inverters, each D/A has the same current value, as shown in Figure 1.
Converter single current source 12R~15R, 12G~15
G, 12B to 15B are arranged close to each other and distributed in a circular manner.

In addition, in order to facilitate comparison with FIG. 5, FIG. 1 shows a 2-bit D/A converter, which is used for R, G, and B signals. ,
In principle, the application of the D/A converter of the present invention is not limited to video signals, and the number of quantization bits of an input digital signal is not limited to 2 bits.

[Effect]

Each single current source in the plurality of D/A converters
Because the single current sources of each D/A converter are distributed cyclically, not for each converter, adjacent single current sources become single current sources in different D/A converters, which makes it difficult to manufacture. It is possible to reduce variations in current values caused by variations in current values.

For example, in the conventional circuit shown in FIG. 5, four current sources 12R to 15R, 12G to 15G, and 12B to 1
Assuming that the current values of 5B are II, 12, and I3, respectively, the constant current value at full-scale output is 4I+ for D/A converter 2, 4I2 for D/A converter 3, and 4I3 for D/A converter 4, respectively. At the output current value of I
l.

The influence of variations in 12.13 is significant.

On the other hand, according to the present invention, four current sources 12R to 13R, 13G to 14G, and 14
Each current value of B to 15B is It.

Assuming I2 and I3, the constant current value at full scale output is 4 (211 + I2 +
I3 >, 4 in the G signal D/A converter (II
+212 +I3 >, 4 (II +I2 +I3) in the D/Δ converter for B signal. Therefore, each output current value is Il.

Since I2 and I3 are included, variations in Il and I2°I3 can be relatively reduced compared to the conventional method.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. In Fig. 2, 01 to Q24 are P-channel MO8 type field effect transistors (FETs), Qs to Q24, respectively.
Q36 is an N-channel MO8 type FET, and 02
5 to Qa constitute the current sources 12R to 15B.

Also, isa, 18b are 2-bit digital signal input terminals for R, 19a, 19b are 2-bit digital signal input terminals for G, 2Qa, 20b are 2-bit digital signal input terminals for B, 21 is a decoder, 22, 23 and 24 is R
These are output terminals for the signal, G signal, and B signal.

In the above circuit, the decoder 21 selects FETQ1 to Q24 according to the values of three types of 2-bit digital signals.
A predetermined signal is applied to the gate of a predetermined FET among them.

For example, the decoder 21 selects FETQ+, Q2 according to the values of the 2-bit digital signals at the input terminals 18a and 18b.
,,Q7,Qs,Q10.

A signal of a predetermined level is supplied to each gate of 0I4, 0I9 and (ho, and these are controlled by switching. For example, when the input digital signals of input terminals 18a and 18b are both logic "'1" and full scale output is performed, , decoder 21
sets Q+, Qy, QCs, and Q10 to off, respectively, and
And it outputs a signal that turns on each of Q2, Qa, Q10, and 020, and FETQ25.02B.

The output currents of Q31 and Q34 are Q2, Qs, Q1
It is output to the output terminal 22 through the 0°QW.

Further, when the logical values of the input digital signals at the input terminals 1sa, 18b are IQIT, 1111+, the decoder 21 turns off Q+, Q7, Q10.020, respectively, and turns off Q2, Q8 . A signal is output to turn on Q10.0I9, and the output currents of FETs Q25, 02B, and Q31 are passed through 02, Qa, and Q10 to the output terminal 22.
At the same time, output of the output current of FETQ34 to output terminal 22 is blocked by FETQ20, which is set to A-F.

Similarly, the decoder 21 has G input terminals 1ga and 1cib.
FETQ3 according to the value of the 2-bit digital signal for
, Q4 , Q9 , QIO, QCs , , Q10
.

A signal of a predetermined level is supplied to each gate of 021 and Q22 to control switching of these, and the input terminal 20a
, 20b, depending on the value of the 2-bit digital signal for B,
FETQs, Q6, Chl, Q10.

A signal at a predetermined level is supplied to each gate of Qll, QCs, Q23, and Q2,1 to control their switching.

In this way, the analog R signal obtained by D/A converting the input digital signals at the input terminals 18a and 18b is taken out from the output terminal 22, and the analog R signal obtained by D/A converting the input digital signals at the input terminals 19a and 19b. The obtained analog G signal is taken out from the output terminal 23, and further sent to the input terminal 20a.
An analog B signal obtained by D/A converting the input digital signal of 20b and 20b is taken out from the output terminal 24.

Here, each FFT constituting the four single current sources in the three types of D/A converters is arranged so that every second FFT has the same D/Δ converter, and the FETs on both sides are different. F and E constitute a single current source for the D/A converter
T, it is possible to ensure a more uniform constant current value at full scale output than in the past.

〔Effect of the invention〕

As described above, according to the present invention, in a semiconductor integrated circuit incorporating a plurality of D/A converters having a plurality of single current sources, adjacent single current sources are connected to different D/A converters. Since the D/A converters are arranged in a distributed manner, it is possible to reduce variations in the current values of the plurality of single current sources between each D/A converter due to manufacturing variations.
This has the advantage that a uniform full-scale output current value of each D/A converter can be ensured.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the main part of the present invention, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is a block diagram of an example of a semiconductor integrated circuit, and Fig. 4 is a D/
FIG. 5 is a block diagram of an example of the A converter. FIG. 5 is a block diagram of an example of the conventional A converter. In the figure, 2 is a D/A converter for the R signal, 3 is a D/AI converter for the G signal, 4 is a D/A converter for the B signal, and 12R, 13R, 14R, and 15R are the D/A converter for the R signal. Current source in A converter, 12G, 13G, 14G, 15G are current sources in D/A converter for G signal, 12BHB, 13B, 14B, 15B are D/A for B signal
Current source in the converter, 21 is a decoder, 22 is an R signal output terminal, 23 is a G signal output terminal, 24 is a B signal output terminal.

Claims (1)

[Claims] A single current source (12R to 15R, 12
In a semiconductor integrated circuit in which a plurality of D/A converters (2, 3, 4) having a plurality of D/A converters (G to 15G, 12B to 15B) are built-in, the plurality of D/A converters (2, 3, 4) Each single current source (12R~15R, 12G~15G, 12B~15
A semiconductor integrated circuit characterized in that B) are arranged close to each other and distributed so that adjacent single current sources are for different D/A converters.