JPH10262159A - Television signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the internal power consumption of a TV signal processing circuit or a D/A converter when effective bit length is short as compared with a case when it is long by executing control so as to permit one or plural bits within the lower side bits of a signal which is inputted to a digital signal processing block or the D/A converter to be 'L'-fixed or 'H'-fixed. SOLUTION: A TV signal inputted to an A/D converter 2 is converted to a 12 bit-parallel digital signal. The 10 high-order side bits in the digital signal are inputted to an arithmetic circuit 4 and the two low-order side bits are inputted to the arithmetic circuit 4 by way of an AND gate circuit 9. When effective bit length is made to be max. so as to execute a signal processing, a control signal 'H' is inputted to a control terminal 13 and the signal is made to pass through AND gates 9-12. When effective bit length is reduced so as to execute the signal processing, the control signal is made to be 'L'. Thus, the power consumption of the respective circuits are reduced in accordance with decreased portions in the time of signal level change-over operations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a circuit for processing a television signal.

[0002]

2. Description of the Related Art FIG. 2 shows a circuit for processing a television signal having a plurality of digital signal processing blocks according to the prior art. As shown in FIG. 2, in this circuit, a value of a rounding error allowable in a process such as A / D conversion as a pre-stage process or a D / A conversion as a post-stage process, and contents of arithmetic processing inside the television signal processing circuit are described. The arithmetic processing is performed by fixing the data bit length of the signal passed between the digital signal processing blocks with a bit length (16 bits in the example of FIG. 2) corresponding to.

Here, when performing television signal processing by switching a plurality of television video signal qualities, or when processing a poorer quality television video signal, input / output signals between the digital signal processing blocks are required. In the data bit configuration of (1), one or more bits on the lower side (LSB side) do not contribute to video quality and become unnecessary bits that are not used for data transfer, thereby shortening the effective bit length. However, in that case, the value of the unnecessary bits output from each digital signal processing block or A / D converter is determined by the result of their internal arithmetic processing or A / D conversion.
Since the power consumption changes in accordance with the D-conversion result, the power consumption for arithmetic processing in each digital signal processing block and the D / A converter due to the change in the value of the unnecessary bit is reduced when the value of the unnecessary bit does not change. Power consumption.

[0004]

An object of the present invention is to provide a D /
When the effective bit length at the time of A conversion, A / D conversion, or calculation of each digital signal processing block is variable,
When the effective bit length is short according to the variable length, the internal power consumption of the television signal processing circuit or the D / A converter can be reduced more than when the effective bit length is long.

[0005]

According to the present invention, in order to achieve the above object, a signal inputted to each digital signal processing block in a television signal processing circuit or a D signal at a subsequent stage is provided.
One or more of the lower bits of the signal input to the / A converter are set to "L" by a gate circuit such as an AND gate.
Power consumption can be reduced by reducing the operating bit length of each digital signal processing block and the subsequent D / A converter processing by enabling control by a control signal so as to be fixed or fixed to “H”. It is a thing.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 1 showing an example of a block configuration of a television signal processing circuit of the present invention.

In FIG. 1, reference numeral 1 denotes an analog television signal input terminal, and reference numeral 2 denotes an A / D converter. 3 is a television signal processing circuit of the present invention, 4 is a first arithmetic circuit (digital signal processing block) in the television signal processing circuit 3, and hereafter, 5 is a second arithmetic circuit, and 6 is a third arithmetic circuit. Arithmetic circuits, 9, 10, 11, 12 are AND gate circuits,
Reference numeral 13 denotes a bit length control terminal. Further, 7 is a D / A converter, and 8 is an output terminal. Next, this operation will be described. The analog television signal input from the input terminal 1 to the A / D converter 2 is converted by the A / D converter 2 into 12
It is converted to a bit parallel digital signal. Of this digital signal, for example, the upper 10 bits (MSB side) are directly input to the first arithmetic circuit 4 of the next stage of the television signal processing circuit 3, while the remaining lower 2 bits (LSB side) are Are input to the first arithmetic circuit 4 via the AND gate circuit 9. Similarly, for the signal input to the second arithmetic circuit 5 and the signal input to the third arithmetic circuit 6, the output of the upper 10 bits of the first arithmetic circuit 4 and the second arithmetic circuit 5 in the preceding stage Each signal is input,
The lower 2-bit output signal is input through AND gate circuits 10 and 11, respectively. Further, as for the signal output from the third arithmetic circuit 6 of the television signal processing circuit 3, the upper 10-bit signal is also converted to the D / D signal at the subsequent stage.
The signal is input to the A converter 7, and the lower two-bit signal is input through the AND gate circuit 12. Each of the AND gate circuits 9, 10, 11, and 12 receives a control signal input from the bit length control terminal 13, and performs a gate operation according to the control signal as described below.

When the television signal input to the input terminal 1 is a signal of higher quality and the signal processing is performed by maximizing the effective bit length in the television signal processing circuit 3, the signal is input to the control terminal 13. When the value of the control signal is set to, for example, “H”, each gate circuit allows the signal to pass through, and the signal input / output between the digital signal processing blocks is transmitted from the A / D converter 2 to the first arithmetic circuit. 4 and the bit length of the signal sent from the third arithmetic circuit 6 to the D / A converter 7 are 10 bits + 2 bits = 12 bits, and similarly, the first arithmetic circuit 1 The bit lengths of the signal sent to the circuit 5 and the signal sent from the second arithmetic circuit 5 to the third arithmetic circuit 6 are 12 bits + 2 bits = 14 bits.

On the other hand, when a poor quality television signal is input from the input terminal 1 and the signal processing is performed by reducing the effective bit length in the television signal processing circuit 3 accordingly, the signal is input to the control terminal 13. By setting the control signal to “L”, for example, a signal fixed to “H” or “L” is output without passing the signal input to each gate circuit. Therefore, among the signals input to each digital signal processing block and the D / A converter 7, the signals output from the AND gate circuits 9, 10, 11, and 12 have fixed values. In digital signal processing performed using the set values, the power consumption of each circuit is reduced in accordance with the decrease in the number of signal level switching operations.

[0010]

As described above, according to the present invention, power can be reduced by controlling the effective bit length.
To realize a television signal processing circuit that prioritizes high-precision signal processing when the effective bit length is large depending on the purpose of use, and prioritizes signal processing with low power consumption when the effective bit length is small. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a block configuration of a television signal processing circuit of the present invention.

FIG. 2 is a diagram showing an example of a block configuration of a conventional television signal processing circuit.

[Explanation of symbols]

1: input terminal, 2: A / D converter, 3: television signal processing circuit, 4, 5, 6: arithmetic processing circuit, 7: D / A converter, 8: output terminal, 9, 10, 11, 12: AND gate circuit, 13: control terminal.

Claims (2)

[Claims] 1. A circuit for processing a television signal having a plurality of digital signal processing blocks, wherein one or a plurality of predetermined bits of an input signal composed of a plurality of bits input to each of the digital signal processing blocks is provided. Each of the gate circuits is input to each digital processing block after being gated by a gate circuit, and each of the gate circuits outputs the predetermined bit as a fixed value according to a control signal, or the value of the signal input to each of the gate circuits. A television signal processing circuit for switching whether or not to output as it is. 2. A predetermined one or more bits of an output signal output from a digital signal processing block at the last stage of the television signal processing circuit are gated by a gate circuit and then output from the television signal processing circuit. Wherein the gate circuit switches between outputting the predetermined bit as a fixed value or outputting the value of the signal input to the gate circuit as it is, according to a control signal. The television signal processing circuit according to the above.