JP2000022536A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means for improving dispersion in characteristics and highly accurately matching them in a semiconductor integrated circuit provided with plural digital-to-analog conversion circuits or analog-to-digital conversion circuits. SOLUTION: A means for finely adjusting a reference level is provided and plural fine adjustment data storage areas are provided. A reference level generation circuit 105 is provided outside this semiconductor integrated circuit and supply is performed from a reference level input terminal 111. The reference level is adjusted in a fine adjustment circuit 103 and then, impressed to the digital-to-analog conversion circuit 102. The three digital-to-analog conversion circuits 102 are used, are partially in charge of R(red), G(green) and B(blue) respectively and convert digital video signals to analog ones. A fine adjustment control circuit for controlling the fine adjustment circuit is denoted by 105. Thus, the dispersion in the characteristics is improved so as to be roughly within 0.1%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a plurality of digital-to-analog conversion circuits, and more particularly to a method for making the characteristics of a plurality of digital-to-analog conversion circuits uniform or for intentionally changing the characteristics. It is.

[0002] The present invention also relates to a semiconductor integrated circuit having a plurality of analog-to-digital conversion circuits, and also relates to a method of making the characteristics of the plurality of analog-to-digital conversion circuits uniform or changing the characteristics intentionally. is there.

[0003]

2. Description of the Related Art FIGS. 7 and 8 show a conventional circuit system in which a plurality of digital-analog conversion circuits are used.

Generally, a digital-analog conversion circuit (10
2) performs a conversion based on a certain reference level.

[0005] As the reference level, for example, a current source, a voltage source, a resistance, a capacitance or the like is used. Alternatively, the clock time may be used together with the capacity. Regarding the selection of the reference level, the same effect is essentially obtained regardless of the method, so that it is described as “reference level” without any particular limitation.

For applications such as audio, video, and measurement, a large number of digital-to-analog conversion circuits having uniform characteristics may be required. In such a case, the most effective method is to incorporate the required number in the same semiconductor integrated circuit as shown in FIG. 8 and operate using the same reference level. This is because, when a plurality of the same digital-analog conversion circuits are incorporated in the same semiconductor integrated circuit, in principle, it can be expected that extremely uniform characteristics can be obtained.

It is known that if a segment-type current addition type digital-analog conversion circuit is used, if the reference current level is adjusted and the full-scale level is adjusted, other characteristics (offset and linearity error) are practically sufficient. I have.

If the design is made with particular attention to the arrangement and wiring,
It is also known that full-scale level fluctuations can be kept below 1%.

[0009] Nevertheless, in practice, a characteristic variation having a random distribution without a specific tendency was observed. Although the full-scale difference is less than 1%, it has a normal distribution.

The inventors conclude that this may be due to minor variations during the manufacturing process. Such fluctuations are random and cannot be corrected by designing.

Conventionally, in order to correct such random variations, a method of adjusting full scale by an external circuit as shown in FIG. 7 has been adopted. Alternatively, test the completed semiconductor integrated circuit and collect data,
There has also been a method of making fine adjustments one by one by a method called trimming. However, in any case, it is obvious that there is a disadvantage from the increase in economy, time, and size.

As another application, there is a case where it is desired to intentionally make a difference in characteristics. However, it is difficult to cope with a semiconductor integrated circuit in which a plurality of digital-analog conversion circuits are integrated on the same chip. It was realized by an external circuit as shown in FIG. For example, in an RGB display of a personal computer, the color balance of three channels may be adjusted not on the display but on the personal computer.

The case where a plurality of digital-analog conversion circuits are used has been described above. However, a similar problem occurs when a plurality of analog-digital conversion circuits are used.

[0014]

SUMMARY OF THE INVENTION The present invention is intended to enable fine adjustment for improving the above-mentioned characteristic variation, and realizes higher accuracy, approximately 0.1% or less. It is intended to be.

In addition to the fine adjustment for correction, the adjustment is positively used to obtain a further effect.

[0016]

According to the present invention, there is provided a semiconductor integrated circuit comprising: (1) at least two digital-analog conversion circuits each having a data input terminal composed of a plurality of bits, a reference level input terminal, and an output terminal. The digital-analog conversion circuit is configured to output analog data corresponding to the digital data applied to the data input terminal to an output terminal based on a given reference level input. And a fine adjustment circuit having a reference level output terminal. The fine adjustment circuit is configured to finely adjust the input reference level and output the finely adjusted reference level to the reference level output terminal. Is connected to a reference level input terminal of the digital-analog conversion circuit.

(2) In (1), a plurality of the fine adjustment circuits are provided, and a reference level output terminal of each of the fine adjustment circuits is connected to a reference level input terminal of each digital-analog conversion circuit. Features.

(3) In (1), the reference level input terminal of at least one digital-analog conversion circuit is not connected to the reference level output terminal of the fine adjustment circuit.

(4) In (1), at least one of the fine adjustment circuits has two or more data storage areas, and two or more data are switched and used for fine adjustment. It is characterized by doing.

(5) In (1), at least one of the fine adjustment circuits has two or more data storage areas, and calculates two or more data, and refers to the calculation result. It is used for fine adjustment.

(6) There are provided two or more analog-digital conversion circuits each having an input terminal, a data output terminal composed of a plurality of bits, and a reference level input terminal.
The digital conversion circuit is configured to output digital data corresponding to the analog data applied to the input terminal to an output terminal based on a given reference level input,
A reference level input terminal, a fine adjustment circuit having a reference level output terminal, the fine adjustment circuit is configured to finely adjust the input reference level and output to the reference level output terminal; A reference level output terminal of the fine adjustment circuit is connected to a reference level input terminal of the analog-digital conversion circuit.

(7) In (6), it is preferable that a plurality of the fine adjustment circuits are provided, and a reference level output terminal of each of the fine adjustment circuits is connected to a reference level input terminal of each analog-digital conversion circuit. Features.

(8) In (6), the reference level input terminal of at least one analog-digital conversion circuit is not connected to the reference level output terminal of the fine adjustment circuit.

(9) In (6), at least one of the fine adjustment circuits has two or more data storage areas, and the two or more data are switched to be used for fine adjustment. It is characterized by doing.

(10) In (6), at least one of the fine adjustment circuits has two or more data storage areas, and calculates two or more data, and refers to the calculation result. It is used for fine adjustment.

[0026]

As described above, in the case of a configuration having two or more digital-to-analog conversion circuits, a fixed reference level is supplied to each digital-to-analog conversion circuit instead of applying a fixed reference level. This makes it possible to adjust each channel independently.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the operation of the present invention will be described in detail based on embodiments.

FIG. 1 shows an embodiment of the present invention. The present invention is implemented by realizing a video signal processing device by a semiconductor integrated circuit. In this example, the reference level generation circuit 105 is outside the semiconductor integrated circuit, and the reference level input terminal 111
Supplied from The reference level is adjusted by the fine adjustment circuit 103 and then applied to the digital-analog conversion circuit 102. In this embodiment, the digital-analog conversion circuit 1
02 are used three, R (red) and G
(Green) and B (Blue) video signals are shared, and digital video signals are converted to analog. A fine adjustment control circuit for controlling the fine adjustment circuit is shown at 105.

FIG. 2 shows the connection between the fine adjustment circuit 103 and the digital-analog conversion circuit 102 in FIG.

FIG. 3 shows a second embodiment of the present invention. In this example, there are three digital-analog conversion circuits 102, but only two fine adjustment circuits 103. Since the B video signal output appearing at the terminal 116 cannot be fine-tuned, it is suitable for use in finely adjusting the other two outputs.

FIG. 4 shows a first example of the fine adjustment circuit. The actual fine-tuning control differs depending on the case where the reference level is indicated by voltage, indicated by current, given by resistance / capacitance, etc., or current is output in response to voltage. There are various implementation methods, and a fine adjustment method suitable for each is selected.

In the group of the inventor, since the present invention is realized by a MOS type semiconductor integrated circuit, a current is selected as a reference level, a current mirror circuit is used as a means for fine adjustment, and a size of a MOS transistor (connection of a minute transistor) is used. (Number). In order to adjust to 0.1% or less, the fine adjustment step width is set in 0.05% units, and 200 of these are prepared, and Tsugo plus or minus 5%
Fine adjustment is possible within the range. In FIG. 4, two fine adjustment data storage areas 401 and 402 are shown. Reference numeral 401 denotes a register which can be set from the outside, which is controlled by software or is freely set by a user. On the other hand, reference numeral 402 denotes a register which is set at the time of shipment from a factory and corrects a manufacturing variation inherent in a semiconductor integrated circuit. Are prepared for you. A programming method generally called a fuse or a method using EPROM (electrical writing) can be applied. In this example, it is designed to switch and select between the adjustment value at the time of shipment from the factory and the user setting value.

FIG. 5 shows a second example of the fine adjustment circuit. In this example, both the fine adjustment data storage areas 401 and 402 are programmable, one of which holds a correction value,
The other holds an offset for the correction value. The arithmetic circuit 501 obtains a final correction value by adding the contents of 401 and 402. The operation is not limited to addition only, but may be subtraction or multiplication in some cases.

FIG. 6 shows a third embodiment of the present invention. In this example, there are two analog-digital conversion circuits 602,
The two reference levels are designed to be finely adjusted to make the characteristics uniform.

[0035]

As described above, according to the semiconductor integrated circuit of the present invention, the characteristic variation between the digital-analog conversion circuit and the analog-digital conversion circuit within the same semiconductor integrated circuit is within 1% to 2%. , Approximately 0.
It is possible to improve the error to within 1%. In addition to the adjustment of errors, it has become possible to positively utilize differences in characteristics.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

2 is a connection diagram of a digital-analog conversion circuit indicated by 102 in FIG. 1 and a fine adjustment circuit indicated by 103 in FIG. 1;

FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a first example of a fine adjustment circuit indicated by 103 in FIG. 1;

FIG. 5 is a diagram showing a second example of the fine adjustment circuit indicated by 103 in FIG. 1;

FIG. 6 is a configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a first example of a semiconductor integrated circuit according to a conventional technique.

FIG. 8 is a diagram showing a second example of a semiconductor integrated circuit according to the related art.

[Explanation of symbols]

 101: semiconductor integrated circuit 102: digital-analog conversion circuit 103: fine adjustment circuit 104: fine adjustment control circuit 105: Reference level generation circuit 106 Storage circuit 107 Video signal processing circuit 108 Host interface circuit 110 Fine adjustment control interface terminal 111 ... Reference level input terminal 112 ... Video signal input terminal 113 ... Host interface terminal 114 ... R video signal output terminal 115 ... G video signal Output terminal 116 B video signal output terminal 201 Fine adjustment control terminal 202 Reference level input terminal 203 Reference level output terminal 20 ... Reference level input terminal 205 Data input terminal 206 Digital-analog conversion output terminal 401 First fine adjustment data storage area 402 ... Second fine adjustment data storage area 403... Fine adjustment data switching circuit 501... Fine adjustment data operation circuit 601... Semiconductor integrated circuit 602. .. .Analog-to-digital conversion circuit 603... Fine adjustment circuit 604... Fine adjustment control circuit 605... Reference level generation circuit 606. 607: video signal processing circuit 608: host interface circuit 610: fine adjustment control interface terminal 611: reference level input terminal 612: · Video signal output terminal 613 ····· Host interface terminal 614 ······ Y video signal input terminal 615 ····· C video signal input terminal 701 ··· By conventional technology Semiconductor integrated circuit 702: Reference level fine adjustment circuit 801: Conventional semiconductor integrated circuit 802: RGB output fine adjustment circuit

Claims (10)

[Claims] In a semiconductor integrated circuit, there are provided at least two digital-to-analog conversion circuits each having a data input terminal consisting of a plurality of bits, a reference level input terminal, and an output terminal. And outputting analog data corresponding to the digital data applied to the data input terminal to the output terminal based on the input reference level input, and comprising a reference level input terminal and a reference level output terminal. An adjustment circuit, wherein the fine adjustment circuit is configured to finely adjust the input reference level and output the finely adjusted reference level to the reference level output terminal. A semiconductor integrated circuit connected to a reference level input terminal of a conversion circuit. 2. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit comprising a plurality of the fine adjustment circuits, wherein reference level output terminals of the fine adjustment circuits are connected to reference level input terminals of respective digital-analog conversion circuits. 3. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit, wherein a reference level input terminal of at least one digital-analog conversion circuit is not connected to a reference level output terminal of the fine adjustment circuit. 4. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit, wherein at least one of the fine adjustment circuits has two or more data storage areas, and two or more data are switched to be used for fine adjustment. 5. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor wherein at least one of the fine adjustment circuits has two or more data storage areas, calculates two or more data, and uses the result of the calculation for fine adjustment. Integrated circuit. 6. A semiconductor integrated circuit comprising two or more analog-to-digital conversion circuits each having an input terminal, a data output terminal composed of a plurality of bits, and a reference level input terminal. It is configured to output digital data corresponding to analog data applied to an input terminal to an output terminal based on a given reference level input, and includes a reference level input terminal and a reference level output terminal. An adjustment circuit, wherein the fine adjustment circuit is configured to finely adjust the input reference level and output the finely adjusted reference level to the reference level output terminal. A semiconductor integrated circuit connected to a reference level input terminal of a conversion circuit. 7. The semiconductor integrated circuit according to claim 6, wherein
A semiconductor integrated circuit comprising a plurality of fine adjustment circuits, wherein reference level output terminals of these fine adjustment circuits are connected to reference level input terminals of respective analog-digital conversion circuits. 8. The semiconductor integrated circuit according to claim 6, wherein
A semiconductor integrated circuit, wherein a reference level input terminal of at least one analog-digital conversion circuit is not connected to a reference level output terminal of the fine adjustment circuit. 9. The semiconductor integrated circuit according to claim 6, wherein
A semiconductor integrated circuit, wherein at least one fine adjustment circuit among the fine adjustment circuits has two or more data storage areas, and two or more data are switched to be used for fine adjustment. 10. The semiconductor integrated circuit according to claim 6, wherein at least one of the fine adjustment circuits has two or more data storage areas, and calculates two or more data. A semiconductor integrated circuit, which is used for fine adjustment with reference to FIG.