JPH01125927A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01125927A JPH01125927A JP28461887A JP28461887A JPH01125927A JP H01125927 A JPH01125927 A JP H01125927A JP 28461887 A JP28461887 A JP 28461887A JP 28461887 A JP28461887 A JP 28461887A JP H01125927 A JPH01125927 A JP H01125927A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- tisi2
- film
- metal
- whole surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000002156 mixing Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229910008479 TiSi2 Inorganic materials 0.000 abstract 2
- 229910008481 TiSi3 Inorganic materials 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract 2
- 230000002269 spontaneous effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 150000002367 halogens Chemical class 0.000 description 3
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来の半導体装置、特にゲート電極上及び不純物拡散層
上にメタルシリサイドを有する（以下サリサイド構造と
略記）ＭＯＩ９型半導体装置の製造方法の一例を第２図
により説明する。An example of a method for manufacturing a conventional semiconductor device, particularly a MOI9 type semiconductor device having metal silicide on a gate electrode and an impurity diffusion layer (hereinafter abbreviated as salicide structure) will be described with reference to FIG.
工程（１）・・・・・・第２図（１）
Ｐ型Ｓ１基板１上に素子分離用酸化膜２．ゲート酸化［
５９（多結晶Ｓｉ）ゲート電極４．低濃度Ｍ型不純物拡
散層５．絶縁膜サイドウオール６、高濃度Ｎ型不純物拡
散層、（ソース・ドレイン）７を順次形成する。Step (1)...Figure 2 (1) An oxide film 2 for element isolation is formed on the P-type S1 substrate 1. Gate oxidation [
59 (polycrystalline Si) gate electrode 4. Low concentration M type impurity diffusion layer 5. An insulating film sidewall 6, a high concentration N-type impurity diffusion layer, and (source/drain) 7 are sequentially formed.
工程（２）・・・・・・第２図（ｂ）
全１ｆＫｒｔを２００〜４００裏スパツタ法で形成し、
７００℃前後の温度でハロゲンランプでアニールするこ
とにより、前記ゲート電極３上及びソース・ドレイン７
上にＴｉ１９１．９を形成し、選択エッチＫＪ：す、未
反応Ｔ１を除去する。Step (2)...Figure 2(b) All 1fKrt is formed by 200-400 back sputtering method,
By annealing with a halogen lamp at a temperature of around 700°C, the top of the gate electrode 3 and the source/drain 7 are removed.
Ti191.9 is formed on top, and unreacted T1 is removed by selective etching KJ:.
工程（８）−・・・・・第２図（ｅ）
８００℃前後の温度でハロゲンランプでアニールした後
に、眉間絶縁膜１０及びコンタクトホ−ル１１を形成し
た後に配線材料Ａｔｌ ４を形成する。Step (8) - Figure 2 (e) After annealing with a halogen lamp at a temperature of around 800°C, after forming the glabellar insulating film 10 and the contact hole 11, the wiring material Atl 4 is formed. .
しかし、前述の従来技術では、工程（２）におけるＴｉ
Ｓｉ、形成時にＮ型不純物は’１’ｉＳｉ、中を容易に
拡散し’１’ ｉ ３１．表面に析出する。このＴｉＳ
ｉ、表面に析出した高濃度のＮ型不純物は’１’ ｉ
３１．の自然酸化を促進し、配線材料用Ａ／。However, in the above-mentioned conventional technology, Ti in step (2)
When forming Si, the N-type impurity easily diffuses into '1'iSi and becomes '1'i31. Precipitates on the surface. This TiS
i, the high concentration of N-type impurity precipitated on the surface is '1' i
31. Promotes the natural oxidation of A/ for wiring materials.
とのコンタクト面に酸化膜を形成することＫなる。この
ため’Ｌ’ｉＳｉ、−Ａｊ間でオーミックなコンタクト
がとれないという問題がありた。It is necessary to form an oxide film on the contact surface with the oxide film. Therefore, there was a problem that ohmic contact could not be established between 'L'iSi and -Aj.
そこで本発明はこのような問題点を解決するもので、そ
の目的はＴｉＳｉ！−、Ａｔ間でオーミックなフッタク
トを得ることにある。Therefore, the present invention is intended to solve these problems, and its purpose is to use TiSi! The objective is to obtain an ohmic foot act between - and At.
本発明は、
α）Ｎ型もしくはＰ型不純物を含む単結晶もしくは多結
晶もしくはアモルファスＳｉ上に第１の金属膜を堆積し
、加熱処理して金属シリサイドを形成する工程
ｂ）前記金属シリサイド上に第２の金属膜を堆積する工
程
Ｃ）前記金属シリサイドと前記第２の金Ｆ４膜の界面に
イオン打込をしてミキシングする工程を含むことを特徴
とする。The present invention includes the steps of α) depositing a first metal film on single crystal, polycrystal, or amorphous Si containing N-type or P-type impurities, and heat-treating to form metal silicide; b) depositing a first metal film on the metal silicide; A step C) of depositing a second metal film is characterized in that it includes a step of implanting and mixing ions into the interface between the metal silicide and the second gold F4 film.
以下第１図により本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to FIG.
工程（１）・・・・・・第１図（α）
Ｐ型Ｓ１基板１上に素子分離用酸化膜２．ゲート醗化膜
３．多結晶Ｓ１ゲート電極４．低濃度Ｎ型不純物拡散層
５．絶縁膜サイドウオール６、゛高濃度Ｎ型不純物拡散
層（ソース・ドレイン）７を順次形成する。Step (1)...Figure 1 (α) An oxide film 2 for element isolation is formed on the P-type S1 substrate 1. Gate oxide film 3. Polycrystalline S1 gate electrode 4. Low concentration N-type impurity diffusion layer 5. An insulating film sidewall 6 and a high concentration N-type impurity diffusion layer (source/drain) 7 are sequentially formed.
工程２・・・・・・第１図＜ｂ＞
全面にＴ１８を２００〜６００又スパツタ法にて堆積す
る。Step 2...Figure 1<b> 200 to 600 layers of T18 are deposited on the entire surface by sputtering.
工程（８）・・・・・・第１図＜ｃ＞
７００℃前後の温度でハロゲンランプでアニールするこ
とＫより、前記ゲート電極４上及びソース・ドＶイン７
上にＴｉ１９１．９を形成し、選択エッチにより未反応
で１を除去する。Step (8)...Figure 1<c> By annealing with a halogen lamp at a temperature of around 700°C, the areas on the gate electrode 4 and the source V-in 7 are removed.
Ti191.9 is formed on top, and unreacted 1 is removed by selective etching.
工程（４）・・・・・・第１図Ｃｄ）
化学的気相成長法により層間絶縁用酸化膜１０を５００
０−４ｏｏｏｉ形成し、ドライエツチング法によりフン
タクトホール１１を形成する。Step (4)...Figure 1Cd) The interlayer insulating oxide film 10 is grown to a thickness of 500 by chemical vapor deposition.
0-4oooi is formed, and a dry etching method is used to form a hole 11.
工程（５）・・・・・・第１図（ａ）
全面にで１１２を２００〜４００Ｘスパツタ法にて形成
する。Step (5)...Fig. 1(a) 112 is formed on the entire surface by a 200-400X sputtering method.
工１１（６）・・・・・・第１図（１）全面１（Ｇｅ１
！ｉをピークがＴｉＳｉ、−Ｔｉ界面にくるようにイオ
ン打込な行い’ｉ’１ｆ９１．−Ｔｉ界面の自然酸化膜
を破壊する。（ミキシングを行う ）
工程（γ）・・・・・・第１図（！Ｉ）全面にＡｔ１４
を６０００〜８０００又スパツタ法に゛て形成し、フォ
トレジストパターンを用い前記Ａｔ、Ｔｉを順次ドライ
エツチングし、配線層を形成する。Engineering 11 (6)...Figure 1 (1) Full surface 1 (Ge1
! Ion implantation was performed so that the peak of i was at the TiSi, -Ti interface.'i'1f91. - Destroys the natural oxide film at the Ti interface. (Mixing) Process (γ)...Figure 1 (!I) At14 on the entire surface
6,000 to 8,000 yen is formed using a sputtering method, and the At and Ti are sequentially dry-etched using a photoresist pattern to form a wiring layer.
以上実施例に基づき具体的に説明したが、本発明は上記
実施例に限定されるものでなく、その要旨を逸脱しない
範囲で種々変更可能であることはいうものでない。Although the present invention has been specifically explained based on the embodiments above, the present invention is not limited to the above embodiments, and does not mean that various changes can be made without departing from the gist thereof.
たとえば金属シリサイドを形成する金属はＴ１以外でも
Ｎｉ、Ｏｏ、Ｗ等の高融点金属であってもよい、またミ
キシングを行うためのイオン打込はＧｅ以外にＳｉ、Ａ
ｓ等でもよい。また、金属シ・ササイド上に形成する金
属はＴ１以外、Ｎ１゜Ｏｏ、Ｗ、Ａｔ、Ｏｕ等の、金属
であってもよい。For example, the metal forming the metal silicide may be a high melting point metal other than T1, such as Ni, Oo, W, etc. In addition to Ge, the ion implantation for mixing may be Si, A
s etc. may also be used. Further, the metal formed on the metal substrate may be other than T1, such as N1°Oo, W, At, and Ou.
更に本実施例においてはＮ型ＭＯＳトランジスタに関し
て述べてきたがＰ型ＭＯ３）ランジスタあるいは０Ｍ０
ｉ９）ランジスタ、Ｂｉｐｏｌａｒトランジスタにおい
ても適・用可能である。Furthermore, in this embodiment, the N-type MOS transistor has been described, but the P-type MO3) transistor or 0M0
i9) It is also applicable to transistors and bipolar transistors.
以上述べた°ように発明によれば’Ｉ’ ｉ Ｓ ｉ、
表面で形成された自然酸化膜はミキシングにより破壊さ
れ、さらに形成されたＴｉ中ではＮ型不純物は°はぼ拡
散しないため、Ｔ１−ムを界面に自然酸化膜はほとんど
形成されない。これＫよりＴｉ８１゜−ムｔはＴ１をは
さんでオーミックなコンタクトが得られるという効果を
有する。As stated above, according to the invention, 'I' i S i,
The natural oxide film formed on the surface is destroyed by mixing, and the N-type impurity hardly diffuses into the formed Ti, so that almost no natural oxide film is formed at the interface of the T1-me. From this K, Ti81°-mt has the effect that ohmic contact can be obtained across T1.
第１図（α）−（ｙ）は本発明の半導体装置の製造工程
を表わす主要断面図、第２図（１）〜（Ｃ）は従来の半
導体装置の製造工程を表わす主要断面図。
１・・・・・・・−Ｐｇ！ｉｌｉ基板
２・・・・・・・・・素子分離用酸化膜５・・・・・・
・・・ゲート酸化膜
４・・・・・・・・・（多結晶＋３１）ゲート電極５・
・・・・・・・・低濃度Ｍ型不純物拡散層６・・・・・
・・・・絶縁膜サイドウオール７・・・・・・・・・高
濃度Ｍ型不純物拡散層（ソース・ドレイン）
８・・・・・・・・・Ｔ１
９・・・…・・・’！’１８１冨
１０・・・・・・層間絶縁膜
１１・・・・・・コンタクトホール′
１２・・・・・・Ｔ１
１！−・・・−Ｇ ・
１４女−６ＡＬ
以上
出願人 セイコーエプソン株式金社
（α）
＜ｂ＞
（Ｃ）
（Ａ）
１１函
＜ｅ＞
算１ 個FIGS. 1(α)-(y) are main cross-sectional views showing the manufacturing process of the semiconductor device of the present invention, and FIGS. 2(1)-(C) are main cross-sectional views showing the manufacturing process of the conventional semiconductor device. 1・・・・・・・・・-Pg! ili substrate 2...Oxide film for element isolation 5...
...Gate oxide film 4... (Polycrystalline +31) Gate electrode 5.
......Low concentration M type impurity diffusion layer 6...
...Insulating film sidewall 7...High concentration M-type impurity diffusion layer (source/drain) 8...T1 9......' ! '181 depth 10...Interlayer insulating film 11...Contact hole' 12...T1 1! -...-G ・ 14th female - 6AL or above Applicant Seiko Epson Co., Ltd. (α) <b> (C) (A) 11 boxes <e> Total 1 piece
Claims (1)
晶もしくはアモルファスＳｉ上に第１の金属膜を堆積し
、加熱処理して金属シリサイドを形成する工程 ｂ）前記金属シリサイド上に第２の金属膜を堆積する工
程 ｃ）前記金属シリサイドと前記第２の金属膜の界面にイ
オン打込をしてミキシングする工程を含むことを特徴と
する半導体装置の製造方法。[Claims] a) step of depositing a first metal film on single crystal, polycrystal, or amorphous Si containing N-type or P-type impurities and heat-treating to form metal silicide b) the metal silicide A method for manufacturing a semiconductor device, comprising: c) depositing a second metal film thereon; c) implanting and mixing ions into the interface between the metal silicide and the second metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28461887A JPH01125927A (en) | 1987-11-11 | 1987-11-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28461887A JPH01125927A (en) | 1987-11-11 | 1987-11-11 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01125927A true JPH01125927A (en) | 1989-05-18 |
Family
ID=17680795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28461887A Pending JPH01125927A (en) | 1987-11-11 | 1987-11-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01125927A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03120820A (en) * | 1989-09-29 | 1991-05-23 | Internatl Business Mach Corp <Ibm> | Method and apparatus for forming metal- lization for interconnecting integrated circuits |
-
1987
- 1987-11-11 JP JP28461887A patent/JPH01125927A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03120820A (en) * | 1989-09-29 | 1991-05-23 | Internatl Business Mach Corp <Ibm> | Method and apparatus for forming metal- lization for interconnecting integrated circuits |
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