JPH01124035A - Output data control device - Google Patents

Abstract

PURPOSE:To surely hold an output signal obtained immediately before the generation of abnormality even at the time of generating runaway by providing the title device with the 1st and 2nd latch circuits and controlling the 2nd latch circuit by an external abnormality diagnosis output signal. CONSTITUTION:A data output circuit is constituted of a microcomputer 10 and the 1st and 2nd latch circuits 16, 18. The 2nd latch circuit 18 for holding an output signal from an operation part based upon control algorithm by means of a signal other than an output instruction from the microcomputer 10 generates no output until a signal based upon a self-diagnosis function 20 indicates a normal state even if output instructions due to the runaway of the microcomputer 10 are repeatedly applied. Consequently, the output signal generated immediately before the generation of abnormality can be surely held.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention is used in the field of peripheral circuits of microcomputers.

The present invention relates to an output data control device, and more particularly to an output data control device for holding output data before the occurrence of an abnormality in a computer, and is used in a process control device, a sequence controller, etc.

(b) Conventional technology When an abnormality occurs in a control device consisting of a microcomputer, it is possible to retain the output data of the control device as the output data immediately before the abnormality occurred, so that the control object is not adversely affected. It is necessary for safety reasons.

In the control device using a microcomputer etc. near H,
It has a self-diagnosis function to detect abnormalities in itself. For example, with the configuration shown in Fig. 5, when an abnormality occurs, the calculation results by the control algorithm are sent to the latch circuit 12 (L).
) so that the output immediately before the error occurs is retained.

In FIG. 5, 10 is a microcomputer, 20 is a self-diagnosis function circuit, and 14 is an AND circuit. The output signal of the self-diagnosis function circuit 20 is π1. is set for normal cases and for H5 abnormal cases.

Therefore, in the case of an abnormality, the latch signal remains at L, the input data of the latch circuit 120 does not become output data, and the input data before the latch signal becomes L is held and output.

When the latch signal becomes H, the input data of the latch circuit 120 is taken in and becomes the output data as it is. In the following, the control logic of the latch signal will be understood in this way.

(c) Problems to be Solved by the Invention However, the conventional example shown in FIG. 5 is insufficient. For example, if the operation of a microcomputer goes out of control, an abnormal signal (not based on the control algorithm) will be output many times before the abnormality is detected by a monitoring function such as a watchdog timer as one of the self-diagnosis functions. As a result, the output signal immediately before the abnormality occurrence cannot be maintained.

This is illustrated by FIGS. 6 and 7. Figure 6 shows normal operation. Output command H is issued from the microcomputer at the output of the calculation result, and the WDT (watchdog timer) is reset at every sampling period with "rWDT reset" in normal operation, so the output ABN of the self-diagnosis function circuit 20 is H
The latch signal remains unchanged, and the latch signal becomes H by the AND circuit 14.

FIG. 7 shows an example where the microcomputer goes out of control and outputs repeatedly. W in case of abnormality or runaway
Although there is no DT reset operation, at the point when the reset is applied, it is determined that a runaway has occurred, and the output signal γπ ball from the self-diagnosis function circuit 20 becomes L.

Therefore, the latch circuit 12 (L) outputs (b) or (
C) is held, and the output immediately before the abnormality occurs, that is, the output one sampling period before, is not held.

An object of the present invention is to reliably maintain the output signal immediately before the abnormality occurs even if a runaway occurs during the operation of the microcomputer.
An object of the present invention is to provide an output data control device.

(d) Means for Solving Problems The above object is to provide a microcomputer, a data output circuit that outputs data from the microcomputer via a first latch circuit and a second latch circuit, and a first latch circuit.
A first control circuit that controls the latch circuit by at least an output command from a microcomputer, and a second control circuit that controls the second latch circuit by an external abnormality diagnosis output signal such as a watchdog timer. , achieved.

(E) A second latch circuit is provided in the action data output circuit to hold the output signal from the arithmetic unit based on the control algorithm as a signal other than the output command from the microcomputer, and the output command is generated when the microcomputer (software) runs out of control. No matter how many times it is received, unless the signal from the self-diagnosis function (watchdog timer, etc.) indicates normality, it will not be output to the outside. In this way, when an abnormality occurs, the output signal immediately before the abnormality occurs is reliably maintained.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to FIGS. 1 to 4 of the drawings.

FIGS. 1 and 2 are circuit block diagrams showing each embodiment.

16 is a first latch circuit, 18 is a second latch circuit, 2
2 and 24 are AND circuits.

The microcomputer 10 and latch circuits 16 and 18 constitute a data output circuit.

The operation of the embodiment according to FIG. 1 is as follows.

A normal state, that is, a case where no abnormality is detected by the self-diagnosis function circuit 20, is shown in FIG.

a. The calculation result is the output command of the microcomputer 10 (
The latch signal "
HJ), the data is transferred to the latch circuit 16 (Ll
).

b0 diagnostic output device ABN, is rH, so WDT
The reset signal directly becomes the latch signal 'HJ for the latch circuit 18 (L2), and the operation result latched by the latch circuit 16 (Ll) by its rising edge is as follows.
It is latched by the latch circuit 18 (L2).

That is, the calculation results from the calculation section are output as they are.

An example of when an abnormality occurs is shown in FIG.

If an abnormality other than runaway of the microcomputer 10 is detected by the self-diagnosis circuit 20, its output ABN becomes 'LJ, so that the latch signal rH, to the latch circuit 18 (L2) is not output.

Even if the VDT reset signal 'HJ is output, the latch signal 'HJ is not output by the AND circuit 22, so the output immediately before the abnormality occurs (that is, one sampling period before) remains latched in the latch circuit 18 (L2). Become.

In addition, if the microcomputer goes out of control and output commands are issued many times within the sampling period, a. Latched.

b. Due to runaway (WDT reset operation does not occur), the output signal ππ ball of the self-diagnosis circuit becomes rL at time ta, but since the WDT reset signal is not output from the microcomputer, the above The abnormal data latched by the latch circuit 16 (LL) in step a is not latched by the latch circuit 18 (L2), and the abnormal data immediately before the abnormality occurs (that is, one sampling period before) is not latched by the latch circuit 18 (L2). The output remains latched.

In this way, when an abnormality occurs, the output immediately before the abnormality occurs is held.

Furthermore, the embodiment shown in FIG. 2 is a configuration in which the microcomputer immediately stops operating (does not issue a WDT reset) when an abnormality is detected by the self-diagnosis circuit. , If an abnormality is detected, the WDT reset will not be issued, so the latch circuit IM1B (L
In case 2), no new data is taken in, and the output immediately before the occurrence of the abnormality (that is, one sampling period before) remains latched.

(g) Effects Even if the microcomputer (software) tries to output an abnormal output due to runaway, the output signal immediately before the abnormality occurs will be reliably maintained and will not adversely affect the controlled object.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit example showing one embodiment of the present invention.
Fig. 2 is a similar diagram showing another embodiment, Fig. 3 is an illustrative diagram of a normal time chart based on Fig. 1, Fig. 4 is an example of an abnormal time chart when visiting the park, and Fig. 5 is a circuit of a conventional example. The block diagram, FIG. 6, is an example of a time chart in a normal state, and FIG. 7 is an example of a time chart in an abnormal state. 10 is a microcomputer, 12, 16 and 18 are latch circuits, 20 is a self-diagnosis circuit, and 22 and 24 are AND circuits. Patent applicant: Shimadzu Corporation?

Claims (1)

[Claims] a microcomputer, a data output circuit that outputs data from the microcomputer via a first latch circuit and a second latch circuit, and a first latch circuit that controls the first latch circuit based on at least an output command from the microcomputer. An output data control device comprising: a control circuit; and a second control circuit that controls a second latch circuit using an external abnormality diagnosis output signal such as a watchdog timer.