JPH01124023A - Video signal converting means for bit block transfer lsi - Google Patents

Abstract

PURPOSE:To output video signals to a hard copying device or the like by including plural shift registers with different clocks in a bit block transfer LSI to obtain multiple video signals with different speeds. CONSTITUTION:The bit block transfer LSI is used for pixel data writing in a frame buffer 5, the contents of a memory are read out respectively different timing and pixel data in a raster direction are converted into a video signal in the LSI. Namely, plural optional shift register 4a-4n with respectively different speeds are prepared and data in the frame buffer 5 are loaded to the registers 4a-4n so that the data can be simultaneously outputted to other devices with different speeds in addition to output conversion to a video monitor. Consequently, data can be simultaneously outputted to the hard copying device e.g. by parallel operation with a video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Conventionally, writing and reading pixel data in a frame buffer is performed by a bit block transfer LSI, while reading is performed by a shift register in a memory element constituting the frame buffer. Either use the built-in dual port memory to perform parallel-to-serial conversion and then convert it into a video signal, or prepare an external high-speed shift register to read out the data in the frame buffer in parallel, and use it as a video signal. there was.

In recent years, in addition to processing for normal displays, frame buffer data has been transferred to monitors and other devices with different speeds, such as plotters and hard copy devices.
There has been an increasing demand for simultaneous output of video signals in parallel operation. In contrast, with a dual-port memory structure, while it is easy to convert frame buffer data into a video signal, it is difficult to convert video signals at multiple speeds with a single set of memory, and external shift・The register method requires a complicated circuit and has drawbacks in terms of cost and stability.

In the present invention, since the bit block transfer LSI is used to write pixel data to the frame buffer and is directly connected to the memory element, the memory is read at different timings at the same time as writing, and raster unidirectional This method converts pixel data into a video signal inside a bit block transfer LSI.

In other words, you can prepare multiple sets of shift registers with different speeds, load the data in the frame buffer into these, and convert not only the output to a video monitor but also output to other devices with different speeds. made possible at the same time.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit diagram related to the present invention. In Figure 1, 1 is a register that stores pixel data given from an external processor, and 2 is a pixel register that latches data in the frame buffer (referred to as source data).
Source data processing circuit consisting of a source data register, barrel shift, etc. 3 is a circuit for performing logical operations on the contents of registers 1 and 2, 48 to 4n are for loading pixel data in the frame buffer in parallel The shift register converts this into serial data, and is provided with clocks C Pa to C P n each having a different speed. 5 indicates a frame buffer.

FIG. 2 shows a timing chart for accessing the frame buffer. In the figure, RAS and CAS are dynamic RAM row and column address control signals, respectively, WR is a data write signal to the frame buffer, and LDa and LDi are load signals to any of shift registers 48 to 4n, respectively. . The operation shows one cycle at two timings, ■ and ■.
is composed of write timing, and ■ is composed of read timing. At the write timing, each of the circuits 1 to 3 operates together with the read/modify write, and pixel data is written into the frame buffer.

On the other hand, in the timing chart, one cycle time is set according to the fastest video signal, so
A read operation ■ exists in each cycle.

With such timing settings, when performing low-speed video signal conversion, frame buffer data must be loaded into any of the shift registers 48-4n at predetermined cycle intervals.

Loading of this low-speed shift register is carried out by stealing the write timing ■ out of one cycle of the timing chart. In FIG. 2, ■ indicates this relationship. LD for the fastest video load signal
Assuming that a, LDa is output every cycle. On the other hand, LDi is outputted to the low-speed shift register at regular cycle intervals at the timing of the write time of the basic cycle. These load signals and timing charts are generated by receiving a write or read request signal from the control circuit, encoding these signals, and converting the data into R/R signals stored in various timing patterns as shown in FIG. O M (Read only mem
ory) and RAM (Random access m
This can be easily created by setting the address to ``emory''. This method is not the subject of the present invention and will therefore be omitted.

In this way, multiple shift clocks with different shift clocks can be used.
By incorporating registers into a bit block transfer LSI, multiple video signals with different speeds can be obtained at low cost using a general RAM without using dual port memory. This allows output to a hard copy device or the like without the need for special additional circuitry and without affecting the video monitor signal.

[Brief explanation of the drawing]

FIG. 1 is a bit block transfer LSI circuit diagram according to the present invention. FIG. 2 is a frame buffer access timing chart according to the present invention. 1 Pixel data register 2 Pixel source data processing circuit 3 Logic operation circuits 48 to 4n Shift register 5 Frame buffer ■ Basic timing chart write cycle ■ Basic timing chart read cycle ■ Shift register load timing ·cycle

Claims (1)

[Claims] Regarding a display device configured with a frame buffer, in a circuit that reads out pixel data written in the frame buffer in parallel in the raster (scanning) direction and converts it into a video signal, a pixel logic operation circuit, a barrel shifter, The input/output terminals of the memory elements constituting the frame buffer are connected to a bit block transfer LSI, and the pixel write timing and scanning direction read timing for video signal conversion are set as basic cycles for frame transfer. a first means for reading pixel data of the frame buffer into the LSI at raster direction read timing; and at least two sets of parallel/serial conversion shift registers each having a different shift clock in the LSI. and a second means for stealing the write timing, reading pixel data of the frame buffer at predetermined time intervals, and loading the pixel data into the shift register. A bit block transfer LSI circuit that makes it possible to output buffer pixel data not only as video monitor information, but also to devices with different speeds in parallel processing.