JPH01122144A - Plastic semiconductor package - Google Patents
Plastic semiconductor packageInfo
- Publication number
- JPH01122144A JPH01122144A JP27923187A JP27923187A JPH01122144A JP H01122144 A JPH01122144 A JP H01122144A JP 27923187 A JP27923187 A JP 27923187A JP 27923187 A JP27923187 A JP 27923187A JP H01122144 A JPH01122144 A JP H01122144A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- tab
- resin
- recess
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000004033 plastic Substances 0.000 title claims description 13
- 239000011347 resin Substances 0.000 claims abstract description 27
- 229920005989 resin Polymers 0.000 claims abstract description 27
- 230000008646 thermal stress Effects 0.000 abstract description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 239000010931 gold Substances 0.000 abstract description 3
- 230000000704 physical effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、プラスチック半導体パッケージに係り、とく
に成形時、温度サイクル時、半田リフロー時の温度負荷
によってレジンクラックなどの強度信頼性を確保するの
に好適なプラスチック半導体パッケージに関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to plastic semiconductor packages, and in particular, to ensure strength reliability against resin cracks and the like due to temperature loads during molding, temperature cycling, and solder reflow. The present invention relates to a plastic semiconductor package suitable for.
従来のレジンで封止する半導体パッケージはたとえば実
開昭５５〜６６０６８号公報に記載され、これを第４図
に示すようにチップ１とタブ２とをＡ。A conventional semiconductor package sealed with resin is described in, for example, Japanese Utility Model Application Publication No. 55-66068, and as shown in FIG.
ペースト（図示せず）などにて固着したのち、全線３と
リードフレーム５でボンディングし、レジン４で封止し
て半導体パッケージを形成している。After being fixed with a paste (not shown) or the like, all the wires 3 are bonded to the lead frame 5, and sealed with resin 4 to form a semiconductor package.
しかるに上記の方法ではモールドしたのちの冷却過程や
温度サイクル時、半田リフロー時の加熱冷却過程でタブ
２上に搭載したチップ１が微小程度（数ｒ程度）ではあ
るが変位する。この微小なチップ１の変位は、半導体パ
ッケージを形成するレジン４の熱応力の増加に大幅に影
響するため、レジンクラックが発生する問題があった。However, in the above method, the chip 1 mounted on the tab 2 is slightly displaced (about several r) during the cooling process after molding, during temperature cycling, and during the heating and cooling process during solder reflow. This minute displacement of the chip 1 significantly affects the increase in thermal stress of the resin 4 forming the semiconductor package, and therefore there is a problem in that resin cracks occur.
そこで、上記の問題を解決するため、従来たとえは、第
５図に示すようにタブ２の裏面に複数のデインプル６を
形成するかまたは第６図に示すように上記チップ１より
も小さい形状の貫通する空隙７を形成したものが実施さ
れる。Therefore, in order to solve the above problem, in the conventional example, a plurality of dimples 6 are formed on the back surface of the tab 2 as shown in FIG. One in which a penetrating gap 7 is formed is implemented.
前記従来技術においては、タブ２のデインプル６または
空隙７内にレジンが入り込むため、タブ２とレジン４と
の熱膨張係数の違いから、第４図の場合にはデインプル
６間のタブ２内、また第５図の場合には空隙７からタブ
２内に割れが発生する問題があった、
本発明の目的は、チップや近傍のレジン部に発生する熱
応力を軽減し、クラックの発生を防止して強度信頼性を
大幅に確保可能とするプラスチック半導体パッケージを
提供することにある。In the prior art, since the resin enters into the dimples 6 or gaps 7 of the tab 2, due to the difference in thermal expansion coefficient between the tab 2 and the resin 4, in the case of FIG. In addition, in the case of Fig. 5, there was a problem in which cracks were generated in the tab 2 from the void 7.The purpose of the present invention is to reduce the thermal stress generated in the chip and the resin part nearby, and to prevent the occurrence of cracks. The object of the present invention is to provide a plastic semiconductor package that can significantly ensure strength and reliability.
前記の目的は、タブおよびチップをレジンで封止したプ
ラスチック半導体パッケージにおいて、上記タブの上記
レジン搭載面にあらかじめ凹みを形成し、この凹みに上
記チップを固嵌するように構成することによって達成さ
れる。The above object is achieved by forming a recess in advance on the resin mounting surface of the tab in a plastic semiconductor package in which a tab and a chip are sealed with resin, and by configuring the chip to be firmly fitted into the recess. Ru.
本発明は、上記タブの上記レジン搭載面にあらかじめ形
成した凹みに上記レジ／を固嵌したので、レジン部に発
生する熱応力を大幅に低減することができ、これによっ
て温度サイクル寿命などの特性を著しく向上することが
できる。In the present invention, since the register is firmly fitted into the recess formed in advance on the resin mounting surface of the tab, the thermal stress generated in the resin part can be significantly reduced, thereby improving characteristics such as temperature cycle life. can be significantly improved.
以下、本発明の実施例を示す第１図および第２図につい
て説明する。Hereinafter, FIG. 1 and FIG. 2 showing an embodiment of the present invention will be explained.
第１図に示すように、タブ２′のチップ１搭載面２ａ’
にあらかじめ凹み８ｔ−形成し、この凹み８内にＡｙペ
ースト（図示せず）を塗布してチップ１′を固嵌したの
ち、金線３とリードフレーム５でボンディングし、レジ
ン４で封止してプラスチック半導体パッケージを構成し
ている。As shown in FIG. 1, the chip 1 mounting surface 2a' of the tab 2'
A recess 8t is formed in advance in the recess 8, and after applying Ay paste (not shown) in the recess 8 and firmly fitting the chip 1', bonding is performed with the gold wire 3 and the lead frame 5, and the resin 4 is used to seal the chip. plastic semiconductor packages.
上記タブ２′およびチップ１′は、その−実施ｇＡＪを
第２図に示すように、互いに同一材質でおるＳｎ十Ｎｉ
メツキを施した銅合金にて形成している。この物性値は
、ヤング率ＥがＥ−９０〜１３０ Ｇ Ｐａで、線膨張
係数αがα＝（１４〜１９）Ｘ１０−’／℃である。ま
たタブ２′はその厚さｈをｈ＝α２〜ＣＬ５■で形成し
、チップ１′を搭載する面２ａ’にはあらかじめプレス
を用いて深さｔがｔ＝（α２〜α８）ｈの矩形状をした
凹み８′を形成し、この凹み８の内周面にｋｆベースを
塗布している。さらに上記レジン４ は、石英式りエポ
キシ樹脂で形成され、この物性値は、ヤング率ＥがＥ＝
９０〜１３０ＧＰ、で線膨張係数αがα＝（５〜２５）
Ｘ１０−’／ｌである。As shown in FIG. 2, the tab 2' and the tip 1' are made of the same material as Sn and Ni.
It is made of plated copper alloy. As for the physical properties, the Young's modulus E is E-90 to 130 GPa, and the linear expansion coefficient α is α=(14 to 19)X10-'/°C. The tab 2' is formed with a thickness h=α2~CL5■, and a rectangle with a depth t=(α2~α8)h is formed using a press in advance on the surface 2a' on which the chip 1' is mounted. A shaped recess 8' is formed, and the inner peripheral surface of this recess 8 is coated with kf base. Furthermore, the resin 4 is made of quartz-based epoxy resin, and its physical properties include Young's modulus E=E=
90-130GP, linear expansion coefficient α = (5-25)
X10-'/l.
つぎに、上記タプダの他の一実施例は、タブ２を５ＯＮ
１入りの鉄−Ｎ１合金にて形成している。この物性値は
、ヤング率ＥがＦｉ＝１４０〜２００ＧＰａで線膨張係
数αがα＝（７〜１２）１０／℃である。その他の条件
は上記の一例と同一である。Next, in another embodiment of the above tapda, the tab 2 is turned 5 ON.
It is made of iron-N1 alloy. As for the physical properties, the Young's modulus E is Fi=140 to 200 GPa, and the linear expansion coefficient α is α=(7 to 12)10/°C. Other conditions are the same as in the above example.
つぎに、上記タブ２′のさらに他の一実施例は、タブ２
′ｔ″４２Ｎｉ入りの４２７０イにて形成している。こ
の物性値は、ヤング率ＥがＥ＝１５０〜１８００Ｐ、で
、線膨張係数αがα＝（２゜５〜６） ｘ １ｏ−６，
”ｃである。Next, yet another embodiment of the tab 2' is the tab 2'.
't'' is made of 4270A containing 42Ni.The physical properties of this material are Young's modulus E = 150 to 1800P, and linear expansion coefficient α = (2°5 to 6) x 1o-6. ，
“c.
また、封止するレジ７４′としては、ポリイミド樹脂に
て形成することも可能である。Furthermore, the resist 74' to be sealed can also be formed of polyimide resin.
さらにタブ２′上にチップ１′を固着させるための物質
は、通常Ａｐペースト、ＬＳペーストを通常の方法で塗
布すれば十分である。Furthermore, as a substance for fixing the chip 1' onto the tab 2', it is sufficient to apply Ap paste or LS paste in a conventional manner.
つぎに上記タブ２′の他の一実施例として第３図に示す
ようにタブ２′のチップ１′搭載面２ａ’にあらかじめ
幅方向を貫通する凹み８′ヲ形成し、この凹み８′内に
チップ１′を固嵌してチップ１の長手方向を拘束してい
る。Next, as another embodiment of the above-mentioned tab 2', as shown in FIG. The chip 1' is tightly fitted to restrain the chip 1 in its longitudinal direction.
したか−・て、本発明によるプラスチック半導体パッケ
ージは、チップがタブ上で移動することがなく、いわゆ
る完全固着の状態であるため、チップ端近傍のレジン部
およびタブコーナのレジン部に発生する熱応力が著しく
低減してレジンクラックの発生を防止することができる
。Therefore, in the plastic semiconductor package according to the present invention, the chip does not move on the tab and is in a so-called completely fixed state, so thermal stress generated in the resin part near the chip edge and the resin part at the tab corner is reduced. is significantly reduced, and the occurrence of resin cracks can be prevented.
またパッケージの端面に設置されているリードフレーム
間のレジン貫通りラックを防止することができる。Furthermore, it is possible to prevent the rack from penetrating the resin between the lead frames installed on the end face of the package.
さらにこれらによってプラス半導体パッケージの温度サ
イクル寿命を従来に比較して約２倍向上でき、かつ半田
リフローなどの熱負荷に対して強度信頼性を大幅に向上
することができる。Furthermore, these make it possible to improve the temperature cycle life of the positive semiconductor package by about twice as compared to the conventional one, and to greatly improve the strength reliability against heat loads such as solder reflow.
本発明によれば、チップおよびタブ近傍のレジン部に発
生する熱応力を軽減し、クラックの発生を防止して強度
信頼性を大幅に向上することができる。According to the present invention, it is possible to reduce the thermal stress generated in the resin portion near the chip and the tab, prevent the occurrence of cracks, and significantly improve the strength reliability.
第１図は本発明の一実施例であるプラスチック半導体パ
ッケージを示す縦断面図、第２図は第１図に示ｔタブの
一実施例を示し、（ａ）は平面図、（ｂ）はそのＡ−Ａ
断面図、（ｃ）はそのＢ−Ｂ断面図、第３図は第１図に
示すタブの他の一実施例を示し、（ａ）は平面図、（ｂ
）はそのＣ−Ｃ断面図、（Ｃ）はそのＤ−Ｄ断面図、第
４図は従来のグラスチック半導体パッケージを示す縦断
面、第５図は従来のタブの一例を示し、（ａ） ′Ｖｉ
その平面図、Ｃｂ）は断面側面図、第６図は従来のタグ
の他の一例を示し、（ａｌはその平面図、（ｂ）はその
断面側面図である。
１・・・チップ
２・・・タブ
３・・・金線
４・・・レジン
５・・・リードフレーム
８．８・・・凹み。
第１Ｉ￥］
第２図
（ａ＞ ０（１）
１′・・・チ、ソγ ４ しシ゛ンｚ１
フ フ′” ５・・・）−ドフし−ム３・金
ｕ＜ ８．８’・回社
第３図
（ｂ）
第４図
第５図
ＣＱ’）
（ｂ）
〒２０１２
第６図
（α） （ｂ）FIG. 1 is a vertical cross-sectional view showing a plastic semiconductor package as an embodiment of the present invention, FIG. 2 is an embodiment of the T tab shown in FIG. 1, (a) is a plan view, and (b) is a top view. Its A-A
3 shows another embodiment of the tab shown in FIG. 1, FIG. 3 shows a plan view, and FIG.
) is a cross-sectional view along line C-C, (C) is a cross-sectional view along line D-D, FIG. 4 is a vertical cross-section showing a conventional glass semiconductor package, and FIG. 5 is an example of a conventional tab. 'Vi
Its plan view, Cb) is a cross-sectional side view, and FIG. 6 shows another example of the conventional tag, (Al is its plan view, and (b) is its cross-sectional side view. 1...Chip 2. ...Tab 3...Gold wire 4...Resin 5...Lead frame 8.8...Concave. γ 4 symbol z1
Fufu'" 5...) - Doff Shim 3, Gold u <8.8', Times Figure 3 (b) Figure 4, Figure 5 CQ') (b) 〒2012 Figure 6 ( α) (b)
Claims (1)
半導体パッケージにおいて、上記タブの上記レジン搭載
面にあらかじめ凹みを形成し、この凹みに上記チップを
固嵌するように構成したことを特徴とするプラスチック
半導体パッケージ。 ２、上記凹みは、上記タブの上記レジン搭載面と平行な
一方向を開口するように構成したことを特徴とする特許
請求の範囲第１項記載のプラスチック半導体パッケージ
。 ３、上記凹みは、上記タブの全厚みに対し２０〜８０％
に構成したことを特徴とする特許請求の範囲第１項記載
のプラスチック半導体パッケージ。[Claims] 1. In a plastic semiconductor package in which a tab and a chip are sealed with resin, a recess is formed in advance on the resin mounting surface of the tab, and the chip is firmly fitted into the recess. A plastic semiconductor package featuring: 2. The plastic semiconductor package according to claim 1, wherein the recess is configured to open in one direction parallel to the resin mounting surface of the tab. 3. The above-mentioned recess is 20-80% of the total thickness of the above-mentioned tab.
A plastic semiconductor package according to claim 1, characterized in that the plastic semiconductor package is configured as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27923187A JPH01122144A (en) | 1987-11-06 | 1987-11-06 | Plastic semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27923187A JPH01122144A (en) | 1987-11-06 | 1987-11-06 | Plastic semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01122144A true JPH01122144A (en) | 1989-05-15 |
Family
ID=17608260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27923187A Pending JPH01122144A (en) | 1987-11-06 | 1987-11-06 | Plastic semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01122144A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635756A (en) * | 1990-04-06 | 1997-06-03 | Hitachi, Ltd. | Semiconductor device, lead frame therefor and memory card to provide a thin structure |
-
1987
- 1987-11-06 JP JP27923187A patent/JPH01122144A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635756A (en) * | 1990-04-06 | 1997-06-03 | Hitachi, Ltd. | Semiconductor device, lead frame therefor and memory card to provide a thin structure |
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