JPH01122114A - Semiconductor device, wafer for the same device and manufacture thereof - Google Patents

Abstract

PURPOSE:To unitize and uniformize the characteristics of formed circuit elements by providing a block having a side made of a crystalline surface (100) partitioned by a plurality of grooves crossing perpendicularly to each other. CONSTITUTION:A block 1 has form sidewall faces made of crystalline faces (100). Thus, when circuit elements are formed on the side faces, works, such as formation of films and ion implantation can be uniformly conducted between the side faces. Accordingly, the elements formed on the side faces of the block 1 can perform uniform characteristics. A plurality of first and second grooves 5, 20 crossing perpendicularly each other are provided on the main surface side of the substrate. Thus, the sidewalls of the grooves utilized when the elements are formed on the surface of the substrate are widely provided, the characteristics of the elements on the sidewall faces of the grooves can be unitized, and irregularities in the performances of the elements among lots of manufacturing steps are eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, a wafer 1 for a semiconductor device, and a method for manufacturing a semiconductor device.

[Prior art and its problems] High-density 4M-D using sidewall isolated capacitor cells applicable to folded bit lines by Nagatomo et al.
RAM (IEDM 86.144-147, 198
6, IEEE) discloses a semiconductor device in which a plurality of first and second grooves orthogonal to each other and a block portion having side surfaces separated by the grooves are formed in the main surface side portion. It is shown. The semiconductor device has a circuit element on the side surface of the block portion. However, M
, Nagatomo et al. do not take into account the direction in which the first and second grooves are formed on the semiconductor substrate with respect to the crystal plane of the semiconductor substrate.

On the other hand, V, G, K REDDI and others (7) rshi IJ: +
Channeling of phosphorus ions into the body (APPLI)
ED PHYSICS LETTERS No. 20
Vol. No. 1.30-31, January 1, 1972) and E. A. IRENE, “Effect of trace moisture on thermal oxidation of silicon in an oxygen atmosphere” (JOURNAL
OF THE ELECTROCHEMICA
L 5OCIETY, 5QLID-8TAT
E 5CIENSE AND TECHN
OLOGY, pp. 1613-1616, December 1974) shows that the degree of ion implantation varies depending on the exposed crystal plane. “Research on trench capacitor structure J (IEEE E
LECTRON DEVICE LETTER3,
EDL-6 volume, No. 5, 215-218 Wataru, 1985
In order to stabilize the degree of ion implantation in the grooves (May 2015), a wafer with a (1001 crystal plane) and an orientation flat of (11'O) was used with an orientation flat of 45 The idea is to draw parallel grooves at an angle of .

However, in the structure disclosed by Kara, C. GONZALEZ et al., grooves are simply formed parallel to a certain direction, and there is a problem in that the usable area of the side wall surface is small.

Note that methods for forming grooves on a silicon substrate include Japanese Patent Publication No. 58-12739, Japanese Patent Application Laid-open No. 58-98927,
Various methods are disclosed in Japanese Patent Laid-open No. 60-161617, DD-207-591, etc.

In view of the above-mentioned conventional technical content, the present invention has a wide groove side wall surface that can be used when forming an element on the surface of a substrate, and furthermore, the characteristics of the element on the groove side wall surface can be standardized, and manufacturing It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof that eliminate variations in device performance between lots in a process.

[Means for Solving the Problems] A semiconductor device according to a first aspect of the present invention includes a substrate having a main surface consisting of a (100) crystal plane, and the substrate has a plurality of mutually orthogonal lines on the main surface side. The first and second grooves are separated by the grooves, and the block portion has a side surface made of crystal planes 1100). Furthermore, the first invention includes a circuit element formed on the side surface of the block portion.

A semiconductor device according to a second aspect of the present invention includes a substrate having a main surface consisting of a +1001 crystal plane, and the substrate has a plurality of first and second grooves orthogonal to each other on the main surface side portion thereof, and It has a block portion having side surfaces consisting of crystal planes (1101) separated by (1101).Furthermore,
The second invention includes a circuit element formed on the side surface of the block portion.

A method for manufacturing a semiconductor device according to a third aspect of the present invention includes the step of detecting the position of an orientation flat of a wafer having an orientation flat, and forming a groove so as to increase the side surface of the groove by +100% based on the position of the detected orientation flat. The method includes the steps of forming grooves in a predetermined pattern on the main surface of the wafer so that the crystal planes of the wafer are exposed, and forming circuit elements in the block portions defined by the grooves.

A method for manufacturing a semiconductor device according to a fourth aspect of the present invention includes the steps of: detecting the position of an orientation flat of a wafer having an orientation flat; and forming a groove as a side surface of the groove ( The method includes the steps of forming grooves in a predetermined pattern on the main surface of the wafer so that the crystal plane 1101 is exposed, and forming circuit elements in the block portions defined by the grooves.

A wafer for a semiconductor device according to a fifth aspect of the invention has a generally circular shape (
It includes a main surface consisting of a 1001 crystal plane and a generally cylindrical side surface, the side surface having an orientation flat consisting of a +1001 crystal plane.

[Function] In the first invention, the block portion has four sidewall surfaces made of T100I crystal planes. Therefore, when forming circuit elements on the side surfaces, operations such as film formation and ion implantation can be performed uniformly between each side surface. Therefore, the circuit elements formed on the side surfaces of the block portion can exhibit uniform characteristics. Additionally, since a plurality of first and second grooves that are perpendicular to each other are provided on the main surface side of the substrate, the area of the side surface that can be used for forming circuit elements is expanded compared to the case where only parallel grooves are provided. , the degree of device integration can be increased. Also, the side surface of the block part is (10
Since it is set to have a crystal plane of 0.01, circuit elements are always formed accurately and uniformly, and there is no difference in the characteristics of circuit elements between lofts.

In the second invention, since the block portion has a side surface made of a +110) crystal plane, a circuit element formed on the side surface has uniform characteristics between each side surface. In addition, since the side surfaces of the block portion are formed to have (110) crystal planes, standardized characteristics can always be obtained for circuit elements, and differences in circuit element characteristics between lofts can be avoided. There's nothing like it coming out. Moreover, since the block portion is formed by forming a plurality of first and second grooves that are perpendicular to each other, the usable area of the side surface is expanded compared to the case where parallel grooves are simply formed. The degree of integration of circuit elements on the top can be improved.

In the third invention, grooves are formed in a predetermined pattern on the main surface of the wafer, with the detected position of the orientation flat as a reference, so that the crystal plane of the floor appears as the side surface of the groove. This makes it possible to always accurately maintain the characteristics of the side surfaces of the grooves, and there are no differences between lots during the manufacturing process. Further, the characteristics of the circuit elements formed on the side surfaces of the groove can be made uniform.

In the fourth invention, grooves are formed in a predetermined pattern on the main surface of the wafer so that +110) crystal planes are exposed as side surfaces of the grooves based on the position of the detected orientation flat. As a result, the characteristics of the side surfaces of the grooves are always constant, and there are no differences between lots during the manufacturing process. Furthermore, uniform characteristics can be obtained for the circuit elements formed on the side surfaces of the groove.

In the fifth invention, the main surface has (1001 crystal planes,
The orientation flat has a flool crystal plane. Therefore, if a groove is formed parallel to, perpendicular to, or both parallel to and perpendicular to the orientation flat, the side surface of the formed groove will have a (100) crystal plane. That is, in the fifth invention, a groove having a uniform crystal plane can be formed by an easier forming method without forming the groove at an angle of 45° with respect to the orientation flat. By using this wafer and forming circuit elements on the sides of the grooves, it is possible to obtain circuit elements with homogeneous characteristics, and it is also possible to obtain semiconductor devices that do not differ between lots in the manufacturing process. It becomes like this.

[Example] For convenience of understanding, FIG. 1 showing a semiconductor device according to the present invention shows only one block portion 1, and also shows a state in which a protective film provided to cover the upper portion is removed. It shows.

In FIG. 1, the block portion 1 is formed in a generally rectangular parallelepiped shape, and the substrate main surface 2 constituting the upper end surface is +1
It is composed of 001 crystal planes. Further, the block portion 1 has four side surfaces 3 formed of f100+ crystal planes.

As is clear from FIG. 2, the block portion 1 is connected to the semiconductor substrate 4.
and are separated from each other by a first groove 5. The first groove 5 extends along the +1001 crystal plane of the substrate 4, thereby forming the side surface 3 of the block 1.
The structure is such that a +1001 crystal plane appears.

At the bottom of the first groove 5, an element isolation oxide film 6 is formed. A diffusion layer 7 having a conductivity type opposite to that of the semiconductor substrate 4 is provided on the side surface 3 of the block portion 1 . Furthermore, a thin oxide film 8 is formed on the side surface 3 so as to cover the diffusion layer 7 . Furthermore, a cell plate 9 made of polysilicon or the like is embedded in the first groove 5.

These diffusion layer 7, oxide film 8, and cell plate 9 constitute a capacitor.

A diffusion layer 10 having the same conductivity type as the diffusion layer 7 is formed at the center of the upper end of the block portion 1 .

The diffusion layer 10 is a diffusion layer 7 extending to the upper end of the block portion 1.
are spaced apart from the top of the Also,
The oxide film 8 extends to the upper end surface of the block portion 1 and also functions as a gate oxide film. A word line 11 serving as a gate electrode is arranged on the oxide film 8 extending to the upper end surface of the block portion 1 . Furthermore, a bit line 12 is in contact with the upper end of the central portion of the diffusion layer 10 . The word line 11 is a line extending substantially perpendicular to the plane of FIG. 2, and the bit line 12 is a line extending in the left-right direction of FIG. These diffusion layer 7, oxide film 8 and diffusion layer 1
0 constitutes a switching transistor. Note that a protective film 13 is formed to cover the above-mentioned components from above.

In the block part 1, a pair of grooves 15 are formed at the center of both left and right ends in FIG. 1, parallel to the first groove 5 and recessed toward the center of the block part 1.

As is clear from FIG. 3, an element isolation oxide film 16 is also formed on the bottom surface of the groove 15. The diffusion layer 7 and the oxide film 8 extend from the first groove 5 side to the upper end surface of the block portion 1 in the groove 1.
5 side, and further extends to the side surface 17 of the groove 15. Further, the cell plate 9 embedded in the first groove 5 extends on the oxide v48 along the upper surface of the block part 1,
Furthermore, it is embedded in the groove 15.

As shown in FIG. 1, a pair of local oxide films 18 are formed on the upper end surface of the block portion 1. As shown in FIG. Further, the element isolation oxide film 6 extends upwardly along the side surface 3 from the central portion of the block portion 1 in the left-right direction in FIG. ing. Further, the cell plate 9 is arranged so that it is not located closer to the center than the local oxide film 18 on the upper end surface side of the block portion 1.
It has a hole 19. As shown in FIG. 4, by providing the hole 19 in the cell plate 9, the cell plate 9 is separated from the switching transistor by the local oxide film 18.

Further, an element isolation oxide film 6 extending on the upper end surface of the block portion 1
A pair of switching transistors constituted by oxide film 8, word line 11, etc. are separated from each other by.

Furthermore, as shown in FIG. 4, the second groove 20 arranged between adjacent block parts 1 is a groove orthogonal to the first groove 5 (FIG. 2). Due to this second groove 20, a +1001 crystal plane appears on the side surface 3 of the block portion 1. Also in the second groove 20, the diffusion layer 7
, an oxide film 8 and a cell plate 9 are arranged to form a capacitor. Furthermore, an element isolation oxide film 21 is formed at the bottom of the second groove 20.

As is clear in FIG. 5, each block 1 has a first groove 5.
and are separated from each other by a second groove 20. Both grooves 5 and 20 are linear grooves that are orthogonal to each other. As a result, the side surfaces 3 of each block portion 1 facing one groove are arranged on the same plane. Further, as is clear from FIG. 5, the diffusion layer 7 and the oxide film 8 are separated by the element isolation oxide film 6 formed on the side surface 3. Further, within the groove 15, the local oxide film 18 extends on the end surface of the block portion 1 on the center side. This local oxide film 18 allows the diffusion layer 7 and the oxide film 8 disposed in the groove 15 to
are separated.

As is clear from the above description of FIGS. 1 to 5, in each block portion 1, four capacitors are formed at the four corners, and four switching transistors are formed at the upper center portion. There will be. In other words, a one-element memory cell type DRAM is constructed in which the grooved capacitor is used as an information charge storage region.

The operation of the embodiment shown in FIGS. 1 to 5 is the same as the general operation of a one-element memory cell type DRAM, and therefore will not be described here. In the above embodiment, the crystal plane (1001) appears on the side surface 3 of each block part 1, and
A (100) crystal plane also appears on the upper end surface. Therefore, each element formed on the side surface 3 and the upper end surface of the block portion 1 can be manufactured in a uniform state in the manufacturing process, so that uniform characteristics can be obtained. That is, high reliability can be expected from the semiconductor device according to the embodiment. Also, the side surface 3 of the block portion 1 is fl
Since it is configured so that the crystal plane of ool appears,
There is no problem that the properties of the obtained product differ between lofts.

Next, a method for manufacturing the semiconductor device according to the above embodiment will be explained.

First, as shown in FIG. 6, a generally disk-shaped wafer 30 is prepared. The wafer 30 has a main surface 2 having a (100) crystal plane and a side surface 31 that is generally cylindrical. Further, the wafer 30 has (10
0) Orientation flat 32 consisting of the crystal plane
have.

The wafer 30 is mounted on a wafer loader (not shown). The wafer 30 is transported on a transport belt of a wafer loader, and its back side is attracted onto a stage.

Then, the orientation flat 3 of the wafer 30 is detected by an orientation flat detection sensor (not shown).
2 positions are detected. Next, the wafer is rotated by a positioning roller, and the wafer is sucked and fixed in a predetermined position.

Through this process, the wafer 30 is fixed to the wafer loader so that the orientation flat 32 is always at a constant position.

Next, first groove 5 and second groove 20 are formed on main surface 2 of wafer 30. In addition, in FIG. 6, in order to facilitate understanding, the interval between the grooves 5 and 20 is enlarged and the number of valley grooves 5 and 20 is shown to be smaller than the actual number. The first grooves 5 formed in the main surface 2 are grooves that extend perpendicularly to the orientation flat 32 and are arranged parallel to each other and at equal intervals. As a result, the first groove 5
A crystal plane (1001) appears on the side surface of In this case, a crystal plane of (1001) appears.

As is clear from FIG. 7, which is a partial cross-sectional view taken along the line ■-■ in FIG. 6, each block portion 1 is formed into a rectangular parallelepiped shape surrounded by the first groove 5 and the second groove 20.

The step of forming the first groove 5 and the second groove 20 on the main surface 2 side of the Ueno\30 is performed as follows. The main surface 2 of the wafer 30 is flat as shown in FIG. 8A. An underlying oxide film 33 is formed on the main surface 2, as shown in FIG. 8B. Next, as shown in FIG. 8C, a nitride film 34 is formed on the underlying oxide film 33 by chemical vapor deposition (CVD). Furthermore, as shown in Figure 8D,
A high temperature oxide film 35 is deposited on the nitride film 34 in a furnace. Next, reactive ion etching (RIE)
Then, predetermined positions of the films 33, 34, and 35 are dry-etched to obtain the state shown in FIG. 8E.

Furthermore, the wafer 30 is etched by reactive ion etching.
Anisotropically etching the 0 body. As a result, a groove 5 (20) is formed in the sea urchin/X30, as shown in FIG. 8F. After the formation of the groove 5 (20) by etching is completed, the films 33, 34, and 35 formed on the wafer 30 are removed. As a result, the first groove 5 and the second groove 20 are formed in the main surface 2 side portion as shown in FIGS. 6 and 7.
A wafer 30 on which is formed is obtained.

Next, the main surface 2 of the wafer 30 shown in FIGS.
The process of forming circuit elements on the side will be explained.

FIG. 9A is a partial cross-sectional view taken along line IX-IX in FIG. 6.

Block portion 1 and groove 20 (in the state shown in FIG. 9A)
5) is subjected to field oxidation to form an element isolation oxide film 6.21 and a local oxide film 18 at the bottom of the groove 20(5) and at predetermined positions on the main surface 2, as shown in FIG. 9B. Next, as shown in FIG. 9C, oblique ion implantation is performed into the side surface 3 and main surface 2 of the block portion 1.
A diffusion layer 7 having a conductivity type opposite to that of the block portion 1 is formed.

Further, by forming an oxide film 8 on the side surface 3 and main surface 2 of the block portion 1, the structure shown in FIG. 9D is obtained. Furthermore, by providing a cell plate 9, providing a word line 11 and a bit line 12, and covering the entire structure with a protective film 13, the semiconductor device shown in FIGS. 1 to 5 can be obtained.

[Another Example] (a) In the above example, the first groove 5 and the second groove 20 were formed by linear grooves orthogonal to each other.
A configuration as shown in the figure can also be used.

In FIG. 10, the second grooves 20 are not connected in a straight line, and the formed block portions 1 are shifted by half a pitch in the arrangement direction with respect to the adjacent block portions 1. In the semiconductor device formed as a result, as shown in FIG. 11, each block portion 1 is arranged shifted by a half pitch.

(b) In the above embodiment, the first groove 5 and the second groove 20 were formed along the (1001) crystal plane;
The groove 5 and the second groove 20 may be formed along the (110) crystal plane. In this case, the side surface 3 of the block portion 1 separated by the grooves 5 and 20 is composed of 1io+ crystal planes.

In this case, the soil surface 2 is composed of (100) crystal planes, while the side surface 3 is composed of il 10) crystal planes. Therefore, from the viewpoint of uniformity, it is inferior to the block part 1 having side surfaces 3 made of +100) crystal planes, but since the characteristics are homogeneous between each side surface 3, it is uniform compared to the conventional one. It becomes possible to obtain a circuit element having standardized and uniform characteristics.

(c) In the above embodiment, the wafer 30 is (100
Although a wafer with an orientation flat 32 having a (110) crystal plane was used, a wafer 30 with an orientation flat 32 having a (110) crystal plane may also be used.

In this case, on the side surfaces of the first groove 5 and the second groove 20 (
In order to expose the crystal plane 100), as shown in FIG.
It is necessary to form the groove 5 and the second groove 20 at an angle of 45°. In addition, in the case of a configuration in which the (110) crystal plane is exposed on the side surface formed by the first groove 5 and the second groove 20, the first groove 5 is placed perpendicularly or parallel to the orientation flat 32. and a second full 20.

(d) As a wafer for a semiconductor device according to the present invention
- is not limited to the case in which the first groove and the second groove are formed in a perpendicular state, but also includes, for example, a case in which only the first groove is formed.

(e) In the embodiment described above, a case has been described in which a capacitor is formed on the side surface 3 portion of the block portion 1, but the circuit element formed on this portion is not limited thereto.

For example, various things such as transistors can be formed on the three side surfaces. (Special application No. 62-45640
(f) In the above embodiment, a semiconductor device constituting a DRAM has been described, but the present invention is not limited to this, and for example, a static RAM including an ECL RAM can be used.
It is also possible to apply the present invention to AM and the like. (T,
AWAYA other r5ns access time 64Kb E
CL RAMJ (IEEE INTERNATIONAL
NAL 5OLID-3TATE CIRCUIT
C0NFERENCE.

130-131, February 26, 1987)) (g
) In the above embodiment, a case was explained in which a silicon substrate was used, but the substrate is not limited to this, and GaAs, ZnP, etc.
The present invention can be similarly applied even when compound semiconductors such as the following are used.

(Effect of the invention) According to the semiconductor device and the manufacturing method thereof according to the present invention,
It is possible to obtain a semiconductor device in which the characteristics of circuit elements formed can be standardized and made uniform. Furthermore, according to the present invention, the manufacturing process is standardized and uniform, so
There are no differences in the characteristics of circuit elements between lots.

Furthermore, since the usable area of the side surfaces of the block portion is large and the characteristics of each side surface are uniform, it is possible to obtain a highly integrated semiconductor device with uniform element characteristics.

According to the wafer for a semiconductor device according to the present invention, a wafer suitable for obtaining a highly integrated semiconductor device with standardized and uniform circuit element characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a partially omitted perspective view of a semiconductor device according to the present invention. FIG. 2 is a partial cross-sectional view taken along the line -n in FIG. 1. FIG. 3 is a partial cross-sectional view taken along the line m--■ in FIG. 1. FIG. 4 is a partial cross-sectional view taken along line IV-IV in FIG. 1. Fifth
The figure is a partial cross-sectional view taken along the line ■-■ in FIG. FIG. 6 is a perspective view of a wafer according to the present invention. FIG. 7 is a partial perspective cross-sectional view taken along the line ■-■ in FIG. 6. FIGS. 88 to 8F are vertical cross-sectional partial views showing the manufacturing process for forming grooves. FIGS. 9A to 9D are vertical cross-sectional partial views corresponding to FIG. 4, showing manufacturing steps when forming a circuit element. FIG. 10 is a vertical cross-sectional perspective partial view corresponding to FIG. 7 showing another embodiment of the wafer. FIG. 11 is a partial cross-sectional view corresponding to FIG. 5 of a semiconductor device manufactured using the wafer of FIG. 10. FIG. 12 is a perspective view showing another example of a wafer that can be used to manufacture a semiconductor device according to the present invention. 1 is a block portion, 2 is a main surface, 3 is a side surface, 5 is a first groove, 6 is an element isolation oxide film, 7 is a diffusion layer, 8 is an oxide film, 9 is a cell plate, 10 is a diffusion film, 11 is a 12 is a bit line, 18 is a local oxide film, 20 is a second groove, 30 is a wafer, 31 is a side surface, and 32 is an orientation flat.

Claims (25)

[Claims] (1) A substrate having a main surface consisting of {100} crystal planes, the substrate having a plurality of first and second grooves perpendicular to each other and separated by the grooves on the main surface side portion. and a block portion having a side surface made of a {100} crystal plane, and further comprising a circuit element formed on a side surface of the block portion. (2) The circuit element includes a first conductor layer formed on a side surface of the block portion, an insulating film formed within the groove and on the first conductor layer, and an insulating film formed within the groove and on the first conductor layer. and a second conductor layer formed on the insulating film, the first and second conductor layers and the insulating film forming a capacitor. Semiconductor equipment. (3) The block part further includes isolation for dividing each side surface of the block part into two, thereby configuring four capacitors at the four corners of the block part. Semiconductor equipment. (4) The block portion further includes an active element consisting of first and second source/drain regions and a gate region on its main surface, and one of the first and second source/drain regions is The semiconductor device according to claim 3, wherein the semiconductor device is connected to the first conductor layer. (5) The number of the active elements is four, corresponding to the four capacitors, and one of the first and second source/drain regions of each active element is connected to the first conductor layer, respectively. The semiconductor device according to claim 4, which is connected. (6) A plurality of the block portions are provided, and the block portions are arranged to be shifted by half a pitch in the arrangement direction with respect to the adjacent block portions.
1. Semiconductor device described in Section 1. (7) A substrate having a main surface consisting of {100} crystal planes, the substrate having a plurality of first and second grooves perpendicular to each other and separated by the grooves on the main surface side portion. a block portion having a side surface made of a {110} crystal plane, and further comprising a circuit element formed on a side surface of the block portion. (8) The circuit element includes a first conductor layer formed on a side surface of the block portion, an insulating film formed within the groove and on the first conductor layer, and an insulating film formed within the groove and on the first conductor layer. and a second conductor layer formed on the insulating film, and the first and second conductor layers and the insulating film constitute a capacitor. Semiconductor equipment. (9) The block part further includes isolation for dividing each side surface of the block part into two, thereby configuring four capacitors at the four corners of the block part. Semiconductor equipment. (10) The block portion further includes an active element consisting of first and second source/drain regions and a gate region on its main surface, and one of the first and second source/drain regions is The semiconductor device according to claim 9, wherein the semiconductor device is connected to the first conductor layer. (11) The number of the active elements is four, corresponding to the four capacitors, and one of the first and second source/drain regions of each active element is connected to the first conductor layer, respectively. The semiconductor device according to claim 10, which is connected. (12) The semiconductor device according to claim 11, wherein a plurality of the block portions are provided, and the block portions are arranged so as to be shifted by half a pitch in the arrangement direction with respect to the adjacent block portions. (13) Detecting the position of the orientation flat of a wafer having an orientation flat, and using the detected position of the orientation flat as a reference, forming a groove so that a {100} crystal plane appears as a side surface of the groove. A method for manufacturing a semiconductor device, comprising the steps of forming grooves in a pattern on the main surface of a wafer, and forming circuit elements in block portions separated by the grooves. (14) The wafer has a main surface having a {100} crystal plane, the orientation flat has a {100} crystal plane, and the groove has a plurality of first grooves perpendicular to the orientation flat. Claim 13 comprising a groove and a plurality of second grooves parallel to the orientation flat.
A method for manufacturing a semiconductor device according to section 1. (15) The method of manufacturing a semiconductor device according to claim 14, wherein the circuit element is a capacitor. (16) The step of forming the groove includes: forming an insulating film on the main surface of the substrate; etching the insulating film on the substrate into a predetermined pattern for forming the groove; and exposing by the etching. 16. The method of manufacturing a semiconductor device according to claim 15, further comprising the step of etching the main surface of the substrate to form a groove. (17) The step of forming the insulating film includes forming an underlying oxide film on the main surface of the substrate, forming a nitride film on the underlying oxide film, and forming a high-temperature oxide film on the nitride film. 17. The method of manufacturing a semiconductor device according to claim 16, comprising the steps of: (18) The step of forming the circuit element includes forming an isolation region in the trench by field oxidation, doping side surfaces of the trench with impurities to form a first conductor layer, and forming a first conductor layer in the trench. 18. The method of manufacturing a semiconductor device according to claim 17, comprising: forming an insulating layer on the surface of the conductor layer; and forming a second conductor layer on the surface of the insulating layer. (19) The method of manufacturing a semiconductor device according to claim 18, wherein the impurity doping is performed by ion implantation. (20) The wafer has a main surface having a {110} crystal plane, the orientation flat has a {100} crystal plane, and the groove has a crystal plane of 4 with respect to the orientation flat.
Claim 19, comprising a plurality of first grooves having an angle of 5 degrees and a second groove having an angle of 45 degrees with respect to the orientation flat and perpendicular to the first grooves. A method for manufacturing a semiconductor device. (21) Detecting the position of the orientation flat of a wafer having an orientation flat, and forming a groove so that a {110} crystal plane appears as a side surface of the groove based on the position of the detected orientation flat. A method for manufacturing a semiconductor device, comprising the steps of forming grooves in a pattern on the main surface of a wafer, and forming circuit elements in block portions separated by the grooves. (22) The wafer has a main surface having a {110} crystal plane, the orientation flat has a {110} crystal plane, and the groove has a plurality of first grooves perpendicular to the orientation flat. Claim 21, comprising a groove and a plurality of second grooves parallel to the orientation flat.
A method for manufacturing a semiconductor device according to section 1. (23) The method of manufacturing a semiconductor device according to claim 22, wherein the circuit element is a capacitor. (24) A wafer for a semiconductor device, including a main surface made of a generally circular {100} crystal plane, and a generally cylindrical side surface, the side surface having an orientation flat made of a {100} crystal plane. . (25) The main surface includes a plurality of first grooves perpendicular to the orientation flat and a plurality of second grooves parallel to the orientation flat, and the first and second grooves are arranged on the side surfaces thereof. 25. The wafer for a semiconductor device according to claim 24, wherein the wafer has a crystal plane of {100}.