JPH01121791A - Electronic timepiece - Google Patents

Abstract

PURPOSE:To reduce the mean current consumption required to read logical fast/slow information in a normal mode by judging the normal mode or a pace measurement mode by a switch means and outputting a waveform corresponding to the mode. CONSTITUTION:The switch means 10 performs switching between the normal mode and pace measurement mode and 1st read waveform 71 and 2nd read waveform 72 outputted by a read waveform generating means 7 in the respective modes are outputted at different timing. Thus, logical fast/slow information is read in at a 10sec period in the rate measurement mode, but read in only once at a period longer than in the pace measurement mode or at the time of transition to the normal mode in the normal mode. Consequently, the mean current consumption required to read in the logical fast/slow information is reduced in the normal mode without decreasing noise resistance characteristics.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an electronic/child clock 9 with a logic adjustment terminal for rate adjustment. [Summary of the Invention] The present invention relates to a logic for rate adjustment. The timing for reading the logical speed information of an electronic watch with speed and speed terminals is changed every maximum time required for step-measurement (normally 10 seconds) when in rate measurement mode.
second period) and in normal mode.

The product is designed to reduce the average current consumption required to read the logical slowdown information in normal mode by making the reading cycle longer than when in rate measurement mode, and also to reduce the average current consumption required to read the logical slowdown information in normal mode than in rate measurement mode. By lengthening the read cycle, the power required for one read is increased and the noise resistance of the read is strengthened, without changing the average current consumption required to read logic information in normal mode. It is.

[Conventional technology]

The reading cycle of the logical adjustment information of a conventional electronic watch with a logical adjustment terminal is always constant regardless of the rate measurement mode or the normal mode, and most of it is the maximum time required for rate measurement (usually a 10 second cycle).

[Problem that the invention seeks to solve]

In the case of the conventional example, the operation of reading the logical slowdown information is carried out every maximum time required for rate measurement, regardless of the rate measurement mode or normal mode. In this case, even in the normal mode in which there is no need to read the rate logical slowdown information once it has been read, the reading operation is always performed every maximum time required for rate measurement, which is a wasteful process. In other words, even if reading operations are always performed every maximum time required for rate measurement in normal mode, the current consumption required for reading operations will affect the current consumption of the entire electronic watch. Reduces the current consumption required for read operations to the extent that
I needed to. This means that the noise resistance when reading the logical regulation information is degraded.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic timepiece that can reduce the average current consumption required for reading logical adjustment information in a normal mode and further improve noise resistance when reading logical adjustment information.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention includes a switch means for making it possible to distinguish between the normal mode and the rate measuring mode, and determining whether the mode is the normal mode or the rate measuring mode based on the state of the switch means or the operation of the switch means. A reading waveform creation means that outputs a reading waveform corresponding to that mode was set.

[Effect]

The audible switch means that makes it possible to distinguish between the normal mode and the rate measurement mode is constructed so that it can be turned on and off by operating the clock or a button switch. By operating the crown or button switch, it is possible to transition from the normal mode to the rate measuring mode or from the rate measuring mode to the normal mode. The mode transition operation is a preset operation and does not need to be specified in particular.Here, when the crown is pulled out, the switch means is set to ONL, which is the rate measurement mode, and when the crown is pushed in, the switch means is set to 0FFL, which is the normal mode. shall become.

The reading waveform creation means is turned on by the switch means.

In the 0 rate measurement mode, which outputs read waveforms at different timings depending on the OFF state, the first and second read waveforms are output at a cycle of 10 seconds, and in the normal mode, the first and second read waveforms are output at a cycle of, for example, 160 seconds. Output.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram illustrating the present invention. The first read waveform 71 and the second read waveform 72 outputted by the conventional read waveform creation means 7 have the maximum time required for rate measurement (
The period was usually 10 seconds). In the present invention, the normal mode and the rate measuring mode can be switched by the switch means, and the reading waveform generating means identifies the normal mode and the rate measuring mode and timings the first and second itching waveforms for each bald. The output is now different. The switch means can be set to O, N, 0, etc. by operating the button on the analog watch. FF' is possible, and digital watches can be turned on by operating buttons, bezels, pressure sensors, transparent electrodes, etc.
, so that it can be turned off.

The operation of the switch means for switching between the normal mode and the rate measurement mode is various. For example, when a digital watch is in a certain mode (time correction mode, etc.), if you hold down a certain button for more than 2 seconds, the mode changes to the rate measurement mode. Transition to normal mode is made by pressing a button once. Or again,
A state in which a plurality of switch means that are turned on and off by rotation of the bezel is in the ON/OFF state is defined as a rate measurement mode, and other states are defined as a normal mode. etc. are possible.

This time, as the simplest example, assume that when the crown is pulled out, the switch means is set to ONL, which is the rate measurement mode, and when the crown is pushed in, the switch means is set to 0FFL, which is set to the normal mode.

FIG. 2 is a circuit embodiment illustrating the present invention. The contents of the logic regulation terminal 9, the reading means 8, the logic regulation and acceleration information storage means 6, and the switch means 10 are specifically shown. The logic adjustment terminal 9 is a fuse that can select whether to connect the terminal of the C-MOS-IC to one power supply or to open it, a slide switch, and a pattern on the circuit board (opened by disconnecting it).

) etc. In some cases C-MOS-IC
This is also possible with a built-in fuse. In FIG. 2, the terminals of the IC are short-circuited to the + side power supply. The reading means 8 consists of N-channel transistors 81 and 82 capable of pulling down the logic adjustment terminal 9. Logical adjustment information storage means 6
is composed of latches 61 and 62.

The logical adjustment information is the first read waveform 71 as Hl and N
The second read waveform 72 is outputted at the timing when the channel transistors 81 and 82 are turned on and the logic slow/slow terminal is sufficiently pulled down, and is stored in the latches 61 and 62. It is assumed that the latches 61 and 62 store data at the falling edge of the second read waveform 72.

FIG. 3 is a circuit embodiment specifically showing the contents of the read waveform synthesis means 7. FIGS. 4 and 5 are time charts showing the first embodiment and the second embodiment.

In the first embodiment, in the normal mode, the logical speed information is read in every 160 seconds, and in the rate measurement mode, the reading operation is carried out in every 10 seconds. , READ14), and MS
Combine the K signals. The switch means 10 is turned on, and the signal 7
When 3 is outputting Hi, it is in rate measurement mode and the 1st
The second read waveforms 71 and 72 are output at a 10-second period like the READIO signal. On the other hand, switch means 1
When 0 is 0FFL and the signal 73 is outputting l and ay, the mode is normal, and the first and second read waveforms 71 and 72 are output at a period of 160 seconds like the MSK signal.

In the second embodiment, in the rate measurement mode, the logic m
The waveform synthesizing means 74 receives the signal from the frequency dividing means 2, and reads the sudden information, and in the normal mode, performs the reading operation only once only when transitioning from the rate measurement mode to the normal mode.
It synthesizes the CLOCK, READIOl and MSK signals, receives the signal 73 from the switch means 10, and generates the RESET signal 78 at the falling and rising edges of the signal 73.
is output and a part of the frequency dividing means is reset. RESET
The signal 78 and the MSK signal 77 are output only once at the falling and rising edges of the signal F3. As in the first embodiment, when the switch means 10 outputs ONI and the signal 73 outputs H4, The rate measurement mode is entered, and the first and second read waveforms 71 and 72 are output at a period of 10 seconds. The switch means IO is turned off, and the L signal 73 changes from Hi to l, o.
When it falls to w, the RESET signal is output, and at the same time the frequency dividing means is reset, the MSK signal is output only once, and the first and second read waveforms 71 and 72 are also MSK.
Like the signal, it is output only once.

According to the above embodiment, when in the rate measurement mode, the logical regulation information is read in a 10 second cycle, and in the normal mode, the logical regulation information is read at a longer cycle than in the rate measurement mode, or only once when transitioning to the normal mode. becomes possible.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the average current consumption required for reading logic regulation information in the normal mode without deteriorating the noise resistance characteristics. If you think about this in a different way, you can use
It has become possible to improve noise resistance. Furthermore, since the noise resistance characteristics are improved in the rate measurement mode, stable rate measurement is possible without being affected by noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the present invention, FIGS. 2 and 3 are circuit diagrams showing an embodiment of the invention, FIG. 4 is a time chart showing the first embodiment of the invention, and FIG. 5 is the second aspect of the present invention.
FIG. 3 is a time chart diagram showing an embodiment of the present invention. l...Crystal oscillation means, 2...Frequency dividing means 3...Driving means 4...Display means 5...Logical slowing/slowing information 6...Logical slowing/slowing information storage means 7...Reading waveform creation Means 8...Reading means 9...Logic slowing/fastening terminal 10...Switching means 71...First read waveform 72...Second read waveform 61, 62...Latch circuits 81, 82... ...Applicant for N-channel transistors and above Seiko Electronics Industries Co., Ltd.

Claims (1)

[Claims] Crystal oscillation means, frequency division means for creating a signal group of a lower frequency from the oscillation signal of the crystal oscillation means, and generating a drive signal by synthesizing the output signal group of the frequency division means. a driving means; a display means for displaying the time based on the output signal of the driving means; a logical slowing/fastening terminal for adjusting the rate which is the delay/advancement of the clock; and inputting a first read waveform to read the logical slowing/fastening terminal. a reading means for setting the enabled state; a logical adjustment/slowdown information storage means for inputting a second read waveform and reading and storing the state of the logical adjustment/slowdown terminal; a logical regulation means for changing the frequency division ratio of the frequency division means according to the logic regulation information; a first read waveform for inputting the output signal group of the frequency division means and reading the state of the logic regulation terminal; and a reading waveform creating means for outputting a second reading waveform, the rate measuring mode can be set by a switch means for setting the rate measuring mode, which is a specific mode for measuring rate. By inputting information as to whether the mode is a normal mode or a rate measurement mode, which is a mode other than the rate measurement mode, to the read waveform creation means, the first and second read waveforms in the normal mode can be set. The electronic timepiece is characterized in that the first and second read waveforms in the rate measurement mode are different, and the state of the logical adjustment terminal is read in the normal mode at a timing different from that in the rate measurement mode.