JP2597110B2 - Electronic clock - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to an electronic timepiece with a logical speed adjustment terminal for adjusting a rate.

[Summary of the Invention]

According to the present invention, the timing of reading the logical acceleration / deceleration information of an electronic timepiece having a logical acceleration / deceleration terminal for adjusting the rate is set to the maximum time required for the rate measurement (usually a period of 10 seconds) in the rate measurement mode, and the rate measurement is performed in the normal mode. To reduce the average current consumption required for reading the logical acceleration / deceleration information in the normal mode by making the read cycle longer than in the mode. Furthermore, in the normal mode, the read cycle is made longer than in the rate measurement mode, so that the average current consumption required for reading the logical acceleration / deceleration information in the normal mode does not change, and the power required for one read is reduced. This is to increase the readout noise characteristics.

[Conventional technology]

The reading cycle of the logic slow / fast information of the conventional electronic timepiece with logic slow / fast terminal is always constant irrespective of the rate measurement mode and the normal mode, and most of the time is the maximum time required for the rate measurement (usually a cycle of 10 seconds).

[Problems to be solved by the invention]

In the case of the conventional example, the reading operation of the logical acceleration / deceleration information is performed at every maximum time necessary for the rate measurement regardless of the rate measurement mode normal mode. In this case, even if the logic mode information is once read, even in the normal mode in which there is no need to read the information, the reading operation is always performed at every maximum time necessary for the rate measurement, which is wasteful. In other words, even if the reading operation is always performed at the maximum time required for the rate measurement in the normal mode, the reading operation is performed so that the current consumption required for the reading operation does not affect the current consumption of the entire electronic watch. It was necessary to reduce the required current consumption. This means that the noise characteristic at the time of reading the logical acceleration / deceleration information is reduced.

[Object of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an electronic timepiece that can reduce the average current consumption required for reading logical acceleration / deceleration information in the normal mode, and can further enhance the noise immunity characteristic when reading logical acceleration / deceleration information.

[Means for solving the problem]

In order to solve the above problems, in the present invention, the switch mode for enabling the normal mode and the rate measurement mode can be distinguished, the state of the switch means or the operation of the switch means to determine the normal mode or the rate measurement mode, A reading waveform creating means for outputting a reading waveform corresponding to the mode is set.

[Action]

The switch means for distinguishing between the normal mode and the rate measurement mode is configured to be turned on and off by operating a crown or a button switch of the timepiece. By operating the crown or button switch, the mode can be changed from the normal mode to the rate measurement mode or from the rate measurement mode to the normal mode. The operation of the mode transition does not need to be specified by a preset operation. Here, the switch means is turned on when the crown is pulled out, the rate measurement mode is set, and the switch means is turned off when the crown is pushed in.
Then, the normal mode is assumed.

The read waveform generating means outputs the read waveform at different timings depending on the ON / OFF state of the switch means. In the rate measurement mode, the first and second read waveforms are output every 10 seconds, and in the normal mode, for example, the first and second read waveforms are output every 160 seconds.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the present invention. Conventionally, the first read waveform 71 and the second read waveform 72 output from the read waveform generating means 7 have the maximum time (usually a period of 10 seconds) required for the rate measurement. According to the present invention, the normal mode and the rate measurement mode can be switched by the switch means, and the read waveform creating means distinguishes the normal mode and the rate measurement mode, and makes the timing of the first and second read waveforms different in each mode. Output. The switch means is configured so that it can be turned on and off by operating a crown or the like in an analog timepiece, and can be turned on or off by operating a button, bezel, pressure sensor, transparent electrode, etc. in a digital timepiece. To be configured.

The operation of the switch means for switching between the normal mode and the rate measurement mode is various. For example, in a certain mode of the digital clock (clock correction mode, etc.),
When the button is pressed for more than a second, the mode transits to the rate measurement mode, and the mode transits to the normal mode when any button is pressed once. Alternatively, a state where there is an ON / OFF state of a plurality of switch means which is turned ON / OFF by rotation of the bezel is set as a rate measurement mode, and other states are set as a normal mode. And so on. In this case, as the simplest example, it is assumed that the switch means is turned on with the crown pulled out, and the rate measurement mode is set, and the switch means is turned off with the crown pushed in, and the mode is set to the normal mode.

FIG. 2 is a circuit embodiment showing the present invention. The contents of the logical acceleration / deceleration terminal 9, the reading means 8, the logical acceleration / deceleration information storage means 6, and the switch means 10 are specifically shown. The logic control terminal 9 is a fuse, a slide switch, which can select whether the terminal of the C-MOS-IC is connected to one power supply or opened.
It is composed of a pattern (opened by cutting) on a circuit board. In some cases, a fuse built in the C-MOS-IC can be used. In FIG. 2, the terminal of the IC is short-circuited to the + side power supply. The reading means 8 comprises N-channel transistors 81 and 82 capable of pulling down the logic speed terminal 9.
It consists of. The logic speed information storage means 6 includes latches 61 and 62
It consists of. For the logical acceleration / deceleration information, refer to the first read waveform 71.
Set to Hi, turn on N-channel transistors 81 and 82,
At the timing when the logic regulation terminal is sufficiently pulled down, the second
Is output and stored in the latches 61 and 62. The latches 61 and 62 store data at the falling edge of the second read waveform 72.

FIG. 3 is a circuit embodiment specifically showing the contents of the read waveform generating means 7. FIG. 4 and FIG. 5 are time charts showing the first embodiment and the second embodiment.

In the first embodiment, the logical mode information is read every 160 seconds in the normal mode, and is read every 10 seconds in the rate measurement mode. The waveform synthesizing unit 74 receives the signal from the frequency dividing unit 2 and synthesizes the CLOCK, READ10, and ▲ ▼ signals. When the switch means 10 is turned ON and the signal 73 outputs Hi, the rate measurement mode is set, and the first and second read waveforms are set.
71 and 72 are output at a period of 10 seconds similarly to the READ10 signal. On the other hand, when the switch means 10 is turned off and the signal 73 is outputting Low, the normal mode is set, and the first and second read waveforms 71
And 72 are output in a 160 second cycle like the ▲ ▼ signal.

In the second embodiment, in the rate measurement mode, logical acceleration / deceleration information is read every 10 seconds, and in the normal mode, the read operation is performed only once when the mode is changed from the rate measurement mode to the normal mode. The waveform synthesizing means 74 receives the signal from the frequency dividing means 2 and
In addition to synthesizing the CLOCK, READ10 and ▲ ▼ signals, it receives the signal 73 from the switch means 10, outputs a RESET signal 78 at the falling and rising of the signal 73, and resets a part of the frequency dividing means. RESET signal 78 and ▲ ▼
The signal 77 is output only once when the signal 73 falls and rises. As in the embodiment of FIG. 1, the switch means 10 is turned on.
When the signal 73 outputs Hi, the rate measurement mode is set, and the first and second read waveforms 71 and 72 are output at a cycle of 10 seconds. The switch means 10 is turned off, and the signal 73 changes from Hi to L
When the signal falls to ow, a RESET signal is output, the frequency divider is reset, and at the same time, a signal is output only once, and the first and second read waveforms 71 and 72 are also output.
It is output only once like a signal.

According to the above-described embodiment, the logic acceleration / deceleration information is read at a period of 10 seconds in the rate measurement mode, and the logic acceleration / deceleration information is read only once in the normal mode in a longer cycle than in the rate measurement mode or when the mode transits to the normal mode. It becomes possible.

〔The invention's effect〕

According to the present invention, in the normal mode, it is possible to reduce the average current consumption required for reading the logical acceleration / deceleration information without deteriorating the noise resistance characteristics. In other words, it is possible to improve the noise resistance without increasing the average current consumption required for reading the logical acceleration / deceleration information in the normal mode. Furthermore, since the noise resistance is improved even in the rate measurement mode, stable rate measurement can be performed without being affected by noise.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the present invention, FIGS. 2 and 3 are circuit diagrams showing an embodiment of the present invention, FIG. 4 is a time chart showing the first embodiment of the present invention, and FIG. Is the second of the present invention.
It is a time chart figure which shows Example. DESCRIPTION OF SYMBOLS 1 ... Crystal oscillation means 2 ... Division means 3 ... Driving means 4 ... Display means 5 ... Logic slow / fast means 6 ... Logic slow / fast information storage means 7 ... Read waveform creation means 8 ... Read means 9 ... ... Logic logic terminal 10... Switch means 71... First read waveform 72... Second read waveform 61, 62... Latch circuit 81, 82.

Claims (1)

(57) [Claims] 1. A crystal oscillator, a frequency divider for generating a signal group having a lower frequency from an oscillation signal of the crystal oscillator, and a drive for generating a drive signal by combining an output signal group of the frequency divider. Means, display means for displaying the time in accordance with the output signal of the driving means, logic slow / fast terminal for adjusting the rate, which is the advance of the clock, and input of a first read waveform to read the logic slow / fast terminal Reading means for inputting a state of the logical read / write terminal, a logical read / write information storage means for reading and storing the state of the logical read / write terminal, inputting logical read / write information output from the logical read / write information storage means, Logic slowing / decreasing means for changing the frequency division ratio of the frequency dividing means in accordance with the slow / fast information, a first read waveform for inputting an output signal group of the frequency dividing means and reading a state of the logical slow / fast terminal, and 2 An electronic timepiece comprising a read waveform creating means for outputting a read waveform, wherein the rate measurement mode can be set by switch means for setting a rate measurement mode, which is a specific mode for measuring a rate, By inputting information on whether the mode is a normal mode or a rate measurement mode other than the rate measurement mode to the reading waveform creating means, the first and second read waveforms in the normal mode and the rate measurement mode are input. An electronic timepiece wherein the first and second read waveforms in a mode are different, and the state of the logical acceleration / deceleration terminal is read at a timing different from that of the rate measurement mode in the normal mode.