JPH01120045A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH01120045A JPH01120045A JP27578687A JP27578687A JPH01120045A JP H01120045 A JPH01120045 A JP H01120045A JP 27578687 A JP27578687 A JP 27578687A JP 27578687 A JP27578687 A JP 27578687A JP H01120045 A JPH01120045 A JP H01120045A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- input
- output
- lsi
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000003780 insertion Methods 0.000 claims abstract description 21
- 230000037431 insertion Effects 0.000 claims abstract description 21
- 239000000872 buffer Substances 0.000 claims abstract description 18
- 238000001514 detection method Methods 0.000 claims 1
- 230000006378 damage Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 101150046174 NIP2-1 gene Proteins 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路（以下、ＬＳＩと称す）Ｋ係
り、特にＬＳＩの端子配置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits (hereinafter referred to as LSIs), and particularly to the terminal arrangement of LSIs.
従来のＬＳＩは、そのパッケージの対向する２辺に端子
を配列したもの、４辺に端子を配列した−もの等１種々
の形態のものがあり、それらの端子のうちＫは電源端子
と接地端子とが含まれる。通常、ＬＳＩは回路基板上に
直接またはソケットを介して実装される。Conventional LSIs come in various forms, such as those with terminals arranged on two opposing sides of the package, and those with terminals arranged on four sides. Of these terminals, K is a power supply terminal and a ground terminal. and is included. Typically, LSIs are mounted directly on a circuit board or via a socket.
上記従来のＬＳＩは、物理的には１８０度あるいは９０
度回転させて回路基板に取付けることもできる構造とな
っているなめ誤挿入または誤実装する可能性があり、Ｌ
ＳＩと外部のシステムとの状況によっては、ＬＳＩに過
大電流が流れ、Ｉ・ＳＩ自。The above-mentioned conventional LSI is physically 180 degrees or 90 degrees
It has a structure that can be rotated once and attached to the circuit board.There is a possibility of incorrect insertion or mounting.
Depending on the situation between the SI and the external system, excessive current may flow through the LSI, causing the I/SI itself to overflow.
身の破壊あるいは、電源回路の破損や、システム側の半
導体の破壊を招くおそれがあった。There was a risk of personal injury, damage to the power supply circuit, or damage to the semiconductors on the system side.
また、従来のＬＳＩにおいて１例えば１日立マイクロコ
ンビ為−タデータブック（昭和６０年９月）第５２２頁
に記載されているように、１源（Ｖｏｃ ）端子および
接地（Ｖｓｓ ）端子を各々２本有しているものがある
が、逆に挿入し九場合には、ＬＳＩに正常な電流は供給
されず、このときのＬＳＩ外部の接続システムへの影響
については考慮されてなかった。In addition, in conventional LSIs, one source (Voc) terminal and one ground (Vss) terminal are each connected to two However, if the LSI is inserted in the opposite direction, normal current will not be supplied to the LSI, and no consideration has been given to the effect this would have on the external connection system of the LSI.
本発明は、Ｉ、ＳＩの誤挿入または誤実装に対しても、
システムへ損害を与えないＬＳＩを提供することＫある
。The present invention also prevents incorrect insertion or implementation of I and SI.
It is important to provide an LSI that does not cause damage to the system.
上記目的を達成するために１本発明は、複数の電源端子
および複数の接地端子を有する半導体集積回路において
。To achieve the above object, the present invention provides a semiconductor integrated circuit having a plurality of power supply terminals and a plurality of ground terminals.
上記複数の電源端子および上記複数の接地端子はそれぞ
れ点対称に配置され。The plurality of power supply terminals and the plurality of ground terminals are arranged point-symmetrically.
かつ、誤挿入検出用入力端子と。And an input terminal for detecting incorrect insertion.
該誤挿入検出用入力端子へ入力される信号に応じて、出
力をハイインピーダンスとするバッファ回路とを備える
ことを特欧とする。A special feature of the present invention is to include a buffer circuit that outputs high impedance according to the signal input to the input terminal for detecting erroneous insertion.
上記点対称とは、半導体集積回路を誤って回転した状態
で回路基板等に実装（挿入）したとしても、半導体集積
回路の電源端子には所定の電圧が印加され、かつ接地端
子には接地電位が印加されることを保証するものであれ
ばよい。The above-mentioned point symmetry means that even if a semiconductor integrated circuit is mounted (inserted) on a circuit board or the like while being rotated by mistake, a predetermined voltage will be applied to the power supply terminal of the semiconductor integrated circuit, and a ground potential will be applied to the ground terminal. It is sufficient as long as it guarantees that the voltage is applied.
本発明は、ＬＳＩの端子配置を誤挿入した場合にも、正
常な電源供給が行なわれるように定め。The present invention is designed to ensure normal power supply even if the LSI terminal arrangement is incorrectly inserted.
かつ、誤挿入かどうかを検出するための誤挿入検出用入
力端子を設け、この信号によりＬＳＩの出力状態を制御
するようにしたものである。Furthermore, an input terminal for detecting erroneous insertion is provided to detect whether or not there is an erroneous insertion, and the output state of the LSI is controlled by this signal.
本発明の半導体記憶装置を有効に機能させるためＫは、
誤挿入検出用入力端子が、正常時と誤挿入時で異なる電
位となるように予め配線しておく、。In order for the semiconductor memory device of the present invention to function effectively, K is:
The input terminal for detecting incorrect insertion is wired in advance so that it has different potentials during normal and incorrect insertion.
この入力端子の状態により、ＬＳＩの出力バッファ回路
をハイインピーダンスか、正常出力状態かを切換える。Depending on the state of this input terminal, the output buffer circuit of the LSI is switched between a high impedance state and a normal output state.
誤挿入時にハイインピーダンスとすることにより、外部
システムの出力とＬＳＩの出力が接続されても、ＬＳＩ
側の出力がハイインピーダンスとなるので問題ない。ま
た、入力と入力との接続、入力と出力との接続について
は、ＬＳＩやシステムを破壊する状態に至らないため、
特別の配慮は不要である。By setting high impedance when incorrectly inserted, even if the output of the external system and the output of the LSI are connected, the LSI
There is no problem because the side output becomes high impedance. In addition, regarding the connections between inputs and inputs, and between inputs and outputs, please ensure that the connections between inputs and outputs do not reach a state that will destroy the LSI or system.
No special consideration is required.
以下１本発明の一実施例を第１図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図はデエアル・イン・ライン・パッケージ（ＤＩＰ
型）のＬＳＩの上面図を示す。ＬＳＩ１のピン数は１本
実施例では２０ピンとなっている。Figure 1 shows the deal-in-line package (DIP).
FIG. The number of pins of the LSI 1 is 1, but in this embodiment there are 20 pins.
このＬＳＩ１の両側の端子に、ＩＥ源端子ｖ００゜接地
端子Ｖｓｓを第１図に示すように、ＬＳｌｌの中心点と
点対称をなす位置にそれぞれ配置する。As shown in FIG. 1, an IE source terminal v00° and a ground terminal Vss are arranged at both terminals of the LSI 1 at positions symmetrical to the center point of the LSII.
これにより、ＬＳｌｌの挿入方向を上下逆にしても、Ｌ
８１ｔの内部回路に対しては正常な電位が与えられるこ
とになる。さらに、ＬＳＩ１に逆挿入検出用入力端子で
ある５ＥＮＳＥ人力２を設け。As a result, even if the insertion direction of LSll is upside down, L
A normal potential is given to the internal circuit of 81t. Furthermore, LSI1 is provided with 5ENSE input terminal 2, which is an input terminal for detecting reverse insertion.
この８ＥＮＳＢ人力２と点対称の位置に、非接続端子Ｎ
Ｃ入力５を設ける。At a point symmetrical position with this 8ENSB manual power 2, there is a non-connection terminal N.
C input 5 is provided.
このようなＬｓｉＩＫ″ｘ源を接続した状態を第２図に
示す。Ｖｏｏには＋５ｖを与え、 Ｖｓｓは接地ｊ６゜
また、５ＥＮＳＫ人力２１Ｃ）−！、＋５Ｖ、ＮＣ入力
３は接地電位を与えるようにする。この電源状態におい
てＬＳｌｌを逆挿入した場合について考える。この時は
ＳＥＮＳｇ人力２が接地され。Figure 2 shows the state in which such an LsiIK''x source is connected.Voo is given +5V, Vss is grounded, and 5ENSK human power 21C)-!, +5V, NC input 3 is given a ground potential. Consider the case where LSll is reversely inserted in this power state.At this time, SENSg human power 2 is grounded.
ＮＣ入力３に＋５ｖが与えられることになり、正常挿入
時の電位とは異なった状態となる。+5v will be applied to the NC input 3, resulting in a state different from the potential at the time of normal insertion.
次に第３図により、ＬＳＩ１内部の動作を説叫する。Ｌ
ＳＩ１は入力バッファ４，５．内部回路６、出力バッフ
ァ７．より構成されている。Ｖｏｏ。Next, the internal operation of the LSI 1 will be explained using FIG. L
SI1 has input buffers 4, 5 . Internal circuit 6, output buffer 7. It is composed of Voo.
Ｋは＋５ｖが印加され、 ＶＳＳは接地される。入力端
子８は入力バッファ４を介して内部回路６に接。+5v is applied to K, and VSS is grounded. Input terminal 8 is connected to internal circuit 6 via input buffer 4.
続される。内部回路６の状態は出力バッファ７を通して
出力端子９に出力される。ＳＥＮ８ｇ人力２は入力バッ
ファ５を通して出力バッファ７のスリーステート制御を
行なうように接続する。またＮＣ入力３は内部未接続と
する。Continued. The state of internal circuit 6 is output to output terminal 9 through output buffer 7. SEN8g human power 2 is connected to perform three-state control of output buffer 7 through input buffer 5. Also, NC input 3 is not connected internally.
このような構成において、ＬＳｌｌが正常に挿入されて
いる場合は８ＥＮＳＥ入力に＋５ｖ即ちＨｉ ｇｈ
レベルが入力され、入力バッファ５を通して、出力バッ
ファ７のスリーステート制御端子全駆動し、内部回路６
の状態を出力端子９に出力するように制御する。一方、
逆挿入した場合は５ＥＮ８Ｅ入力２が接地されるように
なり、出力バッファ７は、ハイインピーダンス状態にな
るように一御される。従って出力端子９からは出力信号
は発生せずに、外部システムとの信号衝突などが防止で
きる。In such a configuration, if the LSll is inserted normally, +5V, that is, High, is applied to the 8ENSE input.
level is input, all three-state control terminals of the output buffer 7 are driven through the input buffer 5, and the internal circuit 6
The state is controlled so as to be output to the output terminal 9. on the other hand,
In the case of reverse insertion, the 5EN8E input 2 is grounded, and the output buffer 7 is controlled to be in a high impedance state. Therefore, no output signal is generated from the output terminal 9, and signal collision with an external system can be prevented.
本実施例では８ＥＮＳｇ人力２を、左上の位置で示しで
あるが、これはＮＣ入力５と点対称の位置であればどこ
でもよいことは明ら、かである。また、ＮＣ入力３は、
内部未接続として示しているが、ＮＣ入力３を用いて５
ＥＮＳＫ人力２と同様の機能を行なってもよい。In this embodiment, the 8ENSg human power 2 is shown at the upper left position, but it is clear that this may be at any position as long as it is symmetrical with the NC input 5. Also, NC input 3 is
Although it is shown as not connected internally, it can be connected to 5 using NC input 3.
It may perform the same function as ENSK human power 2.
第４図には、４辺に端子を持つパッケージの場合にりい
て示す。各辺のピン数が同一で１辺の長さが等しければ
、誤挿入される場合はＳ通りあり。FIG. 4 shows the case of a package having terminals on four sides. If the number of pins on each side is the same and the length of each side is the same, there are S ways of incorrect insertion.
すべての誤挿入に対応するには第４図に示すように、各
辺に、電源、接地、５ＦｌｉＮ８ＢまたはＮＣ端子を設
けることにより１本発明の目的を達成できる。In order to cope with all incorrect insertions, one of the objects of the present invention can be achieved by providing a power supply, ground, 5FliN8B or NC terminal on each side as shown in FIG.
本発明によれば、ＬＳＩの誤抛入に対しこれを検出し、
かつＬＳＩからの出力信号をハイインピーダンス状態に
できるので、誤挿入の際にも、ＬＳＩ自身の破壊や、シ
ステムの破損を防止することができるという効果がある
。According to the present invention, it is possible to detect erroneous insertion of an LSI,
In addition, since the output signal from the LSI can be brought into a high impedance state, it is possible to prevent the LSI itself from being destroyed or the system from being damaged even in the event of erroneous insertion.
第１図は本発明の一実施例のＬＳＩの上面図。
第２図は電気接続図、第３図は本発明の一実′ｍ冊の回
路図、第４図は本発明の他の実施例のＬＳＩの上面図で
ある。
１ ・ＬＳｌ、２・５ＢＮ８Ｅ人カ、５−ＮＣ入力、６
・・・内部回路、７・・・出力バッファ、８・・・入力
。
９・・・出力。
１パ。FIG. 1 is a top view of an LSI according to an embodiment of the present invention. FIG. 2 is an electrical connection diagram, FIG. 3 is a circuit diagram of one embodiment of the present invention, and FIG. 4 is a top view of an LSI according to another embodiment of the present invention. 1 ・LSl, 2 ・5BN8E human power, 5-NC input, 6
...Internal circuit, 7...Output buffer, 8...Input. 9...Output. 1 pa.
Claims (1)
体集積回路において、 上記複数の電源端子および上記複数の接地端子はそれぞ
れ点対称に配置され、 かつ、誤挿入検出用入力端子と、 該誤挿入検出用入力端子へ入力される信号に応じて、出
力をハイインピーダンスとするバッファ回路とを備える ことを特徴とする半導体集積回路。[Claims] 1. In a semifluidic integrated circuit having a plurality of power supply terminals and a plurality of ground terminals, the plurality of power supply terminals and the plurality of ground terminals are arranged point-symmetrically, and for detecting incorrect insertion. 1. A semiconductor integrated circuit comprising: an input terminal; and a buffer circuit that outputs high impedance in accordance with a signal input to the erroneous insertion detection input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27578687A JPH01120045A (en) | 1987-11-02 | 1987-11-02 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27578687A JPH01120045A (en) | 1987-11-02 | 1987-11-02 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01120045A true JPH01120045A (en) | 1989-05-12 |
Family
ID=17560386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27578687A Pending JPH01120045A (en) | 1987-11-02 | 1987-11-02 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01120045A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6417718B1 (en) | 1999-12-22 | 2002-07-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device without limitation on insert orientation on board |
| US7915663B2 (en) | 2005-07-25 | 2011-03-29 | Spansion Llc | Fabrication and method of operation of multi-level memory cell on SOI substrate |
-
1987
- 1987-11-02 JP JP27578687A patent/JPH01120045A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6417718B1 (en) | 1999-12-22 | 2002-07-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device without limitation on insert orientation on board |
| US7915663B2 (en) | 2005-07-25 | 2011-03-29 | Spansion Llc | Fabrication and method of operation of multi-level memory cell on SOI substrate |
| US8369161B2 (en) | 2005-07-25 | 2013-02-05 | Spansion Llc | Semiconductor device and control method therefor |
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