JPH01120034A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve current driving capacity of a logic circuit and to make it possible to use a conventional wiring software by providing a cell region of which unit cell is formed by use of a complementary insulating gate effect transistor and by providing a wiring channel region having an additional field effective transistor in a part whereof. CONSTITUTION:A cell region 1 of which unit cell 3 is formed by use of a complementary insulating gate field effect transistor is provided to compose a gate array. Additional field effective transistors 4, 5 are provided in a part of a wiring channel region 2, alternately with the cell region 1 to make connection between unit cells 3. For instance, in the wiring channel region 2, an N channel MOS transistor 4 and a P channel MOS transistors 5a, 5b are additionally formed before a primary Al wiring layer 6 which is wired crosswise and a secondary Al wiring layer 7 which is formed lengthwise through an interlayer insulation film are provided. The transistor 5b is connected in paralleled to a transistor of the added side of the unit cell when the secondary Al wiring layer 7 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a complementary MIS structure forming a gate array.

[Conventional technology]

Conventionally, this type of gate array semiconductor device has been either a gate array device in which wiring channel regions for only wiring and cell regions for forming elements such as MoS transistors are arranged alternately, or a gate array device in which cell regions are arranged without gaps and wiring channel regions are arranged without gaps. Generally, gate array devices do not have any specific area from the beginning.

FIG. 3 is a plan view of a gate array device (chip) corresponding to the former for explaining a conventional example.

As shown in FIG. 3, the chip 21 includes a cell region 22 made of an N-type diffusion layer for forming semiconductor elements such as MOS transistors, a cell region 23 made of a similar P-type diffusion layer, and a cell region 23 made of a P-type diffusion layer for forming semiconductor elements such as MOS transistors. Wiring channel area 24
, has a buffer section 25 including peripheral circuits formed around these cell regions 22, 23 and channel region '24. Note that pads for external connection are omitted here. In such a chip 21, a cell region 22
．． 23 and the connection between the unit cells and the buffer section 25 are made using the wiring channel region 24.
It is done using.

FIG. 4 is a plan view of such a unit cell forming the cell area in FIG. 3.

As shown in FIG. 4, the unit cell 26 includes an N-type diffusion layer 22 and a gate 27 to form two N-channel MOS transistors, and a P-type diffusion layer 23 and a gate 27 to form two P-channel MOS transistors. was formed.

[Problem that the invention seeks to solve]

The former conventional gate array device described above has a drawback in that the effective width of the gate of the transistor is limited, so that the current driving ability decreases when the load is heavy. Also,
The latter gate array device (not shown) called Sea of Gates allows the necessary logic circuits to be formed freely, but has the disadvantage that wiring software is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that improves the current drive capability of such logic circuits and allows conventional wiring software to be used as is.

[Means for solving problems]

The semiconductor integrated circuit device of the present invention includes a cell region for forming a gate array by forming unit cells using complementary insulated gate field effect transistors, and a cell region for making connections between the unit cells. Wiring channel regions are arranged alternately and have additional field effect transistors formed in some of them.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a gate array device for explaining one embodiment of the present invention.

As shown in FIG. 1, in this gate array device, cell regions 1 in which unit cells 3 are lined up and wiring channel regions 2 are arranged alternately. A first Ae wiring layer 6 and a second Ae wiring layer 7 formed vertically via an interlayer insulating film.
N-channel MOS transistor 4 and P-channel MOS transistors 5a and 5b are additionally formed before providing. This additionally provided P channel M
The OS transistor 5b is connected in parallel to the added transistor in the unit cell 3 when forming the second Af wiring layer 7. In other words, this improves the current driving ability of the added transistor. However, as described above, the connections can be made without changing the conventional wiring. On the other hand, a transistor provided at a transistor on the unit cell 3 side that does not need to improve current drive capability, for example, an N-channel MOS transistor 4
The transistor 5a (P-channel MOS) is buried under the first Ae wiring layer 6 by sandwiching an interlayer insulating film therebetween.

FIG. 2 is an enlarged plan view of the cell region and wiring channel region in FIG. 1.

As shown in FIG. 2, the cell region 1 has an N-type diffusion layer 8 and a P-type diffusion N9 on the substrate, and a complementary insulated gate FET (MI 5-FET) is formed on these diffusion layers. A gate 10 is formed for this purpose. On the other hand, in the wiring channel region 2, the first Ae wiring layer 6 is formed at the same time as that in the cell region 1, and then the second Ae wiring layer 6 is formed. ! The wiring layer 7 is formed via the glabellar membrane. At this time, contacts 11 are provided at locations that need to be connected to the first Ae wiring layer 6. In this embodiment, this second At? Since the second AJ7 wiring layer 13 is formed simultaneously with the formation of the wiring layer 7, there is no need to change the conventional wiring 6.7, and the wiring software can be used as is.

Note that although FIG. 2 shows an enlarged view of the P-channel MOS transistor 5b and its surroundings in FIG. The AJ7 wiring layer 13 connects the gate 10 to each other, and also connects the drain and source regions, that is, the P-type diffusion layers 9 and 1.
By interconnecting the two, the current driving ability of the logic circuit in the unit cell is improved.

〔Effect of the invention〕

As explained above, in the semiconductor integrated circuit device of the present invention, an additional MOS transistor is provided in a part of the wiring channel region of the gate array S integrated circuit device in which the wiring channel region and the cell region are arranged alternately. This has the effect of improving the current drive capability of the desired logic circuit, and also enables wiring of the transistor without adding new restrictions to other wiring, so the wiring software can be used almost as usual. It has the effect of being able to use things.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a gate array device for explaining one embodiment of the present invention, FIG. 2 is an enlarged plan view of a cell region and wiring channel region in FIG. 1, and FIG. 3 is a conventional example. A plan view of the gate array device for explanation, FIG. 4 is a plan view of a unit cell forming the cell region in FIG. 3. 1... Cell area, 2... Wiring channel area, 3...
... Unit cell, 4... N-channel MOS transistor, 5a, 5b... P-channel MOS) transistor, 6... First aluminum wiring layer, 7.13... Second aluminum wiring layer, 8... N type diffusion layer, 9... P type diffusion layer, 10... Gate, 11... Contact, 12...
...P-type diffusion layer.

Claims (1)

[Claims] A cell region for forming a gate array by forming unit cells using complementary insulated gate field effect transistors, and a cell region arranged alternately with the cell region and added to a part for making connections between the unit cells, etc. 1. A semiconductor integrated circuit device comprising a wiring channel region in which a field effect transistor is formed.