JPH01119849A - Multi-processor system - Google Patents

Abstract

PURPOSE:To execute at a high speed the processing of serialization in a lock instruction accompanied with a serialization operation by providing a means for executing a block cancel to a data block of a buffer storage device of other instruction processor. CONSTITUTION:In a lock instruction accompanied with serialization from an instruction processor 1 or 2, when a storage controller 3 applies a lock, a block cancel means of the storage controller 3 sends a block cancel request to the other instruction processor 1 or 2. As a result, in the other instruction processor 1 or 2, a data block of a buffer storage device is cancelled, and also, to a main storage device 4, an access is inhibited by a lock control. In such a way, the lock instruction accompanied with serialization can be ended without waiting for the end of the store.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system, and particularly to a multiprocessor system that can process instructions at high speed that involve serialization operations to ensure the order of instructions. It is related to.

[Conventional technology]

Conventionally, in a multiprocessor system consisting of multiple processors, each processor shares data on the main memory for processing, so when a processor reads or writes shared data in the main memory, a lock is required. A control mechanism prohibits data access from other processors for a certain period of time, and reads and writes shared data.

For this type of lock control mechanism, for example, the time opening 51
-10704, No. 2 publication.

Rock like this! Examples of instructions that use the II control mechanism include, for example, M series processing units (M/EX mode)
(8080-2-093)
There is a compare and swap) instruction◎5th
The figure is a diagram explaining the O8 instruction. This C8 instruction 30
is R with three operands, as shown in Figure 5.
5 type of command. R1 and R3 in this C8 instruction 30 indicate the general purpose register (GR) number, and B2
indicates the pace register number, and B2 indicates the pace register (
B2) shows the displacement from the tail. The contents of pace register B2 and displacement D2 indicate the operand address in main memory 2.

An outline of the operation of the CS instruction will be explained. First, the content 31 (first operand) of the general-purpose register indicated by R1 is compared with the content 33 (second operand) on the main memory 4 at the address specified by pace register B2 and displacement D2. If the comparison results are equal, the contents 32 (third operand) of the general-purpose register indicated by R3 are stored at the corresponding address location (second operand) on the main storage device 4. Furthermore, if the comparison results are equal, the contents 32 (third operand) of the general-purpose register specified by R3 are loaded into the general-purpose register (first operand) specified by R1.

When this C8 instruction is executed by one instruction processor constituting a multiprocessor system, the instruction processor that processes the CS instruction selects the corresponding address on the main storage device 4 of the second operand in the operation of executing the CS instruction. Lock control is performed to prohibit access from other processors to the main memory device 4 from the start of reading data at the location until the predetermined data is stored in the corresponding address location on the main memory device 4 based on the comparison result. That is,
Processing of this C8 instruction is performed with a lock applied by the lock control mechanism. Further, the C8 instruction is a lock instruction that involves a serialization operation, and furthermore, the serialization operation is performed before and after the processing of this C8 instruction. This serialization operation is an operation to guarantee the order of instructions. In other words, when a serialization operation is performed, from the perspective of other instruction processors, in the flow of instruction execution processing, the next operation (fetch or store) is performed after all stores before serialization are completed. It is guaranteed that the process will be executed, and the process execution control operation is performed.

FIG. 6 is a diagram illustrating an operation in which such a CS instruction is executed by one instruction processor IP#O of the multiprocessor system. This will be explained with reference to FIG. When a C8 instruction is executed at IP#O of the instruction processor,
To lock and refer to data from main memory, I
P#O first issues a fetch with lock (LF) request to the storage controller (SC) that controls the main storage.

When the storage control device receives an LF request, it sets a lock address in a lock address array (LKA), reads out data from the main storage device, and sends it to IP#0. When IP#O receives data, it issues a store (ST) request, for example, after testing the data. When the storage control device receives the ST request, it performs a store operation in the main storage device, and then sends a block cancellation request to IP#1. When IP#1 receives a block cancellation request, it performs a cancellation operation for the block. After confirming the completion of the store operation, IP#O issues a lock release (RL) request and
Finish the command.

In this operation, as seen from the IP#1 side, the end point of the C8 instruction is the point C1 when the block cancel operation is performed. In other words, if a block in the data area to be rewritten by the C8 instruction exists in the buffer storage device of IP#1, the block in the buffer storage device in IP#1 will be rewritten until the block in the buffer storage device is canceled by a block cancellation request. , C8 instruction pre-execution data is read. In section A, data before execution of the C8 instruction can be read, and in section B, data after execution of the CS instruction can be read. Therefore, as seen from IP#1, the point in time when execution of the C8 instruction by IP#O ends is the point in time C1.

Therefore, in order to guarantee the serialization operation, IP#O starts executing the next instruction after seeing the completion of the store operation.

[Problem that the invention seeks to solve]

In this way, considering the serialization operation at the end of the C8 instruction, the next instruction must be executed after the store operation to the main memory device by the C8 instruction is completed. Therefore, the next instruction cannot be executed until the store data is written to main memory.
There was a problem that the completion of the O8 instruction was delayed.

The present invention has been made to solve the above problems.

An object of the present invention is to speed up serialization processing in lock instructions that involve serialization operations, such as C8 instructions.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

In order to achieve the second object, the present invention comprises a plurality of instruction processors, a storage control device, and a shared main storage device, and each instruction processor has a buffer storage device that holds data blocks in the main storage device. A multi-processor system each having a lock control mechanism that exclusively processes requests from each instruction processor, and block cancel means that issues a request to invalidate a data block in the buffer storage device, and a serialization operation. Processing of a lock instruction accompanied by is characterized in that, when locking is performed by the lock control mechanism, the block canceling means performs block cancellation of a data block in a buffer storage device of another instruction processor.

[Effect]

According to the above means, in order to process serialization for ensuring ordering of instructions at high speed, the lock control mechanism exclusively processes requests from each instruction processor, and when locking is performed by the lock control mechanism, Block canceling means is provided for block canceling data blocks in buffer storage devices of other instruction processors. When locking a loaf instruction that involves serialization, the block canceling means operates to send a block cancellation request to other instruction processors.

As a result of this operation, other instruction processors cancel the data block in the buffer storage device, and since access to the main memory is prohibited by lock control, other instruction processors are unable to perform lock control operations. The area of the main storage device cannot be referenced.

This makes it possible for lock instructions that involve serialization to finish without waiting for the store to finish.
Processing can be performed at high speed.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention. In Figure 1, 1 is the first
2 is a second instruction processor (IPI), 3 is a storage controller (SC), and 4 is a main memory (MS).

First instruction processor 1 and second instruction processor 2
is connected to the main storage device 4 via the storage control device 3,
A multiprocessor system is configured. Each instruction processor is composed of instruction execution units 1a and 2a and buffer storage control units (hereinafter abbreviated as BS control units) lb and 2b, and the BS control unit stores some data in the main memory. It has a buffer storage (BS) for storing a copy of the BS. The buffer storage device divides data into fixed units (hereinafter referred to as blocks), reads the data from the main storage device 4, and stores the data in the main storage device 4.
I have a copy of the data. In each instruction processor, when the requested data does not exist in the buffer storage device, the data is transferred block by block from the main storage device 4 and stored in the buffer storage device.

FIG. 2 is a block diagram showing main parts of the configuration of the storage control device 8. As shown in FIG. This will be explained with reference to FIG.

A request from a first instruction processor (hereinafter abbreviated as IPO) is a command sent to a signal line 50 and a command sent to a signal line 51.
The address is sent out on the signal line 52, and the store data is sent out on the signal line 52. The command, address, and data of the request sent from the IPO are stored in the command stack 8. Address stack 9, store data stack 1
Stacked at 0.

Similarly, in response to a request from the second instruction processor (hereinafter abbreviated as IFl), commands, addresses, and data from the riffnis 1 to 11 are sent to the command stack 11. Address stack 12° is stacked on store data stack 13. Command stack 8, 1 that stacks request commands from IPO and IPI
The contents of 1 are stored in the command register 14 via the priority circuit 21. address stack 9,1
2 is stored in the address register 15.18 via the priority circuit 22. Address register 18 is used for addressing main memory 4 . The contents of the store data stack 10.11 are stored in the store data register 16 via the priority circuit 23. Lock address array (LKA) 17 is a register that holds lock addresses. A register is provided corresponding to each instruction processor (IPO, IPI) to hold its lock address, and the contents of the address register 15 are set. The contents of this lock address array 17 are compared with the contents of the address register 15 by a comparison circuit 19 under the control of the storage control section 25.
Detect whether a lock area has been accessed. This lock address array 17 and comparison circuit 19 are the parts that perform lock control. The storage control unit 25 uses the contents of the command register 14 and the output of the comparison circuit 19.

It controls the priority circuits 21, 22, 23, the command stacks 8, 11, the address stacks 9, 12, the store data stacks 10, 13, and also controls the lock address array 17. At the same time, the signal lines 64, 6
5, instructions are given to the block cancel control units 26 and 27 for IPO and IP1, respectively, as to whether or not to perform a block cancel operation. Furthermore, signal line 68.69
Store operations are reported to IPO and IPI respectively via . When the block cancellation control unit 26 for IPO receives a block cancellation instruction from the signal line 64, it uses the address stored in the address register 18 to cancel the data of the block on the buffer storage device (BS) including the address. In order to cancel, a block cancellation request is sent to the IPO via the signal line 66. Similarly, upon receiving a block cancel instruction from the signal line 67, the block cancel control unit 27 for IPI uses the address stored in the address register 18 to In order to cancel the block data, a block cancellation request is sent via the signal line 67.
Send to PI.

In addition, the main memory device 4 can read and write data at the address location according to the address stored in the address register 18, and can write the data content stored in the store data register 16, or write the data stored at the address location. It is possible to read out the contents of the main memory 4 to the read data register 20. The data read into the read data register 20 is transferred to the signal line 70.
．． 71, and are sent to IPO and IPI, respectively. In the explanation of this example, in order to make it easier to understand, the unit (block) of transfer of read data to the instruction processor (IPO, IPI) is assumed to be a unit that can be read from the main memory device 4 in one go. The size of the memory that needs to be read multiple times from the storage device 4 may be one block. In this case, data transfer to the instruction processor will be performed multiple times.

Next, the operation of the storage control device configured as described above will be explained. FIG. 3 is an explanatory diagram summarizing the operations of each request issued from the instruction processor to the storage control device. The commands sent from the instruction processor to the storage control device include at least fetch (F),
There are four commands: fetch with lock (LF), store (ST), and store and unlock (ST@RT, . . .).

First, the operation of fetch (F) will be explained.

For example, when the IPO issues a fetch (F) request, a command indicating the fetch (F) request is loaded into the command stack 8 and an address is loaded into the address stack 9.

When the request is accepted, the storage control unit 25 sends a control signal to the signal line 62 and at the same time captures the command from the command stack 8 into the command register 14.
The address is taken into the address register 15 from the address stack 9. At this time, I of the lock address array 17
If a lock address is not set in the register corresponding to the PI, the address is transferred to the address register 18, and the contents of the corresponding address in the main memory 4 are stored in the read data register 20 using the address. Thereafter, it is transferred to the IPO via the signal line 70. Further, at this time, if a lock address is set in the register corresponding to the IPI of the lock address array 17, the lock address of the lock address array 17 and the address stored in the address register 15 are compared.

If the comparison results match, it means that the area at the address in the main memory 4 that is about to be fetched is locked by the IPI, and the request from the IPO is sent to the command stack 8 that stacks IP○ requests. and is returned to the address stack 9, where it is held until the lock is released. If the address in lock address array 17 and the contents of address register 15 do not match, a read operation from main memory 4 is performed.

Next, the operation of fetch with lock (LF) will be explained. Regarding the fetch with lock (LF) request, when a request from IPO is accepted, the lock is placed in the register corresponding to the IPI in the lock address array 17, similar to the operation of the fetch (F) request described above. This is when the address is not set, or even if it is set, the addresses do not match. In this fetch with lock request, when a fetch with lock (LF) request from an IPO is accepted, the contents of the address register 15 are set in the register corresponding to the IPO in the lock address array 17 in order to apply a lock. Thereafter, the storage control section 25 issues a block cancellation request to the block cancellation control section 27 via the signal line 65. The block cancellation control unit 27
The block address data including the address (lock address) stored in the address register 18 is transferred to the IPI buffer storage device (
BS) issues a block cancellation request to be invalidated (cancelled). In response to this block cancellation request, the IPI invalidates the data of the block if the data of the corresponding block is registered in its own buffer storage device (BS). Therefore, after this operation, when the IPI attempts to read the data in the block, it will be read from the main storage device 4.
A fetch (F) request will be issued to the storage control device 3.

=16- Next, the operation of the store (ST) will be explained.

For example, when a store (ST) request is issued from the IPO, a command indicating the store request, an address to store, and store data are sent from the IPO, and the command stack 8, address stack 9.
and stored in the store data stack 10. This store request is accepted when the block in question is not locked by the IPI, similar to the fetch (F) request described above. When locked, the store request is made to wait in the stack that stores the request (command stack 8, address stack 9, store data stack 10) until the lock is released. When a store request is accepted, the address is taken into the address register 15.18 and the store data is taken into the store data register 16. Thereafter, the store data is written to the main storage device 4. At this time,
The storage control unit 25 issues a block cancellation instruction to the block cancellation control unit 27 for the IPI, and the block cancellation control unit 27 issues a block cancellation request to the IPI.

Finally, the store and unlock (ST@RL) operation will be explained. This store and unlock (ST@R
In the request L), the same operation as the store (ST) request described above is performed, and after writing of data to the main memory 4 is completed, the register of the lock address array of the instruction processor that issued the request is written. Contents (
lock address) and release the locked state.

Requests such as the F command, LF command, ST command, and ST@RL command are sent from the instruction processor to the storage control device, and, for example, a C8 instruction is executed. The operation when this C8 instruction is executed will be explained.

FIG. 4 is a diagram showing the flow of processing when a C8 instruction is executed in a multiprocessor system according to an embodiment of the present invention.

This will be explained with reference to FIG. When the CS instruction is executed by the IPO, the IPO issues a fetch with lock (LF) request to the storage controller (SC) in order to lock and refer to the data in the main storage device. The storage controller is
When an LF request is received, the lock address array (
After setting a lock address in LKA), a block cancellation request is sent to IPI. Next, the data is read from the main memory and sent to the IPO. When the engineering PO receives the data, it tests the data, stores the data according to the test results, and then unlocks the data. For this reason, store and unlock (ST
@RL) Issue a request. The storage controller is ST
When it receives the @RL request, it performs a store operation in the main memory, and when the store operation is completed, it releases the lock.

In the operation of this C8 instruction, from the perspective of IPI, I
When a lock is placed on the storage controller by a request from the PO, the block in the IPI's buffer storage is canceled. Therefore, in IPI, up to the C2 point, -19= can refer to the data before the execution of the C8 instruction.
After time 02, an IPI request that refers to the block must access the main memory. In this case, a fetch request is issued from the IPI to the storage control device, but since the area of the block in question is locked in the storage control device by the request from the IPO, it will have to wait until the C3 point when the lock is released. . In other words, from the perspective of the IPI, it is equivalent to the C8 instruction in the IPO having finished at time 02, and the IPO finishes the C8 instruction without seeing the end of the store and starts executing the next instruction. It will be possible.

As described above, according to this embodiment, the C8 instruction, which is a lock instruction that involves serialization, can be completed without seeing the end of the store, and serialization can be processed at high speed, allowing for processing of the next instruction. You can move quickly. Although the C8 instruction has been described in this embodiment, it can be similarly applied to all lock instructions that involve serialization.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, in a multiprocessor system, instructions that require serialization to ensure ordering of instructions can be processed at high speed, and the performance of the multiprocessor system is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention. FIG. 2 is a block diagram showing the main parts of the configuration of the storage control device. FIG. 3 is an explanatory diagram summarizing the operation of each request issued from the instruction processor to the storage control device. A diagram showing the flow of processing when a C8 instruction is executed in a multiprocessor system according to an embodiment of the invention, FIG. 5 is an explanatory diagram explaining the CS instruction, and FIG. FIG. 2 is a diagram showing the flow of processing operations when an O8 instruction is executed in a processor system. In the figure, 1, 2... Instruction processor, 3... Storage control device, 4... Main storage device, 8, 11... Command stack, 9, 12... Address stack, 10.13...
・Store data stack, 14... Command register, 15. 18... Address register, 16... Store data register, 17... Lock address array, 1
9...Comparison circuit, 20...Read data register, 25...Storage control section, 26.27...Block cancellation control section.

Claims (1)

[Claims] 1. In a multiprocessor system consisting of a plurality of instruction processors, a storage control device, and a shared main memory, each instruction processor having a buffer storage device for holding data blocks in the main memory, each instruction processor a lock control mechanism that exclusively processes requests from the instruction processor; and block cancel means that invalidates a data block in a buffer storage device of each instruction processor; A multiprocessor system characterized in that, when a lock is applied, the block cancellation means performs block cancellation of a data block in a buffer storage device of another instruction processor.