JPH011193A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to an improvement in a bit line selection decoder for selecting a bit line in a memory array thereof.

[Conventional technology]

FIG. 3 is a circuit diagram showing the configuration from a memory array to a sense amplifier in a ROM using an 0M08 circuit, which is an example of a conventional semiconductor memory device. Transistors Q1 are arranged in a plurality of columns (only one column is shown in FIG. 3), and a memory gate selection decode input X is applied to these gates. 2 is a bit line selection decoder for selecting a bit line of memory array 1;
A plurality of shunts formed by connecting a plurality of switching transistors Q2 made of channel MoS transistors in series are connected to each bit line of the memory array 1, that is, a train of each memory transistor Q1, and are connected to the gate of each switching transistor Q2. are given bit line selection decode inputs Y 1 , Y 2 , Y 2 , and Y2, respectively.

A sense amplifier 3 is a peripheral circuit of the memory array 1, and is composed of a P-channel MOS transistor Q3゜Q and N-channel MOS transistors Q, Q6゜Q7, and is connected to the bit line selection decoder 2 through a common bit 14. . On the output side of this sense amplifier 3, there is an N-channel MOS transistor Q8 and a P-channel MOS transistor Q8.
An inverter 5 consisting of a transistor Q9 is connected to the inverter 5, and is configured to output a sense amplifier output corresponding to the voltage level of the common bit line 4 via the inverter 5 based on a chip enable signal CE input to the sense amplifier 3. .

As is well known, in the case of a mask ROM, the threshold voltage vth of each memory transistor Q of the memory array 1 is set by selectively implanting ions into a desired one of the memory transistors Q1.
Further, in the case of EPROM and EEPROM, this is performed depending on whether or not electrons are injected into the memory transistor Q1. Furthermore, in order to simplify the manufacturing process, it is common for the MOS l-transistors constituting the peripheral circuits other than the memory transistor Q1 to have a common threshold voltage set for each channel type. In the case of a semiconductor memory device as well, an N-channel MO8t-transistor Q2 forming the bit line selection decoder 2 and an N-channel MOS transistor Q5 . Q6. Q7 is a common threshold voltage vth1. : is set so that only one N-channel injection is required.

A conventional semiconductor memory device is configured as described above, and bit line selection and decoding are performed manually Y1. Y1. Y2.

The switching transistor Q2 of the bit line selection decoder 2 is selectively turned on according to the signal level of Y2, and at this time, the bit line selection decode input Y1 (one memory IJ of the memory array 1, the drain of the transistor Q1) and the common bit The line 4 is electrically connected. For example, Y=
When Y2=L and Y1=Y2=H, the common bit line 4 is connected only to the bit line of the rightmost memory transistor Q1A in the memory array 1. On the other hand, an H" level gate voltage is selectively input to the gate of the memory transistor Q1 as a memory gate selection decode input X. Therefore, the threshold flffi voltage Vth of the selected memory transistor Q in the memory array 1 When A is lower than the above gate voltage, the memory transistor Q1A is turned on, and a discharge path is formed from the common bit line 4 to the ground.Conversely, the threshold voltage Vth of the selected memory transistor Q1A is the memory gate selection When the gate voltage is higher than the gate voltage applied as the decode input X, the memory transistor Q7A is turned off, and the connection between the common bit line 4 and the ground is cut off. 11 of the voltage on common bit line 4 respectively
The chip enable signal @CE corresponds to the “I Hl” level and the “I-1” level during operation.
During standby, the potential of the common bit line 4 is taken out as the sense amplifier output and outputted via the inverter 5.

[Problems to be solved by the invention] In the conventional semiconductor memory device, each MOS that constitutes the circuit from the memory array 1 to the sense amplifier 3 which is its peripheral circuit
Since the threshold voltage Vth of the transistor is set as described above, the memory transistor Q1 of the memory array 1
When the memory transistor Q1 is turned on and discharge is performed from the common bit line 4 to the ground, the load on the discharge path increases, causing a considerable delay in access time compared to when the memory transistor Q1 is turned off. .

For example, in the switching transistor Q2 of the bit line selection decoder 2, W/L = about 10 μm/2μ (where W is the channel width and L is the channel length), and the threshold voltage Vt
If h=0.5■, switching transistor 021
The on-resistance of one is approximately 750Ω. In the case of an M (mega) bit class human data storage device, the number of stages of the bit line selection decoder 2 increases significantly, so the above-mentioned access time delay becomes even larger. The arrangement of the memory transistor Q1 in the X and Y directions in the memory array 1 and the sense amplifier 3
Generally speaking, three to six stages of switching transistors Q2 are used in the bit line selection decoder 2 in an M (mega) bit class memory device, although this varies depending on the number of bit lines.

FIG. 4 shows the threshold voltage v, h=i in the switching transistor Q2 of the bit line selection decoder 2.

This is a waveform diagram of the sense amplifier output when the memory transistor Q1 of the memory array 1 switches from off to on when OV, on-resistance = 1.5 and Ω, and the leftmost waveform in the diagram is the waveform of the bit line selection decoder. The figure shows the case where the switching transistor Q2 in No. 2 has one stage, and as the number of stages increases one by one, the waveform sequentially shifts to the right. The origin of the time axis in the figure indicates the point in time when the memory transistor Q1 is turned on.

As is clear from the figure, switching transistor Q2
As the number of stages increases, the access time delays,
The L” level is also rising.

The waveform of the sense amplifier output rises to the "°L" level as follows. That is, since the voltage level of the common bit line 4 is determined by the resistance division between the resistance valve of the sense amplifier 3 and the resistance valve from the bit line selection decoder 2 to the memory array 1, when the memory transistor Q1 of the memory array 1 is turned on, , the greater the resistance of the tool line selection detector 2, the higher the voltage level of the common bit line 4 will be compared to ground. When the voltage level ("L" level) of the common bit line 4 rises in this way, the MOS transistors Q and Q of the sense amplifier 3
A backgate effect is applied to node A, and MOS transistor Q5 also turns on, causing the level of node A to drop.

Therefore, MOS transistor Q6. Q7 becomes difficult to turn on, and in particular, the resistance of MOS transistor Q7 increases, causing the "L" level of the sense amplifier output to rise.

When the L level of the sense amplifier output rises in this way, the inverter 5 at the next stage of the sense amplifier 3 raises the threshold for determining the L11 level, and prevents malfunctions due to process fluctuations or voltage fluctuations during use. We need to take measures to prevent this from happening.

To achieve this, it is sufficient to shift the input/output characteristics of the inverter 5 shown in FIG. 5 in the direction indicated by the arrow in the figure. As a result, the "L" level of the output rises again, and the operating speed is further delayed.

The present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor memory device which has a small access time delay even in the case of a large storage capacity and is capable of high-speed operation.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a bit line selection decoder formed by connecting a plurality of switching transistors in series and having a plurality of shunts for selecting bit lines of a memory array. and a peripheral circuit connected to the memory array via the bit line selection decoder, the threshold voltage of the switching transistor of the bit line selection decoder being higher than 0V and lower than the threshold voltage of the transistor of the peripheral circuit. This is the setting.

(Function) In this invention, since the threshold voltage of the switching transistor of the bit line selection decoder is set lower than the threshold voltage of the transistor of the peripheral circuit, their on-resistance becomes small, and the switching transistor of the bit line selection decoder Even in the case of the most compact memory device in which the number of stages increases, the load on the discharge path via the bit line selection decoder is reduced when the memory transistor of the memory array is on.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which a memory array 1. Bit line selection decoder 2° sense amplifier 3
．． Each circuit section of the inverter 5 and the connections and configurations between them are the same as those of a conventional semiconductor memory device.

In particular, in this semiconductor memory device, the threshold 1 direct voltage Vth of the switching transistor Q2 of the bit line selection decoder 2
is higher than Ov, which is the threshold voltage V of an N-channel MOS transistor used in peripheral circuits such as the sense amplifier 3.
It is set to a value lower than th. In the figure, * means
Switching transistor Q of bit line selection decoder 2
2 indicates the low threshold voltage Vth.

In this way, the threshold voltage th of the switching transistor Q2 of the bit line selection decoder 2 is set to
In order to set it lower than that of the transistor, one additional ion implantation step is required compared to the conventional case. In other words, the impurity (generally boron) ion implantation process includes the N channel implantation process of the switching transistor Q2 and the M of the peripheral circuit.
The N-channel implantation step for the OS transistor is performed separately, and the N-channel implantation for the switching transistor Q2 is performed with a small amount of implantation.

As described above, this semiconductor memory device has a threshold voltage Vth of the switching transistor Q2 of the bit line selection decoder 2.
is set lower than that of the N-channel MOS transistor in the peripheral circuit, so that the switching transistor Q2 in the bit line selection decoder 2 when the memory transistor Q1 of the memory array 1 is turned on and the common bit line 4 is discharged to the ground. The on-resistance of the conventional example (
Conventionally, the direct voltage V of the switching transistor Q2
th is generally 0.5 to 1. OV), and the load on the discharge path is reduced.

That is, for example, the threshold voltage Vth of the switching transistor Q2=1. In the conventional example of OV, its on-resistance is 1.
5 and Ω, whereas in this semiconductor memory device, the threshold voltage of the switching transistor Q2 is V, h=0.5V (7
), the sonoon resistance is o, 75Ω, threshold voltage Vth=
In the case of 0.2V, the on-resistance is 0.3Ω.

In order to reduce the on-resistance, the threshold voltage ■th of the switching transistor Q2 should be brought as close to Ov as possible, but if a leakage current occurs in the switching transistor Q2 when the gate voltage is OV, it will not be able to perform its switching function. Therefore, in consideration of such points, it is preferable to set the threshold voltage Vth to about 0.2 to 0.5V.

In FIG. 2, the switching transistor Q of the bit line selection decoder 2 has a threshold voltage v th=o.

4V, on-resistance = 0.6 and Ω, is a waveform diagram of the sense amplifier output when the memory transistor Q1 of the memory array 1 switches from off to on;
In the figure, the leftmost waveform is for the case where the switching transistor Q2 of the bit line selection decoder 2 is in one stage, and as the number of stages increases one by one, the waveform is sequentially shifted to the right. As is clear from the figure, the overall access time is faster than in the conventional example shown in FIG. This does not occur, and the L1 level of the sense amplifier output does not rise significantly.

In the above embodiment, the case of ROM was explained, but it goes without saying that similar effects can be obtained even when applied to RAM or other semiconductor memory devices.

〔Effect of the invention〕

As explained above, this invention lowers the threshold voltage of the switching transistor of the bit line selection decoder than the transistors of the peripheral circuit to reduce the on-resistance as much as possible and reduce the load on the discharge path from the bit line selection decoder to the ground. , the access time becomes faster, and high-speed operation becomes possible even in the case of a large-capacity semiconductor memory device in which the bit line selection decoder has multiple switching transistors. Furthermore, since the rise in the "L" level of the sense amplifier output is suppressed to a small level, it becomes easy to determine the ratio of the next stage circuit (for example, determining the W/L ratio between the load transistor Q8 and the driver transistor Q9 of the inverter 5). Sufficient margin can be provided for fluctuations and power supply voltage fluctuations.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing the sense amplifier output in the circuit, Fig. 3 is a circuit diagram showing a conventional semiconductor memory device, and Fig. 4 is the circuit. FIG. 5 is a waveform diagram showing the sense amplifier output in FIG. In the figure, 1 is a memory array, 2 is a pit line selection decoder, 3 is a sense amplifier, 4 is a common bit line, Ql is a memory transistor, Ql is a switching transistor,
05 to Q7 are N channel MOS transistors. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a bit line selection decoder formed by connecting a plurality of switching transistors in series and having a plurality of shunts for selecting bit lines of a memory array; and a bit line selection decoder connected to the memory array via the bit line selection decoder. In the semiconductor memory device equipped with a peripheral circuit, the threshold voltage of the switching transistor of the bit line selection decoder is set to 0V.
A semiconductor memory device characterized in that the threshold voltage is set higher than the threshold voltage of the transistor of the peripheral circuit and lower than the threshold voltage of the transistor of the peripheral circuit.