JPH01118930A - Computer system - Google Patents

Abstract

PURPOSE:To carry out a return instruction at a high speed by realizing the analysis of a register storing form needed for recovery of a register by reference to a stack control information register and without reading a stack frame of a memory. CONSTITUTION:The replacement control is applied to a stack control information register 32 so that the stack control information on the latest stack frame is always held by the register 32. Thus the register holding form needed for recovery of a register carried out with execution of a return instruction can be analyzed by a storing form analyzing part 33 before execution of the return instruction by reference to the register 32. As a result, the return instruction in particular is carried out at a high seed in a subroutine call state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention provides a computer system particularly suitable for save/return processing of register sets during subroutine calls.

(Prior Art) Generally, when subroutine calls are made in computer programming, register sets are saved (SAVE)/returned (RET) using a stack built on memory.
URN) II capability is required. This save/return function is set to Safe (SAVE) command/Return (RETU).
In a computer system realized by machine language instructions such as the RN) instruction, the register save format and the current stack pointer (old stack pointer) are saved along with the register set in the stack frame created in memory by the save instruction. A method is known in which the register set is restored by referring to this in the return instruction.

The details of this method are shown in FIG. 5, in which 15 general-purpose registers (GR) 22.
Taking as an example a computer system equipped with eight pace registers (SR) 23 and eight floating point registers (FR) 24, the register storage format shown in FIG.
This will be explained below with reference to the flowcharts a) and (b).

When a save instruction is executed, first, a register saving format as shown in FIG. 6 given as an operand of the save instruction is analyzed (step 81). Next, the stack pointer (
old SP) is referenced (step S2), and based on this reference result and the storage format analysis result in step S1, a stack frame 12 is created on the stack area 11 starting from the position pointed by the stack pointer (step S83). ~8
6). In the area starting from the start position of the stack frame 12, the contents of the register group (R1 to R2°81 to B2.F1 to F2) specified in the register saving format shown in FIG. 6 are saved in order, and the stack frame 12 In the subsequent area, tI1111 information (stack control information) consisting of (information indicating) a register storage format and a stack pointer (old SP) is stored. Finally, the stack pointer register 25 is set to the new stack pointer (new SP)
(step 87).

Next, when executing a return instruction, the stack pointer (rsP) indicated by the stack pointer register 25 is first referenced (step 511). Then, based on the new SP reference result, the old SP is stored in the CPU 20 from the stack frame 12.
P and the register storage format (stack control information consisting of such) are read out (step 512), and the register storage format is first analyzed (step 513). Next, CP
The old SP read in U 20 is referred to (step 51
4) Based on this reference result and the storage format analysis result in step 813, restore the contents of the register group (R1 to R2, 81 to B2.Fl to F2) stored in the stack frame 12 to the original registers. Register recovery processing (step 8)
15 to 511) are performed. The stack pointer register 25 is then updated to the old SP referenced in step 814 (step 818).

The save/return command execution process described above is performed by c p U
This is done by a microprogram control mechanism provided in 20.

Now, in recent years, there has been a demand for faster execution processing speed of the above save/return instructions. To do this, it is necessary to have dedicated hardware perform part of the processing. However, in the conventional computer system described above, for example, when executing a return instruction, the CPU
Read stack control information (old SP, storage format) in
Since register recovery is performed according to the stack control information read out in a timely manner, in other words, an algorithm is applied that waits for the readout from memory to complete before starting the next operation, so especially in computer systems that use the Vibration method, the hardware It is difficult to speed up the process, and it is difficult to speed up the process.
There was a problem in that the features of the Vibrine method could not be fully utilized.

(Problems to be Solved by the Invention) As described above, in conventional computer systems, when executing a return instruction during a subroutine call, stack control information stored in a stack frame created on memory is Since register recovery is performed according to the control information after reading the data within the register, it is difficult to implement a hardware circuit for analyzing the register storage format indicated by the control information, and it is difficult to increase the speed. .

The present invention has been made in view of the above-mentioned circumstances, and its object is to provide a computer system that can easily speed up the execution of return instructions, especially during subroutine calls.

[Structure of the Invention] (Means for Solving the Problems) The present invention retains a copy of stack control information stored in the latest stack frame created on memory, and reads/writes it by the microprogram IIJ m. 1! A stack control information register that can be read is provided, and when a save instruction is executed during a subroutine call, the contents of the stack control information register are updated with the stack structure information saved in the latest stack frame, and the contents of the stack pointer register are also updated. When updating and executing the return command,
The stack pointer in the stack control information held in the stack control information register is referenced, and the stack control information register is updated with the stack control information saved in the stack frame that precedes the stack frame pointed to by the stack pointer. It is something. This invention further includes:
The register storage format in the stack control information held in the stack control 211 information register is analyzed, and when a return instruction is executed, the register set is restored based on the analysis result.

(Operation) According to the above configuration, the latest stack control information is always held in the stack control information register, so by referring to this stack control information register, the register storage format required for register set recovery processing can be changed. It becomes possible to perform the analysis before executing the return instruction, which improves the execution speed of the return instruction, especially when calling a subroutine.

(Embodiment) FIG. 1 shows a block configuration of a computer system according to an embodiment of the present invention. Note that the same parts as in FIG. 5 are given the same reference numerals and detailed explanations are omitted. In Figure 1, 1
21 and 12J are stack frames created in the stack area 11 secured on the memory 10, and 30 is a CPU. CPU 30 has a register set 21 and a stack pointer register 25, similar to CP jJ 20 in FIG.

The CP LJ 30 further includes a microprogram controller 31 that controls the execution of machine language instructions using a microprogram, and a stack control unit 31 that controls the execution of machine language instructions using a microprogram, and a stack control unit 31 that controls the execution of machine language instructions, which is stored in the latest stack frame on the stack area 11 (stack frame 12j in the tXsI diagram). It has a stacked T11 information register 32 that holds a copy of information, and a storage format analysis section 33 that analyzes the register storage format in the stack control information held in the register 32. The analysis result of the storage format analysis section 33 is used for register recovery processing when the microprogram control section 31 executes a return instruction.

Next, the operation of the configuration shown in FIG. 1 will be explained by the flowchart shown in FIG. 2(a) showing the save instruction execution processing procedure, the flowchart showing the return instruction execution processing procedure in FIG.
The explanation will be given with appropriate reference to the data flow explanatory diagram when the save command is executed in the figure and the data flow explanatory diagram when the return command is executed in FIG.

First, when a save instruction is executed during a subroutine call, the microprogram control section 31 in the CPU 30 controls the same processing as steps 81 to S6 in the flowchart shown in FIG. 7(a).

That is, the register save format shown in FIG. 6 given as the operand of the save instruction is analyzed (step 821), and L.

After that, the stack pointer (old SP) set in the stack pointer register 25 is referenced (step 5).
22) Based on this reference result and the storage format analysis result in step 821, the latest stack frame 12k is created on the stack area 11, starting from the position pointed to by the stack pointer, as shown in FIG. Step 823
~826). In the area starting from the start position of this stack frame 12, the contents of the register group in the register set 21 specified by the register save format given by the save instruction are saved as shown by reference numeral A1 in FIG. , in the subsequent area (hatched area) of the stack frame 12, stack control information consisting of the register storage format (information indicating) and the stack pointer (old SP) is stored as shown by reference numeral A2 in FIG. has been done.

When the latest stack frame 12k in which the register group and stack control information are saved is created, the contents of the stack control information register 32 are changed to A3 in FIG.
As shown in (step 527), the stack control information is updated to the one stored in the latest stack frame 12k.

That is, the stack control information register 32 is updated with the latest stack control information. This updating operation can also be performed by a hardware circuit. When step 827 is completed, the stack pointer register 25 stores a new stack pointer (new S
P') (step 828).

Next, the operation when executing a return instruction will be explained.

First, a storage format analysis section 33 is connected to the stack control information register 32 . The storage format analysis unit 33 extracts information indicating the register storage format (in this case, the same information as the stack control information stored in the stack frame 12k) of the latest stack control information set in the stack control information register 32. ), the analysis is performed (step 831), and the register type to be saved (
Here, it is broken down into three types (general-purpose register 22, pace register 23, and floating-point register 24 shown in FIG. 5), register numbers, and the number of registers. This register save format analysis process is performed independently of the return instruction execution, that is, independent of the save instruction execution control operation of the microprogram control section 31. The analysis result of the register storage format is held in a register (not shown) in the storage format analysis section 33, for example, at the start of execution of a return instruction, and is supplied to the microprogram control section 31 via the same register. Therefore, when executing a return instruction, the microprogram control unit 31 can perform register recovery processing without requiring the conventional procedure of reading the register saving format from the stack frame and then performing register saving format analysis processing. It becomes possible to perform control.

Now, the execution of the return instruction is started by referring to the stack pointer (old SP) in the stack υ control information set in the stack control information register 32, as shown in step 832 in FIG. 2(b). be done. next,
Based on the old SP referenced in step 832, this old SP
The stack control information stored in the last area (hatched area) of the stack frame 12J preceding the stack frame 12k in the stack area 11 pointed to by is read into the CP Ll 30, and the contents of the stack control information register 32 are
As indicated by reference numeral B1 in FIG. 4, the stack control information is updated to the stack control information from the stack frame 12j (step 533).

When step 833 is completed, the old SP of step 832
Based on the reference result and the analysis result of the register storage format for the stack frame 12k supplied from the storage format analysis unit 33, the contents of the register group stored in the stack frame 12k in the stack area 11 pointed to by the old SP are determined. A register recovery process (steps 834 to 836) is performed to return the data to the register set 21 (original registers) as shown by reference numeral B2 in FIG. The raster storage format analysis, which is not necessary for this recovery process, is performed in the storage format analysis unit 33 before executing the return instruction as described above, and does not need to be performed during the execution of the return instruction, so the execution processing time of the return instruction is Shorten. In particular, in a pipelined computer system, the addresses on the memory 10 of the stack area 11 to be successively created can be pre-fetched, making it possible to further reduce the time.

When the register recovery process is completed, the stack pointer register 25 is updated to the old SP referenced in step 832 (step 537).

As described above, in this embodiment, in order to enable the storage format analysis unit 33 to analyze the register storage format necessary for register recovery processing by executing the return instruction, the stack control Update control of the information register 32 is performed so that the stack control information of the latest stack frame is always held in the information register 32. However, if the stack frame or stack pointer is changed due to a software request (separately from a subroutine call), it is difficult to retain the stack υ1111 information of the latest stack frame in the stack control information register 32. becomes. Therefore, here, a stack control information register operation instruction (master edict instruction) for operating the stack suppression information register is prepared, and the stack control information register 32 is updated by executing this instruction. ing.

In the above embodiment, the analysis of the register storage format necessary for register storage processing is performed by microprogram processing, but it is also possible to have the storage format analysis section 33 perform this analysis processing. Furthermore, in the embodiment described above, the case where the analysis of the register storage format necessary for register recovery processing is performed by the storage format analysis unit 33 before executing the return instruction is explained. If the register storage format is analyzed based on the stack υJt[l information of the stack frame of (that is, the register storage format is analyzed without reading the stack control information from the memory 10), ■Return Even if it is performed after the start of instruction execution, or even if analysis is performed by microprogram processing in a pipelined calculation-specific system (the address in the memory 10 of the stack area 11 to be continuously generated can be prefetched). (depending on the matter) I don't care.

However, in the above case (■), the degree of reduction in the return instruction large line processing time compared to the conventional example is smaller than that of the above embodiment,
In the case of ■, it becomes even smaller than ■.

[Effects of the Invention] As detailed above, according to the present invention, the analysis of the register saving format required for the register recovery processing performed during subroutine calls, especially when executing a return instruction, refers to the stack control information register. This allows the return instruction to be executed without the need for reading from the stack frame created in memory as in the past, making it easy to speed up the return instruction execution process, which is particularly effective in Vibration-based calculation systems. . Further, it is easy to implement the register storage analysis means in hardware, and in this case, it is possible to analyze the register storage format before executing the return instruction, so that the speed of the − layer can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a calculation system according to an embodiment of the present invention, FIG. 2 is a flowchart showing the save/return command execution procedure in the system of FIG. 1, and FIG.
Figure 4 is a diagram explaining the data flow when executing a save instruction, Figure 4 is a diagram explaining the data flow when executing a return instruction, Figure 5 is a block diagram showing a conventional example, and Figure 6 is a diagram explaining the register saving format. FIG. 7 is a flowchart showing a conventional save/return instruction execution procedure. 10...Memory, 11...Stack area, 12.1
2i to 12k... stack frame, 20.30...
・CPU 121...Register set, 25...Stack pointer register, 31...Microprogram control unit, 32...Stack control information register, 33.
...Storage format analysis section. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) Execute a save instruction when calling a subroutine,
The contents of the register set starting from the position indicated by the stack pointer set in the stack pointer register, the register save format specified by the above save instruction, and the stack control information having the above stack pointer at that time are saved in the memory. In a microprogram control computer system that generates a stack frame, executes a return instruction upon return, and performs register set recovery processing using the contents of the register set saved in the stack frame, the most recent one saved in the stack frame is A stack control information register that holds a copy of the above stack control information that is stored and can be read/written by microprogram control, and a stack control information register that stores the contents of the above stack control information register in the latest stack frame when the above save instruction is executed. a first updating means for updating the stack control information stored in the stack control information and updating the contents of the stack pointer register; a second updating means for referencing a pointer and updating the stack control information register with stack control information stored in a stack frame preceding the stack frame indicated by the pointer; a storage format analysis means for analyzing the register storage format in the stack control information; and a recovery means for performing the register set recovery processing based on the analysis result of the storage format analysis means when executing the return instruction. A computer system comprising: (2) The computer system according to claim 1, wherein the storage format analysis means analyzes the register storage format before executing the return instruction. (3) The computer system according to claim 1 or 2, further comprising stack control information register operating means for operating the stack control information register independently of subroutine calls.