JPH01118887A - Memory address generation control circuit - Google Patents

Abstract

PURPOSE: To reduce the burden to software by converting an address corresponding to a dot position to a desired address based on a set reference. CONSTITUTION: Values N and N-1 with which a memory address is updated by a certain extent are preliminarily set in registers 1 and 2, and outputs of registers 1 and 2 are connected to inputs A and B of a selector 3. A plotting start reference dot address signal and information generated from a dot address generation circuit 8 are added by an adder 12, and one of inputs A and B of the selector 3 is selected by the carry output as the addition result. A plotting start memory address is inputted to the input B of a selector 6, and the output is latched in a register 7 and is fed back to the input A of an adder 5. Hereafter, the plotting memory address is controlled by information outputted from a dot address generation circuit 8 and a control signal C. Thus, the burden to software is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory address generation control circuit used in a dot line drawing device.

〔overview〕

The present invention is capable of reducing the burden on software by converting the address corresponding to a dot position into a desired address based on a set standard in a typeface changing means for a character pattern of a dot drawing device. be.

[Conventional technology]

In the hardware circuit used in the conventional drawing memory address control circuit, the address can only be updated by a narrow amount of change based on a given drawing start memory address.

[Problem that the invention seeks to solve]

In such a conventional apparatus, since the drawing start dot position of the drawing pattern information is determined and controlled mainly by software control, it has the disadvantage of increasing the software load.

The present invention aims to eliminate such drawbacks and to provide a memory address generation control circuit in which the load on software is reduced.

[Means for solving problems]

The present invention provides a memory address generation control circuit that generates an address related to a memory that stores pixel information corresponding to the presence or absence of a dot in a character pattern drawn by repeating a plurality of dot lines at an address corresponding to the position of the dot. , a first register in which the first value for updating the address is preset, a second register in which the second value for updating the address is preset, and the drawing start point and dot position of one character pattern. The apparatus is characterized by comprising a calculation means for updating the address corresponding to the new dot position to the address corresponding to the new dot position based on the first and second values.

[Effect]

For example, assume that a character pattern stored in a memory that stores pixel information is given an address corresponding to the position of a dot to be drawn in Gothic font.

If this address is converted to a drawing start reference dot address to an address different from that for Gothic type, dots are drawn at different positions based on the pixel information. In the present invention, values to be updated are set in two registers, and address conversion is performed using these set values.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. The figure is a block configuration diagram showing the configuration of this embodiment.

First, the configuration of this embodiment will be explained based on the drawings. In this embodiment, register 1 inputs data from the data bus.
and 2, and selector 3 that selects the output of this register.
, an AND gate 4 that controls the input from the selector 3 with a control signal C, an adder 5 that inputs and adds the output of the AND gate 4, the output of the register 7, and an inverted signal of the control signal; A selector 6 that inputs output and data bus data, a register 7 that inputs the output of this selector 6, a counter 9, a dot address generation circuit 8 controlled by this counter 9, and a dot address generation circuit 8 that is controlled by this counter 9. An AND gate 10 that controls the output, a selector 11 that selects one of the drawing start reference dot address signal and the output of the adder 12, and a selector 3 that controls the result of adding the output of the selector 11 and the output of the AND gate 10. and an adder 12 that provides the signal as a signal.

Next, the operation of this embodiment will be explained based on the drawings. Values N and N-1 for updating the memory address by a certain amount are set in advance in each of registers 1 and 2. The outputs of registers 1 and 2 are connected to selector 30 inputs A and I. One of the inputs A and B of the selector 3 is selected by the carry output of the result of calculating the drawing start reference dot address signal and the information generated from the dot address generation circuit 8 in the adder 12. Further, the drawing start memory address is input to the selector 6's manual input B, the output thereof is latched to the register 7, and is fed back to the adder 50 manual input A. Thereafter, the data added to the human input A of the adder 5 by the control signal C will be "1" or rN-IJ or "N" which is the output from the AND gate 4, and the data will be added from the dot address generation circuit 8. The drawing memory address is controlled by the output information and control signal C.

〔Effect of the invention〕

As described above, the present invention has the effect of converting a Gothic character dot pattern into an italic character pattern by performing drawing control on a memory address controlled by a memory address generation control circuit.

Furthermore, there is an effect of reducing the load on software when controlling memory address generation.

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration of an embodiment of the present invention. 1.2.7...Register, 3.6.11...Selector, 4.10...And gate, 5.12...Adder,...Dot address generation circuit, 9... counter.

Claims (1)

[Claims] (1) In a memory address generation control circuit that generates an address related to a memory that stores pixel information corresponding to the presence or absence of a dot in a character pattern drawn by repeating multiple dot lines at an address corresponding to the position of the dot. , a first register in which the first value for updating the address is preset, a second register in which the second value for updating the address is preset, and the drawing starting point and dot position of one character pattern. 1. A memory address generation control circuit comprising: an arithmetic means for updating the address corresponding to a new dot position to an address corresponding to a new dot position based on the first and second values.