JPH01117580U - - Google Patents
Info
- Publication number
- JPH01117580U JPH01117580U JP1288088U JP1288088U JPH01117580U JP H01117580 U JPH01117580 U JP H01117580U JP 1288088 U JP1288088 U JP 1288088U JP 1288088 U JP1288088 U JP 1288088U JP H01117580 U JPH01117580 U JP H01117580U
- Authority
- JP
- Japan
- Prior art keywords
- array package
- pin grid
- grid array
- lands
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Description
第１図は本考案の実施例１を示す斜視図、第２
図は同拡大断面図、第３図は本考案の実施例２を
示す拡大断面図、第４図は従来例を示す斜視図で
ある。
１……ＰＧＡパツケージ半導体、１ａ……ピン
、２……検査用治具、３……回路基板、４……ソ
ケツト、２１……フレキシブルプリント基板、２
２……押え、２３……穴、２４……ランド、２５
……信号線、２６……プローブ接続端子、２７…
…反発力、２８……突起又はバンプ状導体。
Fig. 1 is a perspective view showing the first embodiment of the present invention; Fig. 2 is a perspective view showing the first embodiment of the present invention;
3 is an enlarged sectional view showing a second embodiment of the present invention, and FIG. 4 is a perspective view showing a conventional example. 1...PGA package semiconductor, 1a...pin, 2...inspection jig, 3...circuit board, 4...socket, 21...flexible printed circuit board, 2
2... Presser foot, 23... Hole, 24... Land, 25
...Signal line, 26...Probe connection terminal, 27...
...Repulsive force, 28...Protrusion or bump-shaped conductor.
Claims (1)
ピンに電気的に接触させるランド及び該ランドか
ら引き出された信号線を印刷したフレキシブルプ
リント基板と、該基板の裏面（ピン・グリツド・
アレイ・パツケージの装着面の反対側面）に設け
た弾力性のある押えとを有することを特徴とする
ピン・グリツド・アレイ・パツケージ半導体の検
査用治具。 Pin Grid Array Package A flexible printed circuit board with printed lands that electrically contact the pins of the semiconductor and signal lines drawn out from the lands, and the back side of the board (pin grid array package).
1. A jig for inspecting pin grid array package semiconductors, comprising a resilient presser provided on the opposite side of the mounting surface of the array package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1288088U JPH01117580U (en) | 1988-02-02 | 1988-02-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1288088U JPH01117580U (en) | 1988-02-02 | 1988-02-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01117580U true JPH01117580U (en) | 1989-08-08 |
Family
ID=31222715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1288088U Pending JPH01117580U (en) | 1988-02-02 | 1988-02-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01117580U (en) |
-
1988
- 1988-02-02 JP JP1288088U patent/JPH01117580U/ja active Pending
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