JPH01117469A - Scanning circuit - Google Patents

Abstract

PURPOSE:To attain high sensitivity and to obtain sufficient S/N by operating a switch means operating a set means of a preceding unit circuit by a scanning pulse by means of other drive pulse than the drive pulse. CONSTITUTION:Other drive pulses phic1, phic2 than drive pulses phih1, phih2 are inputted to apply ON/OFF control of transistors(TRs) M3, M4, M7, M8, M11, M12.... An optional scanning pulse is fed back to the unit circuit by two preceding stages to turn on TRs M5, M9, M13.... In such a circuit as above, TRs Q1, Q2... are provided to each feedback wire and the TRs Q1, Q2... are subject to ON/OFF control by the drive pulse phic1 (phic2). Thus, the scanning pulse is outputted duplicatedly timewise and the scanning pulse of duty ratio of 50% or over is obtained and excellent S/N and high sensitivity are attained even at a high speed operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scanning circuit in which a plurality of unit circuits are connected in multiple stages and sequentially outputs scanning pulses of two or more phases from the unit circuits in accordance with multiphase drive pulses.

[Prior art] FIG. 14 is a schematic circuit diagram of a conventional scanning circuit.

In this conventional example, unit circuits are connected in n stages, and scanning pulses φ11. φ21. φ12 fists are sequentially output.

In the first stage unit circuit, when the start pulse φhs is input, the transistor M1 is activated by the pulse φh2.
is made conductive, and the potential V(1) rises. Potential v(
Since 1) is the gate potential of the transistor M2, the transistor M2 exhibits a conductance corresponding to the potential V (1).

Subsequently, the pulse φh2 becomes the falling pulse φh.

When the voltage rises, the potential at the terminal opt begins to rise through the transistor M2. J of the potential of terminal OPI:lLt*
, Nfilc t to the gate of transistor M2, raising the potential V (1) by 2. Since the increase in the potential v(1) acts to increase the conductance of the transistor M2, the scanning pulse φ11 appears at the terminal opt without a voltage drop.

Further, the first pulse φ11 increases the potential v(2) of the second stage through the transistor M3. And pulse φ
When h2 rises, terminal O is connected through transistor M6.
A scanning pulse φ21 is output from P2.

At the same time, a pulse φh2 causes the transistor Ml to
turns on, lowering the potential V (1) to the reference potential. Further, by outputting the third stage scan pulse φ12, the transistor M5 is turned on, and the potential v(2) is returned to the reference potential.

In this way, scanning pulses can be sequentially output at the timing of pulses φh1 and φh2.

FIG. 15(A) is a circuit diagram showing an example of a signal reading device using a conventional scanning circuit, and FIG. 15(B) is a timing chart showing an example of its operation.

First, a sensor noise N and a sensor signal S including noise are applied P:iJA to capacitors Ct1 and ct2, respectively.

In this state, the scanning pulse φ11 becomes high level with a pulse width Tb, and the transistors Qtl and QSl are turned on. As a result, the sensor noise N accumulated in the capacitor CLl is read out to the output line 0UT1 via the bipolar transistor amplifier Q.

When the noise N is read out during the period Tc (<Tb), the scanning pulse φ11 is at a high level, the pulse φbc is at a high level, and the transistor Qbc is turned on. This resets capacitor Ct1 and the base of transistor Q.

Next, by scanning pulse φ21 and pulse φbc,
The sensor signal S stored in the capacitor ct2 is similarly read out to the output line 0UT2 during the period Tc.

In this way, the noise N and sensor signal S read from the output lines 0UT1 and 0UT2 are subjected to differential processing, and the noise S is removed from the sensor signal S.

At the same time, the output of the bipolar transistor Q is connected to the output line 0UTI via the ON resistance of the transistor QSI or QS2.
Or, since it is read out to 0UT2, feedback by the diffuse capacitor is suppressed and noise components are reduced.

[Problems to be Solved by the Invention] However, in the conventional example described above, as shown in FIG. 15(B), the effective period for reading out the accumulated signals of the capacitors Ctl and ct2 is Tc. This accumulated signal readout period Tc is a very short period obtained by subtracting the residual component reset period from the pulse width Tb of the scanning pulse.

For this reason, a signal readout device using a conventional scanning circuit cannot obtain a sufficient S/N ratio, making it difficult to achieve high sensitivity when used in an imaging device or the like.

[Means for Solving the Problems] A scanning circuit according to the present invention is a scanning circuit in which a plurality of intermediate circuits are connected and sequentially outputs scanning pulses of two or more phases from the unit circuit in accordance with a multiphase drive pulse. It has a setting means for setting the intermediate circuit to a constant state, and a switch means for operating the setting means of the preceding rljl times by the scanning pulse, and the switching means is operated by a driving pulse different from the driving pulse. It is characterized by being operated by.

[Function] With this arrangement, the scanning pulses can be outputted temporally overlappingly, and scanning pulses with a duty ratio of 50% or more can be obtained. For this reason, for example, when driving a signal readout system, the effective signal readout period can be made longer than in the past, and good S/N and high sensitivity can be achieved even in high-speed operation.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic circuit diagram of one embodiment of a scanning circuit according to the present invention. Note that transistors having the same or similar functions as those of the conventional example shown in FIG. 14 are given the same symbols.

In this embodiment, drive pulses φC1 and φC2 separate from drive pulses φh1 and φh2 are input, and transistors M3, M4, M7 . M8, Mll, M12-...0
Perform N10FF control.

Further, an arbitrary scanning pulse is fed back to the unit circuit two stages before each transistor M5. M9, M2S...
In a circuit that turns ON, transistors Ql, Q2, etc. are provided in each feedback wiring, and these transistors Ql, Q2, etc. are driven by a driving pulse φc1 or φC.
ON/OFF F ftJ is controlled by 2.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart for explaining the operation of this embodiment.

First, in the unit circuit of the previous stage, the start pulse φhs
is input, the transistor M1 is made conductive by the pulse φh1, and the voltage v1 increases. voltage v1
is the gate lv of the transistor M2, so the transistor M2 exhibits a conductance corresponding to the potential v1.

Subsequently, when the pulse φh1 falls and the pulse φh2 rises, the voltage v2 increases through the transistor M2, which is fed back to the gate of the transistor M2 through the capacitor IcI, thereby further increasing the voltage V1. As a result, the conductance of the transistor M2 further increases, and the pulse φh2 appears as I[voltage v2] without voltage drop.

In this state, a drive pulse φC2 with a narrow pulse width is input. As a result, the transistor M3 is turned on and the voltage 3 of the first stage position circuit is increased.

Subsequently, the drive pulse φh1 with a wide pulse width rises.

This causes voltage v4 to rise through transistor M6, further increasing voltage v3 through capacitor 1c2. Therefore, the pulse φh1 appears as it is as the voltage v4, which is output as the scanning pulse φ11.

At the same time, the pulse φh1 causes the transistor M1 to
is turned on, and the potential v1 drops to the reference potential.

While the voltage v4 is at a high level, the drive pulse φC,1 with a narrow pulse width rises, the transistor M7 of the first stage position circuit is turned on, and the voltage v5 of the second stage position circuit rises.

Then, when the drive pulse φh2 rises, the voltage v6 is increased by the transistor MIO and the capacitor lc3, and is output as the scan pulse φ21. At this point, since the transistor Ql of the feedback wiring is OFF, the transistor M5 remains OFF, and therefore the first stage voltage v3 is also at a high level, and the scanning pulse φ1
1 is also maintaining a high level.

Subsequently, when the drive pulse φh1 falls, the voltage V4
(Scanning pulse φ11) falls, and voltage v3 also falls.

Subsequently, when the drive pulse φC2 rises, the transistor Mll turns on and at the same time raises the voltage V7,
Transistor M8. Ql and M3 are turned ON.

By turning on the transistor M8, the voltage v4 becomes
(Reset to quasi-potential Vns.

Further, by turning on the transistor Ql, the scanning pulse φ21 turns on the transistor M5, and the voltage v3 becomes the ground potential. Furthermore, transistor M3 is O
By becoming N, the upper pressure (2) is also reset to the ground potential.

In this way, as shown in FIG.
At the timing of 1 and φh2, scanning pulses φ11 and φ
21, φ12, . . . are output sequentially while overlapping.

That is, it is possible to obtain a wide scanning pulse output with a duty ratio of 50% or more.

FIG. 3(A) is an evening/f timing chart for explaining the batch reset operation in this embodiment, and the 3rd IN (B
) is a timing chart for explaining the collective high level setting operation.

As shown in FIG.
In the case of 0 period 71, which is performed by simultaneously setting the drive pulses φc1 and φC2 to high level with ns set to low level, it is a batch reset during scanning pulse output, and in the case of period T2, it is performed at the time of scanning start. This is a batch reset.

Such a collective reset function is useful for an enlarged readout operation in an imaging device, which will be described later.

In addition, as shown in CB) in the figure, the high level set in the 0 period T4, which is performed by setting the reference voltage Vns to high level and driving pulses φC1 and φC2 to high level, sets φC2 to high level. When becomes high level, transistors M8, M2S, etc. are turned on, and scanning pulses φ11, φ12, . ...In the case of 0 period T5 when eφ1 n is set to high level, the scanning pulse φ
21, φ22...φ2n are set to high level.

Note that the period T3 indicates the case of the above-mentioned -.

FIG. 4 is a schematic circuit diagram of a signal readout system of an image sensor using this embodiment.

In this image sensor, the optical sensor cell S11. S12, 轡, are arranged in mXn areas. Further, these cells are sequentially selected row by row by a vertical scanning circuit (not shown), and a sensor signal S is outputted from each cell in the selected row. However, as will be described later, the sensor signal S includes a noise component N of each cell.

For example, when the first row is selected, the transistor Qb2 is turned on by the pulse φt2, and each cell S11"S1n
The sensor signal S is transferred to the capacitor ct2 by the read operation of
Accumulate in.

Subsequently, after resetting each cell S11''S1n, the transistor Qbx is turned on by a pulse φt1, and each cell is read out again, thereby accumulating the noise component N of each cell in the capacitor Cti.

In this way, the noise component N of each cell is accumulated in each capacitor Ctl, and the sensor signal N containing noise of each cell is accumulated in each capacitor ct2, and is read out to the output lines 0UT1 to 0UT4 according to the operation of this embodiment. The details will be explained below.

(Configuration of Signal Readout System) Capacitors Ctl and ct2 corresponding to each column of the area sensor are commonly connected to the base terminal of a buffer amplifier Q via transistors Qtt and Qt2, respectively. This base terminal is further grounded via a transistor Qbc, and a pulse φbc is commonly input to the gate electrode of the transistor Qbc.

A constant positive voltage is applied to the collector electrode of the buffer amplifier Q. In addition, the emitter electrode of the buffer amplifier Q is
Transistor Q when corresponding to odd numbered rows of area sensors
5t to the output line 0UTl, and the transistor QS2 to the output line 0UT2, and in the case corresponding to an even column, they are also connected to the output lines 0UT3 and 0UT4, respectively.

The output of the bipolar transistor Q is the transistor QSl
Or, by being read out to the output line via QS2, the current is limited by the ON resistance of transistor Qlu or QS2, as described later, and contributes to noise reduction. Effective.
゛Scanning pulse φ1 from the scanning circuit 1 of this embodiment
1 and φ21 are input to respective gate electrodes of transistors Qt1 and Qsl corresponding to the first and second columns of the area sensor.

Furthermore, the scanning pulse φ12 is input to each gate electrode of the transistors Qt2 and QS2 corresponding to the first column, and at the same time, the scanning pulse φ12 is input to the gate electrodes of the transistors Qt1 and Qst corresponding to the third column.
It is also input to each gate electrode. In addition, the scanning pulse φ22
are transistors Qt2 and QS2 corresponding to the second column.
At the same time, it is also input to each gate electrode of transistors Qtx, a, and Qst corresponding to the fourth column. Thereafter, scanning pulses φ13, φ23°, φ14, etc. are input in the same manner.

Output lines 0UTI to 0UT4 are each connected to transistors Ql to
Grounded via Qr+. A drive pulse φC2 is input to each gate electrode of transistors Qrz and Qr+, and a drive pulse φC1 is input to each gate electrode of transistors Qr2 and Qr3.

(Operation of Signal Readout System) FIG. 5A is an explanatory diagram of the operation of the signal readout system using this embodiment, and FIG. 5B is an explanatory diagram of the conventional operation as a comparative example.

When the scanning pulse φ11 with a wide pulse width is output from the scanning circuit l of this embodiment with the noise component N and the sensor signal S accumulated in the capacitors ct1 and ct2, respectively, the pulse width corresponding to the first column is output as described above. transistor Qt
1 and Qsi are turned ON.

As a result, the noise component N1 corresponding to the first column is read out to the output line OUT1 via the buffer amplifier Q (see the column of scanning pulse φ11 in FIG. 5(A)).

Subsequently, when the scanning pulse φ21 is output, the transistors Qt1 and QS1 corresponding to the second column are turned on. As a result, the noise component N2 is read out to the output line 0UT3 via the buffer amplifier Q (see the column for scanning pulse φ21).

Subsequently, when the scanning pulse φ12 is output, the sensor signal S1 is similarly read out to the output line 0UT2, and the noise component N3 is read out to the output line 0UTI. Similarly below,
As shown in FIG. 5(A), the sensor signal and the noise component are sequentially read out.

Note that the output lines 0UT1 and 0UT2 are reset at the timing of the drive pulse φC2 by the transistors Qrl and Q T 2 k,'-, and the output lines 0UT3 and 0UT4 are reset at the timing of the drive pulse φC1 by the transistors Qr+ and Qr+. will be reset.

Also, after each scanning pulse rises and a certain period of time elapses,
Pulse φbc rises and transistor Qbc turns on. This resets the capacitor Ct1 or ct2 corresponding to the column from which the signal was read.

For comparison, a conventional driving method is shown in FIG.
), the effective read period is becoming shorter.

The configuration of the signal readout system is not limited to the above image sensor, and there are various configurations.

FIGS. 6A to 6C are schematic circuit diagrams showing other configuration examples of the signal readout system, respectively.

The figure (A) shows a capacitor split output type, the figure (B) shows a bipolar transistor with a scan switch on the base side, and the figure (C) shows a bipolar transistor with a scan switch on the emitter side. Each item is shown.

As already mentioned, in the signal readout system using this embodiment, the output of the bipolar transistor amplifier Q is connected to the transistor Q.
It is read out to the output line OUT via the ON resistance of S1 or Q32. This ON resistance limits the output current,
Contributes to noise reduction. As current limiting methods, in addition to methods that use resistance or ON resistance of transistors,
There is also the J method, which reduces the rising edge of the scanning pulse.

FIGS. 7(A) to 7(C) are schematic configuration diagrams each showing the current limiting means.

FIG. 2A shows a method using the ONN resistance and r' of the transistor employed in the signal readout system.

Furthermore, as shown in FIG. 2B, the rise of the drive pulses φh1 and φh2 input to the scanning circuit 1 according to this embodiment may be relaxed using an RC time constant.

On the contrary, the time constant may become too large due to wiring resistance, parasitic capacitance, etc. within the IC. in this case,
As shown in FIG. 5C, a buffer circuit is provided after the protection circuit to lower the impedance, and then a resistor r'' and a capacitor C1 or C2 may be provided to match the design.

FIG. 8 is a schematic configuration diagram of an example of an imaging device using the above-mentioned imaging device, and FIG. 9 is an explanatory diagram of its operation.

In gS81m, the sensor 101 represents the image sensor shown in FIG.

Drive pulses of sensor 101 φhL, φh21, φC1,
φc2. φhs, φbc, etc. are supplied from the driver 102, and the driver 102 operates according to the clock from the clock generator 103.

As shown in FIG. 5(^), the output 1;j of the sensor 101
The noise component N from OUTl and 0UT3 is output &
The sensor signals S from aOUT2 and 0UT4 are delayed by one cycle from the corresponding noise components, and the scanning pulse φh1 is generated from aOUT2 and 0UT4, respectively.
and sequentially output at the timing of φh2.

Therefore, in order to remove the noise component Ni from any sensor signal Si, it is necessary to delay the noise component Ni by one cycle and perform differential processing on the two. For this purpose, a delay 'JADLl that delays the output lines 0UTl and 0UT3 by one period is connected to the output lines 0UTl and 0UT3.

Furthermore, the sensor signals and noise components of the odd numbered columns of the area sensor are transmitted from the output lines 0UT1 and 0UT2 to the output line 0UT2.
Even-numbered columns are output from UT3 and 0UT4, respectively.

Therefore, a delay device DL2 and a sample-and-hold circuit 104 are provided to restore the signals in the odd and even columns to their original arrangement.

The sample and hold circuit 104 is connected to the clock generator 103.
Terminal a or b is selected by the S/H pulse from .

As shown in FIG. 5, the output 10a of the delay device DL2 is the odd column sensor signal Sl', 83 from which noise components have been removed.
'..., and the output 10b is the even-numbered sequence of sensor signals S2', B4'... from which noise components have been removed. Therefore, the output 10c of the sample-and-hold circuit 104 is dot-sequentially outputted by the S/H pulse. The converted sensor signals s1', B2', B3' become fist...

The output 10c has high frequency components removed by a low-pass filter LPFI, and is further processed by a process circuit 105 to
It is converted into a V signal, etc.

In this embodiment, in order to supply scanning pulses with a wide pulse width, the current limiting means is used to reduce the sensor signal S with less noise.
and the noise component N can be read out. Therefore, with this imaging device, the noise component N is extracted from the sensor signal S.
The sensor signal S' from which is removed has a high S/N, and high sensitivity can be achieved.

:jSlo is a schematic circuit diagram showing a signal processing system in another imaging device, and FIG. 11 is an explanatory diagram of its operation.

In this signal processing system, the sensor signal S and the noise component N are separately converted into point-sequential signals by switches SW3 and SW2, respectively. Then, the output 10d of switch SW2 is delayed!
1DL1 performs phase matching (output 10d'),
It is subtracted from the point-sequential senna signal 10e and output as a sensor signal 10c from which noise components have been removed.

This signal processing system eliminates the need for one delay device compared to the one shown in FIG.

FIG. 12(A) is a schematic configuration diagram of an example of a color imaging device, and FIG. 12(B) is a schematic diagram showing an example of the arrangement of color filters.

The color sensor 201 has a configuration in which the present embodiment shown in FIG. 1 is provided on both sides of an area sensor, and has eight output lines 0UT1 to 0UT8.

Further, the arrangement shown in FIG. 3B is an example, and W indicates white, R indicates red, and B indicates blue.

From the output line 0UT2, the odd rows wl, w3, ---,
From 0UT4, even rows w2, w4...φ, 0UT
It is assumed that R1, R3@@-1 of the odd-numbered rows are outputted from OUT8, and B2, B4, . . . of the even-numbered rows are outputted from OUT8. The other output lines 0UT1.3.5 and 7 are respective noise components.

Noise components are removed from the sensor signals of each color by differential processing as described above, and wl and W2 are obtained as white signals, r as a red signal, and b as a blue signal, respectively.

The white signals wl and w2 are supplied to the sample and hold circuit 204.
is restored to the original array as described above, and the LPF
Color process circuit 205 as luminance signal Y through I
Enter.

Further, the adder 206 adds a coefficient to each of the red signal r and the green signal (2b to kl r+), and the adder 207 adds the white signals wl and W2 (
wl+w2), and the respective addition results are sent to subtracter 2
08 to form the green signal g.

The color signals r1g and b obtained in this way are respectively LPF2
The signal is input to the color processing circuit 205 as a color signal RGB along with the luminance signal Y, and is converted into a TV signal or the like.

Next, an example of application of the -closing Z function in this embodiment will be explained.

FIG. 13(A) is an explanatory diagram of enlarged reading, FIG. 13(B)
) is a schematic timing chart showing driving of the image sensor during enlarged readout.

When reading out the signal of part B of the image sensor 301 in an enlarged manner,
In horizontal scanning 302, unnecessary portions a and C must be removed within the horizontal blanking period.

First, during the horizontal blanking period, a start pulse φhs is input, and high-speed drive pulses φh1 and φh2 are input.
A scanning pulse synchronized with is output.

The signal of the unnecessary portion a is transferred at high speed during the period ta.

Subsequently, after the signal of the enlarged part is transferred at low speed during the effective period [b, - pulses φC1 and φC are applied to reset the signal.
2 rises at the same time, and the scanning circuit 1 is initialized. In other words, the unnecessary portion C1 is scanned without empty scanning of the scanning circuit 1.
can be removed. Therefore, in this case, the idle scanning period of the scanning circuit 1 is only the period ta, which is significantly shortened compared to the prior art.

[Effects of the Invention] As described above in detail, the scanning circuit according to the present invention can output scanning pulses temporally overlapping and obtain scanning pulses with a duty ratio of 50% or more. be able to. For this reason, for example, when driving a signal readout system, the effective signal readout period can be made longer than in the past, and good S/N and high sensitivity can be achieved even in high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a schematic circuit diagram of one embodiment of a scanning circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of this embodiment, and FIG. 3IN(B) is a timing chart for explaining the batch reset operation, and FIG. 4 is a timing chart for explaining the batch high level setting operation. A schematic circuit diagram; FIG. 5(A) is an explanatory diagram of the operation of the signal readout system using this embodiment; FIG. 5(B) is an explanatory diagram of the conventional operation as a comparative example. FIGS. 6(A) to (C) are schematic circuit diagrams showing other configuration examples of the signal readout system, and FIGS. 7(A) to (C) are schematic configuration diagrams showing current limiting means, respectively. , Figure 8 shows imaging using the above image sensor! A schematic configuration diagram of an example of the lt position, FIG. 9 is an explanatory diagram of the operation of the above-mentioned imaging device, FIG. 1θ is a schematic circuit diagram showing a signal processing system in another imaging device, and FIG. An explanatory diagram of the operation of the processing system. FIG. 12(^) is a schematic configuration diagram of an example of a color imaging device, FIG. 12(B) is a schematic diagram showing an example of the arrangement of color filters, and FIG. 13(A) is an explanation of enlarged readout. Fig. 13 (B
) is a schematic timing chart showing the driving of the image sensor during enlarged readout, FIG. 14 is a schematic circuit diagram of a conventional scanning circuit, and FIG. FIG. 15(B), a circuit diagram showing an example of the reading device, is a timing chart showing an example of its operation. Ml, M2~...Transistors C1, C2~...Capacitance Q0@Fist buffer amplifier Ql, Q2...Transistors (switch means) φh1
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Claims (1)

[Claims] (1) In a scanning circuit in which a plurality of unit circuits are connected and sequentially outputs scanning pulses of two or more phases from the unit circuit according to a multiphase drive pulse, a setting means for setting the unit circuit to a constant state, and the scanning pulse a switch means for operating the setting means of the preceding unit circuit, and the switch means is operated by a drive pulse different from the drive pulse.