JP2651168B2 - Photoelectric conversion device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device in which a plurality of photoelectric conversion elements are arranged in a matrix, and in particular, optical information stored in the photoelectric conversion elements is transmitted to a vertical signal line. The data is selectively read from both ends.

[Prior Art] FIG. 13 is a schematic circuit diagram of a conventional photoelectric conversion device.

In the figure, electrodes 100a of photoelectric conversion elements 100 arranged in a matrix are commonly connected to a horizontal signal line 101 for each row, and each horizontal signal line 101 is connected to an output terminal of a vertical scanning circuit 102. . Further, the electrode 100 of the photoelectric conversion element 100
“b” is commonly connected to the vertical signal lines 103 for each column, and each of the vertical signal lines 103 is commonly connected to the read signal line 105 via a horizontal scanning transistor 104 having a MOS structure. The gate electrode of each scanning transistor 104 is connected to each output terminal of the horizontal scanning circuit 106, and the scanning transistor 104 is sequentially turned on at the timing when the horizontal scanning pulse from each output terminal shifts. The optical information stored in the photoelectric conversion element of a certain horizontal signal line by this horizontal scanning is serially read out from the readout signal line 10.
5 is amplified by the amplifier 107 and output to the outside.

The MOS transistor 108 connected to the read signal line 105 is for clearing the signal line capacitance of the read signal line 105.

[Problems to be Solved by the Invention] In such a conventional technique, the level of an output signal may be reduced due to the capacitance of the read signal line. In particular, when the number of horizontal scanning transistors increases and the density increases, the capacity of the readout signal line also increases, and the signal level decreases significantly. In addition, when the frequency of the scanning pulse is increased with the increase in resolution, design restrictions are strict and the circuit structure is complicated.

For this reason, a method has been proposed in which the read signal line is divided and the vertical signal lines in the odd-numbered columns and the vertical signal lines in the even-numbered columns are connected to different read signal lines (JP-A-61-154366). . With this configuration, although the above problem is solved, the read signal line is uniquely determined by the photoelectric conversion elements in the odd-numbered columns and the photoelectric conversion elements in the even-numbered columns. There is a possibility that it becomes narrow. For example, when used as an image sensor of a monochrome camera, it is more advantageous in terms of characteristics and mounting to read out signals of the same horizontal signal line from the same readout signal line. Further, even when the readout signal line is used as an image pickup device of a color camera, it may be desired to change the readout signal line depending on the arrangement of the color separation filters.

Also, a method in which MOS transistors are provided at both ends of the same vertical signal line and connected to a read signal line (US Pat. No. 4,658,287)
In the present invention, one image sensor is used for both B / W and color, so that one end of the vertical signal line has an output signal line for B / W and the other end has Only an output signal line for color is provided.

[Means for Solving the Problems] The photoelectric conversion device according to the present invention has been made to solve such problems, and a plurality of photoelectric conversion devices arranged in a matrix on a plurality of horizontal signal lines and a plurality of vertical signal lines. A plurality of photoelectric conversion elements; a first photoelectric conversion element provided on a first end side of the vertical signal line and selectively storing photocharge information stored in the photoelectric conversion elements.
Accumulating means, a second accumulating means provided on a first end side of the vertical signal line for accumulating a residual signal after the refresh operation of the photoelectric conversion element, and an output of the photoelectric conversion element. First and second switch means respectively provided between the vertical signal line and the first and second storage means for selectively sequentially leading the first and second storage means; The first and second switches are connected via the first and second switch means.
A first difference processing unit for performing a difference process between the read signal and the residual signal stored in the storage unit, and a second end opposite to a first end of the vertical signal line, Third storage means for selectively storing the photocharge information stored in the conversion element, and a third storage means for storing the remaining signal after the refresh operation of the photoelectric conversion element, at the second end of the vertical signal line. A fourth storage means provided; and a vertical signal line and the third and fourth storage means for selectively sequentially leading an output of the photoelectric conversion element to the third and fourth storage means. And third and fourth switch means respectively provided between the third and fourth switch means, and the third and fourth switch means via the third and fourth switch means.
And a second difference processing unit that performs a difference process between the read signal and the residual signal stored in the storage unit.

[Operation] As described above, the optical information accumulated in the photoelectric conversion element is selectively output from both ends of the vertical signal line, so that the application range of the application can be expanded.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic circuit diagram showing one embodiment of the photoelectric conversion device according to the present invention.

As shown in FIG. 1, a photoelectric conversion device according to the present invention includes an imaging unit 1, a vertical scanning unit 2, and first and second horizontal scanning units 3.
And 4.

The imaging unit 1 includes horizontal signal lines HL1 to HLm and vertical signal lines VL
A plurality of photoelectric conversion elements C11 to Cmn are arranged in a matrix on 1 to VLn, and each photoelectric conversion element C11
To Cmn are read and driven by the horizontal signal lines HL1 to HLm for each row, and the accumulated optical information is transferred from the vertical signal lines VL1 to VLn to the first
And to the second horizontal scanning units 3 and 4. The read optical information is applied to the read signal lines AL1 to AL of the first horizontal scanning unit 3.
It is output to the outside through L4 and the read signal lines BL1 to BL4 of the second horizontal scanning section 4.

The configuration of the photoelectric conversion elements C11 to Cmn is described in Japanese Patent Application Laid-Open No. Sho 62-17150 filed by the present applicant (title of the invention: photoelectric conversion device).
However, each element is composed of a bipolar transistor Tr, a capacitor Cox and a MOS transistor Qc, and the base electrode of the transistor Tr is one electrode plate of the capacitor Cox. And the other electrode of the capacitor Cox and the transistor Qc connected to one main electrode of the transistor Qc, respectively.
Are connected to each other and the corresponding horizontal signal line HL
1 to HLm are connected for each row. The emitter electrode of the transistor Tr of each element is connected to the corresponding vertical signal line VL1.
To VLm for each column, and to the power supply Evc via transistors QA1 to QAn and QB1 to QBn.

The transistors Qc of each element are connected in series for each row, and the vertical signal line
The transistor Qc of the element connected to VL1 has the other main electrode connected to the power supply Ec, and the transistor Qc of the element connected to the vertical signal line VLn has a MOS transistor Qx whose gate electrode is connected to the horizontal signal line. To the power supply Ec.

The MOS transistors Qc and Qx are both p-channel type and normally-off type, and are turned on when the potential of the drive signal applied to the gate electrode via the horizontal signal line is a negative potential exceeding the threshold potential, Conversely, if the potential of the drive signal is the ground potential or the positive potential, the drive signal is turned off. In the off state, adjacent elements are electrically separated from each other, and there is no need to form an element region. Therefore, the structure is suitable for miniaturization and can easily cope with high resolution.

The vertical scanning section 2 includes a vertical scanning circuit 21 and a vertical buffer circuit 22, and FIG. 2 is a circuit diagram showing details thereof.

In the figure, a vertical scanning circuit 21 having a shift register configuration is shown.
Means that the output terminal of each stage is a vertical buffer circuit 22
The transistors Qv1 to Qv3 are connected to the gate electrodes of the transistors Qv1 to Qv3.
HL3, HL5,..., Each transistor Qv2 sequentially transfers the drive signal SV2 to horizontal signal lines HL2, HL4, HL6,..., And each transistor Qv3 sequentially transfers the drive signal SV3 to the horizontal signal lines HL3, HL5, HL7,. It is configured as follows.

In such a circuit configuration, the vertical scanning circuit 21 starts operation by a start pulse φVS, and outputs scanning pulses φ1, φ2,... Which sequentially become “1” in accordance with the two-phase driving pulses φV1 and φV2. Accordingly, for example, as shown in FIG.
1 and SV2 are applied to sequentially drive the horizontal signal lines HL1 and HL2, HL3 and HL4,..., And the drive signals SV2 and SV3 are applied to the even field Fe to apply the horizontal signal lines HL2 and HL3, H
By sequentially driving L4 and HL5,..., Two-line driving interlaced scanning is performed.

The first and second horizontal scanning units 3 and 4 are provided at both ends of the vertical signal lines VL1 to VLn and have the same configuration, and transfer signals on the vertical signal lines VL1 to VLn from two directions to the outside. It is configured to be selectively read.

The first horizontal scanning unit 3 determines the line capacitance of the horizontal scanning circuit 31 having a shift register configuration, the read circuits YA1 to YAn connected to the signal lines VL1 to VLn, the read signal lines AL1 to AL4, and the signal lines AL1 to AL4. It comprises a clear circuit 32 for clearing and an output circuit 33.

Further, the second horizontal scanning unit 4 includes a horizontal scanning circuit 41 having a shift register configuration, read circuits YB1 to YBn, and a read signal line BL.
1 to BL4, a clear circuit 42 and an output circuit 43.

FIG. 4 is a circuit diagram showing a part of the horizontal scanning section, and representatively shows the read circuits YA3 and YA4, the clear circuit 32 and the output circuit 33 of the first horizontal scanning section 3.

In the figure, vertical signal lines VL3 and VL4 are connected to transfer transistors Qh1 and Qh of read circuits YA3 and YA4, respectively.
The capacitors C1 and C2 are respectively connected to the storage capacitors C1 and C2 via h2, and the capacitors C1 and C2 are connected to the base electrode of the buffer amplifier Qh5 via the first scanning transistors Qh3 and Qh4, respectively. This buffer amplifier Qh5
Prevents the signal level from decreasing when the signals stored in the capacitors C1 and C2 are read out,
This is to enable high-speed scanning.

The buffer amplifier Qh5 has a base electrode grounded via a clearing transistor Qh6, and an emitter electrode connected to predetermined two signal lines AL1 to AL4 of the readout signal edges AL1 to AL4 via second scanning transistors Qh7 and Qh8. Connected to each other. In this case, the readout circuit of the odd-numbered column YA3
Transistors Qh7 and Qh8 are connected to signal lines AL1 and AL2, respectively, and transistors Qh7 and Qh8 of YA4, which is an even-numbered readout circuit, are connected to signal lines AL3 and AL4, respectively.

The read signal lines AL1 to AL4 are connected to the transistors QC1 to QC4 of the clear circuit 32 for clearing the line capacitance, respectively, and the signal lines AL1 and AL3 are connected to the transistors QC1 and QC3.
The signal lines AL2 and AL4 are connected to ground via
2 and connected to the power supply Er via QC4, respectively.

The signal lines AL1 to AL4 are connected to the output circuit 33, the signal lines AL1 and AL2 are connected to the differential amplifier OP1, and the signal lines AL3 and AL
4 are connected to the differential amplifier OP2, respectively. The output terminals of the differential amplifiers OP1 and OP2 are connected to the sampling pulse φSH
1 and φSH2 are connected to sample and hold circuits SH1 and SH2, respectively, which sample and hold the input signal.

FIG. 5 is a layout diagram of color separation filters arranged on the photoelectric conversion elements C11 to Cmn of the imaging unit 1, where W indicates a white transparent filter, B indicates a blue transmission filter, R indicates a red transmission filter, and odd-numbered rows. Filters W and R on the photoelectric conversion element of the eye
Are alternately arranged in these order, and filters B and W are alternately arranged on the even-numbered rows of photoelectric conversion elements in this order.

Next, the operation of the above-described photoelectric conversion device will be described with reference to the timing charts of FIGS. 6 and 7.

FIG. 6 is a timing chart showing an operation of reading out the optical information stored in the photoelectric conversion element to the horizontal scanning section during the horizontal blanking period HBLK.

First, when the driving pulses φv1 and φv2 are input to the vertical scanning circuit 21 in the odd field Fo, the scanning pulse φ1 rises, whereby the vertical buffer circuit 22 outputs the driving signals SV1 and SV2 to the horizontal signal lines HL1 and HL2, respectively.

Simultaneously with the rise of the pulse .phi.v1, the potential of the power supply Evc drops from the positive potential E _H to the negative potential E _L. At this time, since φvc is “1”, the transistors QA1 to QAn and QB1 to QBn are respectively turned on, and the emitter potentials of the photoelectric conversion elements C11 to Cmn are reduced.
Decreases to E _L. For this reason, each element irradiated with strong light is in a forward bias state, blooming is suppressed immediately before signal reading, and surplus charges are removed (period T1).

Then return the potential of the power supply Evc to E _H, and turning off transistor QA1~QAn and QB1~QBn by a pulse φVC to "0", reads the signal components from the vertical signal line VL1~VLn floated . That is, the drive signal SV
When 1 is set to a positive potential, the read operation of the elements C11 to C1n of the horizontal signal line HL1 is performed and the accumulated optical information is transferred to the vertical signal lines VL1 to VLn.
Read out. At the same time, the pulse φY1 is set to “1” to turn on the transfer transistors Qh1 of the read circuits YA1 to YAn of the horizontal scanning unit 3, and the read optical information is stored in the capacitors C1.
At this time, as is apparent from the arrangement of the color separation filters in FIG. 5, the capacitors C1 of the read circuits YA1, YA3, YA5,. , YA4, YA6,... Store a red signal component (period T2).

Next, while the drive signal SV1 is maintained at a positive potential,
Lower the vc to the potential E _L, to turn on the transistor QA1~QAn and QB1~QBn to the pulse φVC to "1". As a result, the elements C11 to C1n are transiently refreshed, and the signal components of the optical information are removed. Then, when the pulse φVC is set to “0” to turn off the transistors QA1 to QAn and QB1 to QBn again,
The residual components of the elements C11 to C1n are used as noise components as vertical signal lines.
Read to VL1 to VLn. At this time, the pulse φY2 is set to “1”.
Then, when the transfer transistors Qh2 of the read circuits YA1 to YAn are opened, this noise component is accumulated in each capacitor C2 (period T3).

By the way, the potential of the vertical signal line, that is, the emitter potential of the element is made negative during the transient refresh because the element is completely forward-biased to remove the residual component contained in the noise component and read out earlier. This is to improve the similarity with the noise component included in the signal component.

When reading of the photoelectric conversion elements C11 to C1n in the first row is completed in this way, next, the photoelectric conversion elements C21 to C2n in the second row are next.
Is read out.

First, return the power Evc to potential E _H, the pulse φVC "1"
In to fix the signal line capacitance of the transistor QA1~QAn and QB1~QBn by turning on the vertical signal line HL1~HLn to the potential E _H. Next, the pulse φVC is set to “0” to set the transistor QA
1 to QAn and QB1 to QBn are turned off, and the vertical signal lines VL1 to VLn
In a state where is floating, the drive signal SV2 is set to a positive potential to perform a read operation of the elements C21 to C2n of the horizontal signal line HL2 to read optical information to the vertical signal lines VL1 to VLn. At the same time, the pulse φY3 is set to “1” to read out the readout circuit YB1 of the second horizontal scanning section 4.
YYBn transfer transistors Qh1 are turned on, and the read optical information is stored in each capacitor C1. As shown in FIG. 5, the arrangement of the color separation filters for the horizontal signal line HL2 is B for odd columns and W for even columns, so that the readout circuits YB1, YB3,
The blue signal component is stored in the capacitor C1 of YB5,..., And the white signal component is stored in the capacitor C2 of the readout circuits YB2, YB4, YB6,.

Subsequently, the elements C21 to C2n are transiently refreshed to remove the signal components of the optical information in the same manner as in the case of the period T3, and then the pulse φY4 is set to “1” and the transistors of the read circuits YB1 to YBn
Qh2 is opened, and the residual components of the elements C21 to C2n, that is, noise components are accumulated in each capacitor C2 (period T5).

Thus, the first horizontal scanning section 3 accumulates the signal components and the noise components of the white information and the red information of the elements C11 to C1n in the first row, and the second horizontal scanning section 4 stores the signal components and the noise components in the second row. The signal components and noise components of blue information and white information of the elements C21 to C2n are accumulated.

The above operation is performed in the horizontal blanking period HBLK, and subsequently, the optical information of the first and second rows stored in the horizontal scanning units 3 and 4 is scanned and output to the outside during the horizontal effective period. In parallel with this, the power Evc the potential E _H, turns on transistor QA1~QAn and QB1~QBn by the φVC to "1", the vertical signal line VL1~VLn to the potential E _H. In addition, the drive signals SV1 and SV2 are set to a negative potential,
Refresh the element in the row. That is, the MO of each element
The S transistor QC is turned on to reset each base potential of the transistor Tr to a constant value EC (period T6).

Subsequently, the drive signals SV1 and SV2 become positive potentials, and refresh the base region reset to a constant potential. That is, the emitter potential of each element, through the vertical signal lines, since it is fixed at a constant potential E _H, the capacitor
When a high positive voltage is applied than the voltage E _H to Cox, the base-emitter is forward biased, carriers accumulated in the base region in the same manner as the read operation disappears (period T7).

When the refresh operation is completed in this way, the elements in the first and second rows restart the accumulation operation.

Similarly, the reading and refreshing operations of the third and fourth rows, the fifth and sixth rows,... Being the odd field Fo by the pulses φV1 and φV2 are sequentially performed, and the scanning of the odd field Fo is performed. Ends.

In the even-numbered field Fe, the read and refresh operations of the second and third rows, the fourth and fifth rows,... Are similarly performed by the drive signals SV2 and SV3.

FIG. 7 is a timing chart showing an operation for reading out the optical information stored in the first and second horizontal scanning units 3 and 4 to the outside during the horizontal effective period (period T6). The operation of the figure is shown.

First, a read operation is started by applying a start pulse φHS to the horizontal scanning circuit 31. The horizontal scanning circuit 31 is driven by two-phase driving pulses φH1 and φH2, and outputs scanning pulses φA1, φA2... Which sequentially become “1” from output terminals.

At time t63, the scan pulse φA3 is output, and the scan transistors Qh3 and Qh7 of the readout circuit YA3 are turned on to buffer the signal component stored in the capacitor C1.
Read to read signal line AL1 via Qh5.

Next, at time t63 ', the transistor Qh6 is turned on by the pulse φYR, and the capacitor C1 and the buffer amplifier Q
The residual charge on the base of h5 is cleared via transistors Qh3 and Qh6. At this time, the buffer amplifier Qh5 is reverse-biased and becomes non-conductive, so the signal line AL1
Is read out as it is.

In the clear circuit 32, the transistor QC is generated by the pulse φC2.
2 and QC3 are turned on, and the signal lines AL2 and AL3 are cleared to the power supply Er and the ground, respectively.

The reason why the signal lines AL2 and AL4 are cleared to the power supply Er is that the signal reading periods T2 and T4 and the noise reading period T3
This is because the reference potentials at the time of reading at T5 and T5 are different. In other words, while the initial potential before the signal in the signal readout period T2 and T4 reading is E _H, since the initial potential before the noise reading the noise read period T3 and T5 are E _L, the capacitors C1 and C2 The DC potentials of the read signal component and the noise component are different. This potential is uniquely determined by the initial capacitance of the line capacitance of the vertical signal line and the temporary storage capacitance of the capacitors C1 and C2. In this embodiment, since the DC potential of the noise component read to the capacitor C2 is lower than the DC potential of the signal component read to the capacitor C1, the signal component and the noise component
When transferring the read signal lines AL1 to AL4 from C2 and C2 to the read signal lines AL1 to AL4, the signal lines AL2 and AL4 are cleared to make the base-emitter potential of the buffer amplifier Qh5 equal between the signal component read and the noise component read. Apply potential to signal line AL1
And a predetermined reference potential Er (negative potential in this embodiment) lower than AL3.

Next, at time t64, the transistors Qh4 and Qh8 of the read circuit YA3 are turned on by the scan pulse φA4, and the noise component accumulated in the capacitor C2 is read out to the signal line AL2 via the buffer amplifier Qh5. Therefore, the signal component and the noise component accumulated in the capacitors C1 and C2 of the readout circuit YA3 are both supplied to the input of the differential amplifier OP1 of the output circuit 33. The removed difference signal is held in the sample field circuit SH1 by the sampling pulse φsh1,
Output as signal SW.

The scanning pulse φA4 simultaneously turns on the transistors Qh3 and Qh7 of the readout circuit YA4, and reads out the red signal component stored in the capacitor C1 to the readout signal line AL3 via the buffer amplifier Qh5.

At time t64 ', the transistor Qh6 is turned on by the pulse φYR, and the capacitor C1 and the buffer amplifier Qh5 are cleared in the same manner as at the time t63'. In the clear circuit 32, the transistor Q is output by the pulse QC1.
C1 and QC4 are turned on, and signal lines AL1 and AL4 are
Cleared to r and ground.

At time t65, a scanning pulse φA5 is generated, and the above-described time t
Similarly to 63, the capacitor C of the readout circuit YA5 (not shown)
The signal component stored in 1 is read out to the signal line AL1. At the same time, the noise component stored in the capacitor C2 of the readout circuit YA4 is read out to the signal line AL4, and is input to the differential amplifier OP2 of the output circuit 33. Therefore, the differential amplifier OP2
Is supplied with both the signal component and the noise component accumulated in the capacitors C1 and C2 of the readout circuit YA4.
Is held by the sample-and-hold circuit SH2 and output as a signal SR.

Similarly, the scanning pulse φA from the horizontal scanning circuit 31
6, Capacitor C1 of readout circuit YA6, YA7, ... by φA7, ...
And C2 are sequentially read out and output as a white component signal SW and a red component signal SR.

Also, from the second horizontal scanning section 4, in the same manner as in the case of the first horizontal scanning section 3, the scanning circuits φB1, φB2, φB3,... From the horizontal scanning circuit 41 read the read circuits YB1, YB2, YB3,. …
The signals stored in the capacitors C1 and C2 are sequentially read, and a blue component signal SB and a white component signal SW are output.

FIG. 8 is a schematic circuit diagram showing another embodiment of the photoelectric conversion device according to the present invention.

In this embodiment, since only the signal component of the optical information stored in the photoelectric conversion element is read out and the noise component is not read out, the readout circuits YA1 to YAn and YB1 to YBn, the clear circuits 32 and 42, and the output circuit 33 And 43 are simplified, so that the read signal lines are changed to AL1 and AL2, BL1 and B
Only L2. The configuration is the same as that of FIG. 1 except that the vertical signal lines VL1 to VLn are grounded via the transistors QA1 to QAn and QB1 to QBn.

FIG. 9 shows a readout circuit YA of the first horizontal scanning section 3 of the present embodiment.
3 is a circuit diagram illustrating a configuration of YA4, a clear circuit 32. FIG.

In the figure, read circuits YA3 and YA4 are transfer transistors connected to vertical signal lines VL3 and VL4, respectively.
It has Q1, and accumulates the signal components read out to the vertical signal lines VL3 and VL4 in the capacitor C1 via the transistor Q1. Capacitor C1 is connected to readout signal line AL1 or AL2 via buffer amplifier Q2 and scan transistor Q4. In this case, the read circuits in the odd columns are connected to the signal line AL1, and the read circuits in the even columns are connected to the signal line AL2, so that the transistor Q4 of the read circuit YA3 is connected to the signal line AL1, and the transistor Q4 of the read circuit YA4 is connected. Are connected to the signal line AL2.

The base electrode of the buffer amplifier Q2 is a transistor
Grounded via Q3, the residual charge on the base is cleared together with the residual charge on the capacitor C1 each time a pulse φYR arrives at the gate electrode of the transistor Q3. Also, a pulse φY1 is applied to the gate electrode of the transistor Q1 of the odd-numbered readout circuits YA1, YA3, YA5,. Each is applied.

The clear circuit 32 clears the line capacitance of the signal lines AL1 and AL2, and includes a transistor Q5 that clears the signal line AL1 to the ground potential, and a transistor Q6 that clears the signal line AL2 to the ground potential. Pulses φc1 and φc2 are supplied to the gate electrode of Q6, respectively. The output of the clear circuit 32 is output from an output circuit 33 (not shown).
Is output to the outside through the buffer circuit of FIG.

FIG. 10 and FIG. 11 are timing charts for explaining the operation of FIG. 8 and FIG. The basic operation is the same as in FIGS. 6 and 7, and will be described briefly.

First, in the period T1 ′, the pulse φYR becomes “1”, turning on the transistors Q3 of the read circuits YA1 to YAn and YB1 to YBn to clear the base regions of the capacitor C1 and the transistor Q2.

Next, in a period T2 ′, the drive signal SV1 becomes a positive potential,
Reading of the elements C11 to C1n connected to the horizontal signal line HL1 is performed. At the same time, the pulses φY1 and φY2 become “1”, so that each transistor Q1 of the readout circuits YA1 to YAn is turned on, and optical information is accumulated in each capacitor C1. In this case, white signal components are stored in the odd-numbered readout circuits YA1, YA3, YA5,..., And red signal components are stored in the even-numbered readout circuits YA2, YA4, YA6,.

Subsequently, in a period T3 ′, the pulse φVC becomes “1”,
The line capacitance of the vertical signal lines HL1 to HLn is cleared and the element C2
Prepare for reading 1 to C2n.

Next, in the period T4 ', the drive signal SV2 becomes positive potential, and the element C
The read operation of 21 to C2n is performed, and at the same time, the pulses φY3 and φY4 become “1”, and optical information is accumulated in each capacitor C1 of the read circuits YB1 to YBn. In this case, blue signal components are stored in the odd-numbered readout circuits YB1, YB3, YB5,..., And white signal components are stored in the even-numbered readout circuits YB2, YB4, YB6,.

In the horizontal effective period T5 ', the read circuits YA1 to YAn and YB1
~ Scan the optical information stored in YBn and output to the outside, reset the elements C11 ~ C1n and C21 ~ C2n,
Refresh in period T6 '.

Next, the operation of the first horizontal scanning unit in the period T5 'will be described with reference to FIG.

In the present embodiment, since the reading of the noise component is not performed, the reading circuit is operated in accordance with the scanning pulses φA3, φA4,.
The white signal component and the red signal component are sequentially read from the capacitors C1 of YA3, YA4,... To the signal lines AL1 and AL2, and the line capacitance of the read signal lines AL1 and AL2 is cleared by the clear circuit 32 during the reading operation. As pulse φC1
And φC2 are supplied.

Next, another read operation in the embodiment of FIG.
This will be described with reference to the timing chart in FIG.

In the above-described read operation, the color signal components accumulated in the elements C11 to C1n in the first row are read out to the first horizontal scanning unit, and
The color signal components accumulated in the elements C21 to C2n in the row are read out to the second horizontal scanning unit. However, in this embodiment, when reading out the elements C11 to C1n in the first row, the pulse φY1 And φY4 are set to “1” to read the white signal components of the odd-numbered columns to the first horizontal scanning unit and the red signal components of the even-numbered columns to the second horizontal scanning unit, respectively, and read out the elements C21 to C2n in the second row. At times, the pulses φY2 and φY3 are set to “1” so that the blue signal components in the odd columns are read out to the second horizontal scanning unit, and the white signal components in the even columns are read out to the first horizontal scanning unit.

As described above, by reading out the white signal components forming the luminance signal from the same direction in both the odd-numbered rows and the even-numbered rows, the signal waveforms or the frequency characteristics of the white signal components substantially match, and the signal processing in the subsequent stage is performed. Since the wiring processing can be performed in the same manner in the circuit, a luminance signal with less fixed pattern noise and good frequency characteristics can be obtained.

[Effects] As described in detail above, according to the photoelectric conversion device of the present invention, the optical information stored in the imaging unit is selectively read from both directions of the vertical signal line. It is possible to cope with the reduction and the increase in the frequency of the scanning pulse, and it is possible to expand the range of application to various systems, such as application to a monochrome camera and various color cameras.

In addition, since a signal forming a luminance signal can be read from the same signal line or a neighboring signal line, a signal with good image quality can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing one embodiment of a photoelectric conversion device according to the present invention, FIG. 2 is a circuit diagram showing a vertical scanning unit in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a part of the horizontal scanning unit in FIG. 1, FIG. 5 is a layout diagram of a color separation filter, FIG. 6 and FIG. 8 is a timing chart for explaining the operation of FIG. 4; FIG. 8 is a schematic circuit diagram showing another embodiment of the photoelectric conversion device according to the present invention; FIG. 9 is a horizontal scanning unit of FIG. 10 and 11 are timing charts for explaining the operation of FIGS. 8 and 9, and FIG. 12 is another read operation of FIG. FIG. 13 is a schematic circuit diagram showing an example of a conventional photoelectric conversion device. DESCRIPTION OF SYMBOLS 1 ... Image pick-up part 2 ... Vertical scanning part 3 ... 1st horizontal scanning part 4 ... 2nd horizontal scanning part 31 ... 1st horizontal scanning circuit 41 ... 2nd horizontal scanning circuit C11-C1n ... Photoelectric conversion Element HL1 to HLn Horizontal signal lines VL1 to VL2 Vertical signal lines YA1 to YAn First readout circuit YB1 to YBn Second readout circuit

Claims (1)

(57) [Claims] A plurality of photoelectric conversion elements arranged in a matrix on a plurality of horizontal signal lines and a plurality of vertical signal lines; and a plurality of photoelectric conversion elements provided at a first end side of the vertical signal lines and stored in the photoelectric conversion elements. First accumulation means for selectively accumulating the photocharge information, and a second accumulation means provided on a first end side of the vertical signal line for accumulating a residual signal after refresh operation of the photoelectric conversion element. Storage means, and between the vertical signal line and the first and second storage means for selectively guiding the output of the photoelectric conversion element sequentially to the first and second storage means. The first provided,
Second switch means, and first difference processing means for performing a difference process between the read signal and the residual signal stored in the first and second storage means via the first and second switch means. A third storage means provided on a second end side of the vertical signal line opposite to the first end, for selectively storing the photocharge information stored in the photoelectric conversion element; Fourth storage means provided on the second end side of the vertical signal line for storing a residual signal after the element has been refreshed; and storing the output of the photoelectric conversion element in the third and fourth storages. And third and fourth storage means respectively provided between the vertical signal line and the third and fourth storage means for selectively guiding the data sequentially.
Fourth switch means; and second difference processing means for performing a difference processing of the read signal and the residual signal stored in the third and fourth storage means via the third and fourth switch means. And a photoelectric conversion device comprising: