JPH01116862A - マルチプロセッサシステムにおけるクロック同期方式 - Google Patents

マルチプロセッサシステムにおけるクロック同期方式

Info

Publication number
JPH01116862A
JPH01116862A JP62276391A JP27639187A JPH01116862A JP H01116862 A JPH01116862 A JP H01116862A JP 62276391 A JP62276391 A JP 62276391A JP 27639187 A JP27639187 A JP 27639187A JP H01116862 A JPH01116862 A JP H01116862A
Authority
JP
Japan
Prior art keywords
time
clock
processor
processors
interrupt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62276391A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0528867B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Satoshi Hasegawa
聡 長谷川
Shoichiro Nakai
正一郎 中井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62276391A priority Critical patent/JPH01116862A/ja
Publication of JPH01116862A publication Critical patent/JPH01116862A/ja
Publication of JPH0528867B2 publication Critical patent/JPH0528867B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP62276391A 1987-10-30 1987-10-30 マルチプロセッサシステムにおけるクロック同期方式 Granted JPH01116862A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62276391A JPH01116862A (ja) 1987-10-30 1987-10-30 マルチプロセッサシステムにおけるクロック同期方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62276391A JPH01116862A (ja) 1987-10-30 1987-10-30 マルチプロセッサシステムにおけるクロック同期方式

Publications (2)

Publication Number Publication Date
JPH01116862A true JPH01116862A (ja) 1989-05-09
JPH0528867B2 JPH0528867B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-04-27

Family

ID=17568758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62276391A Granted JPH01116862A (ja) 1987-10-30 1987-10-30 マルチプロセッサシステムにおけるクロック同期方式

Country Status (1)

Country Link
JP (1) JPH01116862A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04225647A (ja) * 1990-04-02 1992-08-14 American Teleph & Telegr Co <Att> 相互接続されたディジタル機器を同期する方法
JP2011199420A (ja) * 2010-03-17 2011-10-06 Mitsubishi Electric Corp リング状同期ネットワークシステム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04225647A (ja) * 1990-04-02 1992-08-14 American Teleph & Telegr Co <Att> 相互接続されたディジタル機器を同期する方法
JP2011199420A (ja) * 2010-03-17 2011-10-06 Mitsubishi Electric Corp リング状同期ネットワークシステム

Also Published As

Publication number Publication date
JPH0528867B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-04-27

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