JPH0528864B2 - - Google Patents
Info
- Publication number
- JPH0528864B2 JPH0528864B2 JP62151827A JP15182787A JPH0528864B2 JP H0528864 B2 JPH0528864 B2 JP H0528864B2 JP 62151827 A JP62151827 A JP 62151827A JP 15182787 A JP15182787 A JP 15182787A JP H0528864 B2 JPH0528864 B2 JP H0528864B2
- Authority
- JP
- Japan
- Prior art keywords
- clock
- time
- processors
- processor
- control block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 28
- 238000004891 communication Methods 0.000 description 18
- 238000004422 calculation algorithm Methods 0.000 description 17
- 230000004044 response Effects 0.000 description 10
- 230000001360 synchronised effect Effects 0.000 description 5
- 230000001934 delay Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- GDOPTJXRTPNYNR-UHFFFAOYSA-N methyl-cyclopentane Natural products CC1CCCC1 GDOPTJXRTPNYNR-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Landscapes
- Multi Processors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62151827A JPS63314670A (ja) | 1987-06-17 | 1987-06-17 | マルチプロセッサシステムにおけるクロック同期方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62151827A JPS63314670A (ja) | 1987-06-17 | 1987-06-17 | マルチプロセッサシステムにおけるクロック同期方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63314670A JPS63314670A (ja) | 1988-12-22 |
| JPH0528864B2 true JPH0528864B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1993-04-27 |
Family
ID=15527179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62151827A Granted JPS63314670A (ja) | 1987-06-17 | 1987-06-17 | マルチプロセッサシステムにおけるクロック同期方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63314670A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
-
1987
- 1987-06-17 JP JP62151827A patent/JPS63314670A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63314670A (ja) | 1988-12-22 |
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