JPH01116454A - Full-wave rectifying circuit - Google Patents
Full-wave rectifying circuitInfo
- Publication number
- JPH01116454A JPH01116454A JP27492187A JP27492187A JPH01116454A JP H01116454 A JPH01116454 A JP H01116454A JP 27492187 A JP27492187 A JP 27492187A JP 27492187 A JP27492187 A JP 27492187A JP H01116454 A JPH01116454 A JP H01116454A
- Authority
- JP
- Japan
- Prior art keywords
- value
- transistor
- input signal
- current
- full
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007423 decrease Effects 0.000 abstract description 4
- 238000001514 detection method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Rectifiers (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は全波整流回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a full-wave rectifier circuit.
第2図に従来の半波整流回路例を示す0図において、電
圧源15は入力が無信号時にトランジスタ11がオフと
なる電圧値とする0図において、12はコンデンサ、1
3.14は抵抗である。FIG. 2 shows an example of a conventional half-wave rectifier circuit, in which the voltage source 15 has a voltage value that turns off the transistor 11 when there is no input signal.
3.14 is resistance.
入力端子に第3図のような信号が入力された場合、A点
の電位がトランジスタ11を導通するに足する電位にな
った時点から入力信号の大小に応じてトランジスタ11
に流れる電流が増減する。このときB点には、第5図の
ような電流波形が現れ、この電流変化を抵抗14で電圧
変化として取り出すことによって入力信号を半波整流す
るものである。When a signal as shown in FIG. 3 is input to the input terminal, the transistor 11 changes depending on the magnitude of the input signal from the point at which the potential at point A reaches a potential sufficient to make the transistor 11 conductive.
The current flowing through increases and decreases. At this time, a current waveform as shown in FIG. 5 appears at point B, and by extracting this current change as a voltage change at the resistor 14, the input signal is half-wave rectified.
上述した従来の半波整流回路は入力信号のピーク値のみ
を検出しており、ボトム値に対しては動作しないため1
回路の後段に接続するピーク保持回路の時定数を大きく
する必要があるという欠点がある。The conventional half-wave rectifier circuit described above detects only the peak value of the input signal and does not operate on the bottom value.
There is a drawback that the time constant of the peak holding circuit connected to the subsequent stage of the circuit needs to be increased.
本発明の目的は上記欠点を解消した全波整流回路を提供
することにある。An object of the present invention is to provide a full-wave rectifier circuit that eliminates the above-mentioned drawbacks.
本発明は入力信号の最大値、最小値を検出する全波整流
回路にお・いて、入力信号のピーク値を検出してこれを
電流値に変換する第1のトランジスタと、ボトム値を検
出してこれを電流値に変換する第2のトランジスタとを
備えたことを特徴とする全波整流回路である。The present invention is a full-wave rectifier circuit that detects the maximum and minimum values of an input signal, and includes a first transistor that detects the peak value of the input signal and converts it into a current value, and a first transistor that detects the bottom value. This is a full-wave rectifier circuit characterized by comprising a second transistor that converts the current into a current value.
第1図に本発明の実施例を示す0図において、本発明は
2つのトランジスタ1,2と、各トランジスタのベース
・エミッタ間に接続された2つの電圧源6,7と、コン
デンサ3及び抵抗4,5を備え、両トランジスタ1,2
はコレクタ間が接続され、入力はコンデンサ3を通して
図中A点に加えられ、出力はB点の電流変化が抵抗15
で電圧変化として取り出される。1 shows an embodiment of the present invention, the present invention consists of two transistors 1 and 2, two voltage sources 6 and 7 connected between the base and emitter of each transistor, a capacitor 3, and a resistor. 4, 5, both transistors 1, 2
is connected between the collectors of
is extracted as a voltage change.
電圧源6及び7は入力が無信号時にトランジスタ1及び
トランジスタ2がオフとなる電圧値とする。Voltage sources 6 and 7 are set to voltage values that turn off transistor 1 and transistor 2 when there is no input signal.
入力端子に第3図のような信号が入力された場合、正レ
ベルの信号の場合は、A点の電位がトランジスタ1を導
通するに足りる電位になった時点から入力信号の大小に
応じて、トランジスタ1に流れる電流が増減する。この
電流のピーク値が入力信号のピーク値に対応する。この
とき、トランジスタ2はベース・エミッタ間の電位差が
導通するに足りる値以下となるため、オフ状態となる。When a signal as shown in Fig. 3 is input to the input terminal, if it is a positive level signal, from the time when the potential at point A reaches a potential sufficient to make transistor 1 conductive, depending on the magnitude of the input signal, The current flowing through transistor 1 increases or decreases. The peak value of this current corresponds to the peak value of the input signal. At this time, the potential difference between the base and emitter of the transistor 2 becomes less than a value sufficient for conduction, so that the transistor 2 is turned off.
また、負レベルの信号が入力された場合は、A点の電位
がトランジスタ2を導通するに足りる電位となった時点
から入力信号の大小に応じてトランジスタ2に流れる電
流が増減する。この電流のピーク値が入力信号のボトム
値となる。このとき、トランジスタ1はベース・エミッ
タ間の電位差が導通するに足りる値以下となるため、オ
フ状態となる。Further, when a negative level signal is input, the current flowing through the transistor 2 increases or decreases depending on the magnitude of the input signal from the time when the potential at the point A becomes a potential sufficient to make the transistor 2 conductive. The peak value of this current becomes the bottom value of the input signal. At this time, the potential difference between the base and emitter of the transistor 1 becomes less than a value sufficient for conduction, so that the transistor 1 is turned off.
前記の動作を繰り返すことにより第1図のB点には第4
図のような電流波形が現れる。By repeating the above operation, the fourth point will be placed at point B in Figure 1.
A current waveform as shown in the figure appears.
この電流変化を抵抗5で電圧変化として取り出し、入力
信号のピーク値、ボトム値を検出し全波整流をする。This current change is taken out as a voltage change by a resistor 5, the peak value and bottom value of the input signal are detected, and full-wave rectification is performed.
以上説明したように本発明は入力信号のピーク値、ボト
ム値を検出する構成としたことにより、本全波整流回路
の後段に接続するピーク保持回路の時定数を従来の回路
に比べると172にできる効果がある。As explained above, the present invention has a configuration that detects the peak value and bottom value of the input signal, so that the time constant of the peak holding circuit connected after the present full-wave rectifier circuit can be reduced to 172 compared to the conventional circuit. There is an effect that can be done.
第1図は本発明の実施例を示す回路図、第2図は従来例
の半波整流回路を示す回路図、第3図は第1図、第2図
の入力電圧波形を示す図、第4図は本発明回路に第3図
の波形を入力したときのB点の電流波形を示す図、第5
図は従来の回路に第3図の波形を入力したときのB点の
電流波形を示す図である。Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional half-wave rectifier circuit, Fig. 3 is a diagram showing the input voltage waveforms of Figs. Figure 4 shows the current waveform at point B when the waveform in Figure 3 is input to the circuit of the present invention, and Figure 5 shows the current waveform at point B.
The figure shows a current waveform at point B when the waveform shown in FIG. 3 is input to a conventional circuit.
Claims (1)
路において、入力信号のピーク値を検出してこれを電流
値に変換する第1のトランジスタと、ボトム値を検出し
てこれを電流値に変換する第2のトランジスタとを備え
たことを特徴とする全波整流回路。(1) In a full-wave rectifier circuit that detects the maximum and minimum values of an input signal, the first transistor detects the peak value of the input signal and converts it into a current value, and the first transistor detects the bottom value and converts it into a current value. A full-wave rectifier circuit comprising: a second transistor that converts into a current value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27492187A JPH01116454A (en) | 1987-10-30 | 1987-10-30 | Full-wave rectifying circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27492187A JPH01116454A (en) | 1987-10-30 | 1987-10-30 | Full-wave rectifying circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01116454A true JPH01116454A (en) | 1989-05-09 |
Family
ID=17548397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27492187A Pending JPH01116454A (en) | 1987-10-30 | 1987-10-30 | Full-wave rectifying circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01116454A (en) |
-
1987
- 1987-10-30 JP JP27492187A patent/JPH01116454A/en active Pending
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