JPH01109814A - Voltage comparator circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption of a voltage comparator without increasing the number of element by controlling the connection between a differential stage and a load circuit by means of a switch controlled by a control signal. CONSTITUTION:NMOS transistors; M4-M7 change over M2 and M3 of a differential input stage and M8 and M9 being its load circuit. Just after a switching control signal CLK 1 goes to a high logic level, voltages V10, V11 and V8, V9 change rapidly to change a voltage at input terminals 4, 5 through the stray capacitance between the gate and drain electrodes of the M2, M3. Thus, the timing when the input starts changing comes after a prescribed time elapses after the CLK 1 goes to a high logic level. Since the current flowing to a load TR is made zero, useless power consumption is suppressed.

Description

[Detailed Description of the Invention] - [Field of Industrial Application] The present invention relates to a voltage comparator, and more specifically,
The present invention relates to a voltage comparator that compares the magnitude of two analog voltages and outputs a logic level corresponding to the result, and is particularly suitable for implementation in an MO8 semiconductor integrated circuit.

[Conventional technology]

A conventional voltage comparator can be set to a preamplifier mode by switching the connection of the gate electrodes of two MoS transistors forming a load circuit of a differential amplifier stage, as described in, for example, Japanese Patent Laid-Open No. 60-70816. By selecting one of the two modes including the comparison amplification mode, stable comparison and amplification operation of the two analog comparison voltages is realized.

[Problem that the invention seeks to solve]

However, in the conventional circuit described above, a constant current flows between the power supplies (V
oo-Vss), so under usage conditions that the input is only valid for a portion of one clock cycle, power is wasted during the period when the input is invalid. There is.

In order to avoid this, it is necessary to add a switch means for switching the bias voltage so as to limit the current during the input invalid period and a logic circuit for controlling the operation of the switch means.

An object of the present invention is to provide a voltage comparator that can reduce power consumption without increasing the number of elements in the voltage comparison circuit.

[Means for solving problems]

In order to achieve the above object, the present invention includes the above-mentioned switch means for controlling the current, and load circuit switching means for operating the differential amplifier stage in either the preamplifier mode or the comparison amplification mode. It is characterized by being shared.

[Effect]

That is, in the voltage comparator of the present invention, the gate electrodes of two transistors forming a load circuit are fixedly connected to the drain electrodes of two differential input transistors, and the drain electrodes of the load transistors are connected to the drain electrodes of the two differential input transistors. The connecting point is configured to be switched and connected to the above-mentioned connection point by a switching means provided between the two connection points.

According to the present invention, by not connecting the switching means to any of the load transistors during a period when the input is invalid, the current flowing through the load transistors can be reduced to zero, thereby reducing unnecessary power consumption. It becomes possible to suppress the

〔Example〕

Hereinafter, the present invention will be explained using the drawings. FIG. 1 is a circuit diagram showing one embodiment of a voltage comparator according to the present invention.

The voltage comparator according to the present invention has voltages Vno and Vss at power supply terminals 1 and 2, respectively (where Voo-Vss>0
) is applied, and the gate electrode of the p-channel MOS transistor (hereinafter simply referred to as PMO8) M1 is connected to the terminal 3.
A bias voltage from VB to VB is applied. Va is M
Set so that a current io flows through the transistor l. M
2 and M3 are PMO3 transistors having the same size, whose source electrodes are commonly connected, and whose respective gate electrodes 4
and 5 are the two analog voltages Vt, (-
) and vi, (+) are applied, forming a differential input stage. N-channel MOS transistors (hereinafter simply referred to as NHO8) M8 and M9 are load circuits for M2 and M3, and their respective gate electrodes are connected to the drain electrodes 8 and 9 of the differential input stage. NHO2; M4 to M7 are connected between the drain electrodes 8 and 9 of the differential input stage and the drain electrodes 10 and 11 of the load circuit. That is, M4 is connected between the drain electrode 8 of the differential input stage and the drain electrode 10 of the load circuit, and M5 is connected between the drain electrode 9 and the drain electrode 11. M6 is connected between the drain electrode 8 and the drain electrode 11, and Ml is connected between the drain electrode 9 and the drain electrode 1ftio. These NHO2; M4 to M7 are connected to M2 and M3 . of the differential input stage. and its load circuit M
This is to switch the interconnection between M8 and M9.

Furthermore, PMO8; MlOl and NHO8; Mll are
The gate and drain electrodes of each are connected to each other to form a so-called CMO8 inverting amplifier. This inverting amplifier inverts and amplifies the voltage appearing at the drain electrode 11 of the load circuit described above, and as a result of the comparison, the voltage between the power supplies (
Output terminal 1 outputs a logic level close to Voo-Vgs).
Output to 2.

Next, the operation of each part of the above circuit configuration will be described.

FIG. 2 is a waveform diagram for explaining the operation of the above embodiment, in which the horizontal axis represents the switching control signal CLKI.

The numbers in Figure 6, which show the current flow through CLK2 and Ml, and the operating waveforms of each part, indicate the voltages at the nodes with the same numbers in Figure 1.The voltage applied to terminal 5, Vt, (+) is constant. The voltage applied to the terminal 4 vIII(-) will be explained as a voltage to be compared with the voltage V*-(+). 0≦1
< In the time range of 11.

Since CLKI at terminal 6 and CLK2 at terminal 7 are both at a low logic level, transistors M4-M7 are all off and no current flows.

In the time range t1≦t<tx, CLKI of terminal 6
Since the current becomes a high logic level, both transistors M4 and M5 turn on, and a current begins to flow. During this period, the connection between the differential input stage and the load circuit is in the state shown in FIG. 3(a), with M1 to M3°M8. The first stage circuit consisting of M9 operates as a linear differential amplifier, and Via (+)
” If Vt+a (-), then node 10.11 (7) voltage V
to, Vxx becomes Vxo:Vnx.

Next, vfin (+) of terminal 5 becomes vt of terminal s, (-)
'When ΔvlB becomes lower than ', vtll(+) = v
t.

(-)-ΔVwa, Vzo:Vzz-ΔVoa.

Next, at t = t x, if CLKI at terminal 6 is set to a low logic level and CLK2 at terminal 7 is set to a high logic level, then M4. M
5 is off state, M6. M7 becomes an on-state layer, and the load M8
．． M9 and differential input stage M2. M3 is.

As shown in FIG. 3(b), a cross-connected state is created.

Cross-connected load transistor M8. Since the gate electrodes of M9 are connected to nodes 8 and 9, respectively, positive feedback is applied to increase ΔVoa. Therefore, the voltage swing between nodes 10 and 11 will be much larger than VOB, and the output of the subsequent CMO8 inverting amplifier (consisting of Mlo and Mll) will be at a low logic output level.

During the period t8≦t<t4, CLKI of terminal 6.

CLK2 at terminal 7 both go to a low logic level, and the current no longer flows. At this time, ML, M2. Since M3 is on, the voltage V a at nodes 8 and 9.

It becomes Ve4Voo. Also 1M8. Since M9 is on-site, Vzo and Vtz4 Vais.

When t4≦t<t y, contrary to what was mentioned above, terminal 5 (7) V t -(+) becomes Vl@(+) of terminal 6.
-), and a high logic output opposite to that described above is obtained.

In this example, the timing at which the input starts to change is
This is assumed to be after a certain period of time has elapsed since CLKI became a high logic level. This means that immediately after CLKI goes to a high logic level, V 1G , V 11 . and Va, Vs
suddenly changed to 1M2. This is to change the voltages at the input terminals 4 and 5 through the overlapping capacitance between the gate and drain electrodes of M3.

FIG. 4 shows a second embodiment of the present invention, in which M2. For the differential input stage consisting of M3, a MOS transistor M14.Ml5 serving as a load and a MOS transistor M12.M15 for positive feedback are provided. Ml3 are provided separately and connected to the drain electrodes of the differential input stage. The source electrodes of Ml4゜Ml5 are connected to the switching control signal CLK.
They are commonly connected to the drain electrodes of M17, which is turned on when 1 is at a high logic level, and the source electrodes of M17 are connected to the power supply Vsg. Also, Ml2. The source electrode of Ml3 is
M turns on when switching control signal CLK2 is at a high logic level.
The source electrode of Ml6 is connected to the power supply Via.
It is connected to the.

The circuit of FIG. 4 uses the analog input voltages Via (+) and Vi-(-) when the switching control signal CLKI is at a high logic level.
), and the result appears as a potential difference between node 8 and node 9. When the switching control signal CLK2 is at a high logic level,
The above-described potential difference between node 8 and node 9 is amplified by positive feedback.

When the switching control signals CLKI and CLK2 are both at a low logic level, both M16 and M17 are in the off state, so no current flows through the differential stage. Therefore, this circuit is the first stage of the circuit shown in FIG. Note that in the above embodiment, especially when operating multiple voltage comparators in parallel at the same timing, node 2
1 and 22 can be commonly connected to the corresponding nodes of other voltage comparators, and MOS transistors M16 and M17, which are turned on and off by a switching control signal, are used as one element for a plurality of voltage comparators. You can do it one by one.

FIG. 5 shows a third embodiment of the invention, in which MOS transistors M2. M2S and M19, which are turned on by the switching control signal CLK2, are connected to each drain electrode of the differential input stage composed of M3, and M2O and M21 for positive feedback are connected to the source electrodes of these M2S and M19, respectively. .

Above M2. A switching control signal CL is connected to the drain electrode of M3.
M22 turned on with KI. M2S is also connected. C.L.
When KI is at a high logic level, M22°M2S is turned on and thus functions as a load for the differential input stage. When CLK2 is at a high logic level.

M2S and M19 are turned on, and M2O and M21 perform positive feedback operation. When CLKI and CLK2 are both at a low logic level, no current flows through the differential input stage.

That is, this embodiment circuit can also perform the same operation as the first stage of the circuit shown in FIG. In the third embodiment, the amplitude of CLKI is changed from Vss to a preferable embodiment as a differential stage load.

〔Effect of the invention〕

As explained above, according to the present invention, the current flowing through the voltage comparator can be made zero according to the logical value of the control signal,
Furthermore, since the connection between the differential stage and the load circuit can be controlled by the switch controlled by the control signal, the power consumption of the voltage comparator can be reduced without increasing the number of elements.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3(a) and 3(b) are diagrams showing the connection equivalent circuits of the circuit in FIG. Figure 5

Claims (1)

[Claims] 1. A differential input stage into which two analog voltages to be compared are input, a load circuit, and differential amplification by connecting the load circuit as a load of the differential input stage. A voltage comparator comprising means for switching between a first state in which a width stage is configured and a second state in which a voltage difference generated at the output of the differential amplification stage is amplified by positive feedback, The differential input stage is composed of first and second transistors whose respective source electrodes are commonly connected to a constant current circuit, and whose gate electrodes are respectively applied with the two analog input voltages, and the load circuit is , third and fourth transistors whose source electrodes are commonly connected to a fixed potential and whose gate electrodes are connected to the drains of the first and second transistors, respectively; fifth and sixth transistors connected between the drains of the third transistor and between the drains of the second and fourth transistors, respectively, and having gates commonly connected to the first switching control signal; between the drains of the fourth transistor and the second
, seventh and eighth transistors each connected between the drains of the third transistor and having gates commonly connected to the second switching control signal. 2. In the voltage comparator according to claim 1, the load circuit is composed of a circuit that serves as a load for the differential input stage, and a circuit that performs positive feedback using the differential input stage as a load,
A voltage comparator characterized by selectively switching using switching means.