JPH01108761A - High breakdown strength semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the resistance of base region, improve the breakdown strength, and enable controlling the threshold voltage proper to DMOS, by constituting the base region of a high breakdown strength DMOS transistor of a shallow region of high concentration and a deep region of low concentration. CONSTITUTION:On one main surface of a P-type silicon substrate 23, an N<-> epitaxial layer 14 is grown, and P<+> impurity diffusion layer 15 reaching the P-type silicon substrate 13 and a thick oxide film 16 are formed on an element isolation region. After, by using a diffusion mask, P-type impurity is ion- implanted into the N<->epitaxial layer 14 in the manner of surface concentration, a diffusion region is formed by heat treatment, and turned into a well region 17 of an N-channel transistor of CMOS, and a first base region 18 of DMOS. After a gate oxide film 19 is formed and a gate electrode 20 is formed of polysilicon, P-type impurity is ion-implanted into the first base layer 18 of DMOS, by using the gate electrode 20 and the thick oxide film 16 as masks. Further heat treatment is performed and a diffusion region is formed, which is turned into a second base region 21.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an insulated gate FET having a high breakdown voltage.

Conventional technology> Insulated gate FETs are used as semiconductor devices with high breakdown voltage.
(hereinafter referred to as MO5FET) is generally widely used. The structure of the MO5FET will be explained with reference to diagram M4.

An N-epitaxial layer 2 is formed on a P-type silicon substrate 1, and a low-concentration P-type impurity diffusion region 3 is formed in the N-epitaxial layer 2 to become a substrate (hereinafter referred to as base) of the MOSFET. A source region 4 is formed by implanting N-type impurities at a high concentration, and the space region 8 and N-
The N-epitaxial layer 2 via the epitaxial layer 2
A drain region 5 is formed by doping or implanting N-type impurities at a high concentration. the drain region 5 and the source region 4
The upper layer of the space region 3 between the space region 3 acts as a channel, and a gate electrode 6 is formed on the channel region via an insulating film, and electrodes 7 are also formed on the source region 4 and drain region 5, respectively. 〇2t #I The MOSFET with this unstructured structure is especially polar-1 → Yu #)
It is called the 4-tei MOSFET (hereinafter referred to as DMO5). Since the impurity implantation into the pace region 3 is performed in a self-aligned manner using the gate electrode 6 as a mask, the long-time high temperature heat treatment step for diffusing the implanted impurity is relatively slow, and the impurities are formed on the same silicon substrate 1. This tends to affect the reliability of other semiconductor devices such as CMOS. For this reason,
The heat treatment process for forming the pace region 3 needs to be short, and as a result the pace region 3 becomes relatively shallow (
(approximately 2 μm), electric field concentration tends to occur, making it difficult to obtain a very high breakdown voltage. As a method to solve this problem and obtain a relatively deep pace region without increasing the number of steps, there is a method of forming the pace region 9 at the same time as the well region 8 of the CMOSN channel transistor is formed, as shown in FIG. At this time, the well region 8 of the 0MO8N channel transistor is relatively deep (approximately 5 μm) and has a relatively low concentration (N
A 10 cm).

<Problems to be Solved by the Invention> Here, an L-lateral NPN bipolar transistor structure exists in the N-type source region 10, P-type base 1N region 9, N-epitaxial layer 11, and N-type drain region 12 in the DMOS. However, as described above, the impurity concentration in the pace region 9 is relatively high, and there is a problem that the withstand voltage in the ON state between the drain and the source is lowered due to the bipolar transistor effect.

Furthermore, as shown in the fifth factor, since the well region 8 of the CMOS N-channel transistor and the space region 9 of the DMOS are formed in the same process, the threshold voltage of the CMOS N-channel transistor and the threshold voltage of the N-channel DMO transistor are the same. or N-channel DMOS5) transistors, the lateral diffusion region of the P-type base region 9 is sometimes used as a channel region;
The threshold voltage is lower than that of a channel transistor. However, - there is an N-channel DMO in the film.
5) Since the threshold voltage of the transistor and the threshold voltage of the CMOS N channel transistor are set high, there is a problem that the threshold voltage of the CMOS N channel transistor must be lowered by channel doping of the 6MO8N channel transistor. Means for Solving the Problems> The present invention has been made to solve the above-mentioned problems, and in an FET formed on a first conductivity type semiconductor substrate, a source region formed of a g1 conductivity type impurity region. The pace region surrounds the pace region, and includes: a second conductivity type impurity high concentration region that surrounds the pace region and is formed relatively shallowly; and a second conductivity type impurity high concentration region that surrounds the second conductivity type impurity high concentration region and is formed relatively deeply. As described above, the pace region of the high voltage DMO5 transistor is composed of a shallow high concentration region and a deep low concentration region. In particular, the electric field concentration in the pace region can be alleviated by the deeper low-concentration region, and at the same time, the resistance of the pace region can be lowered by the presence of the shallow high-concentration region. Even when formed using a common process on the same substrate as other semiconductor devices, since the space region is a double diffusion region, it is possible to control the threshold voltage of the five DMOs. becomes.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto. DMOS and C
0, which is formed by sharing the process with MOS, +000
・I on the whole surface of the (+00) P-type silicon substrate 13 of m
An N-epitaxial film 414 of OΩ·m is grown to a thickness of about 20 μm, and the P-type silicon substrate 1 is grown in the element isolation region.
3 P+ impurity diffusion region 15 and thick oxide film 16
form. Next, using a diffusion mask, the N-epitaxial layer 4 is doped with a P-type impurity at a surface concentration of IX1.
After ion implantation of approximately 0 m6 cm-3, heat treatment is performed to form a diffusion region with a depth of 5 to 6 μm, and the well region 17 of the CMOS N-channel transistor and the DMOS
The first pace area 18 of FIG.

Next, a gate oxide film 19 is formed, and a gate electrode 20 is formed of polysilicon. Using the gate electrode 20 and the thick oxide film 16 as a mask, a P-type impurity is added to the surface concentration of the first space region 18 of 0MO5. 5X10”t-In
-3 ion implantation and further heat treatment to form a diffusion region with a depth of 2 μm, which will be used as the second pace region 21 of the DMO 8. Subsequently, using a conventionally known technique, 0MO5
Source region 22, drain region 23, CMO5N channel transistor source, drain region 24, CMO
Source and drain regions 25 of 5P channel transistor
, and further form source and drain electrodes 26 and the like to complete the transistor.

It is advantageous to configure the pace region of this transistor with a shallow high-concentration region and a deep low-concentration region. resistance is low. In addition, the DMOS pace region and the well region of the CMO5N channel transistor are formed in a common process, but the base region of the 0MO5 is made up of two layers, and the second base region, which controls the threshold voltage of the DMOS, and the CMO8N channel transistor are formed in the same process. The 0MO5 threshold is formed in a separate process from the well regions that affect the threshold voltage of the gate.

The field voltage and the threshold voltage of the CMO5N channel transistor can be controlled individually.

In the above embodiment, the OMO5 of the present invention was applied to a horizontal transistor, but the present invention is not limited thereto.As shown in FIG. The N+ electrode 2 is implanted into the N+ epitaxial layer 14 to form the N+ buried layer 27.
It is also possible to use a vertical transistor forming the drain region 28 reaching the drain region 7.

Further, in the above embodiment, the OMO5 is formed on the same substrate as the CMOS, but the present invention is not limited to this, and it may be formed on the same substrate as the bipolar transistor, or as shown in FIG. A power transistor having a source 301, gate 31, and space 32 on the main surface of the N-type semiconductor substrate 29 and a drain 33 on the back surface can be fabricated without sharing the process with other elements.

Furthermore, in this embodiment, the DMOS transistor is
Although the description has been made using a channel transistor, the present invention is not limited thereto, and may be applied to a P-channel transistor.

<Effects of the Invention> In a DMO or S structure transistor, when a high voltage is applied between the drain and the source, the transistor becomes a first conductivity type semiconductor.

Most of the voltage is applied to the junction between the body substrate and the second conductivity type base region, and the depletion region is approximately inversely proportional to the impurity concentration ratio between the first conductivity type semiconductor substrate and the second conductivity type base region. Therefore, according to the present invention, the pace region is formed into a double structure of a shallow diffusion region with a relatively high concentration and a deep diffusion region with a relatively low concentration, so that the drain-source voltage spreads to the base region. It is possible to spread the depletion region sufficiently widely into the deep pace region with a relatively low concentration, which is effective in increasing the withstand voltage. This has the effect of restricting the spread of the depletion region inward and preventing punch-through to the source.

Furthermore, the presence of the shallow pace region with a relatively high concentration reduces the resistance of the base region, thereby improving the reduction in breakdown voltage caused by the bipolar transistor structure in the ON state of the DMOS FET.

Therefore, the present invention has high performance and high voltage resistance. This contributes to the manufacture of DMOSFETs.

[Brief explanation of the drawing]

i@1 Figure is a sectional view showing the first embodiment of the invention, Figure 2 is a sectional view showing the second embodiment of the invention, and Figure 3 is a sectional view showing the third embodiment of the invention. 01BIP type silicon substrate 14:N
-Epitaxial layer 15: P+ impurity diffusion region I6
: Thick oxide film 17: Well region 18: Base region of il 19: Gate oxide film 20: Gate electrode 21: Second space region 22: Source region (DMO3) 2
a Nidorain region (DMO8) 24. Source, drain region (CMO5N channel transistor) 25 near-x, train region (CMOSP channel transistor) 26: Electrode 27N+buried layer
28: N+ drain region 29: N-type semiconductor substrate 3o
: Source 3 Summer: Gate 32: Base 33 Nidrain agent Patent attorney Takeshi Sugiyama (1 other person) Figure 1 Figure 2

Claims (1)

[Claims] 1. FET formed on a first conductivity type semiconductor substrate
ldEffectTransistor), surrounding the source region formed by the first conductivity type impurity region,
The base region includes a second conductivity type impurity high concentration region that surrounds the source region and is formed relatively shallowly, and a second conductivity type impurity low concentration region that surrounds the second conductivity type impurity high concentration region and is formed relatively deeply. A high voltage semiconductor device characterized by comprising a concentration region.