JPH01107564A - Cooler for semiconductor device - Google Patents
Cooler for semiconductor deviceInfo
- Publication number
- JPH01107564A JPH01107564A JP62263856A JP26385687A JPH01107564A JP H01107564 A JPH01107564 A JP H01107564A JP 62263856 A JP62263856 A JP 62263856A JP 26385687 A JP26385687 A JP 26385687A JP H01107564 A JPH01107564 A JP H01107564A
- Authority
- JP
- Japan
- Prior art keywords
- bellows
- cooling
- chip
- package
- housing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000001816 cooling Methods 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 2
- 239000002826 coolant Substances 0.000 claims 2
- 230000006835 compression Effects 0.000 claims 1
- 238000007906 compression Methods 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 239000004519 grease Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 239000000498 cooling water Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005489 elastic deformation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005482 strain hardening Methods 0.000 description 1
- 239000002470 thermal conductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、冷却性能の優れた半導体モジュールの構造及
び組立方法に係り、特に、複数の半導体チップ、あるい
は、キャリアに冷却体を均等に密着させ得る冷却装置に
関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure and assembly method of a semiconductor module with excellent cooling performance, and in particular, to a method for uniformly and closely adhering a cooling body to a plurality of semiconductor chips or a carrier. The present invention relates to a cooling device that can
従来、高速データ処理装置等の半導体装置では、装置の
性能を向上させるため、素子の高集積化、並びに、実装
の高密度化が図られ、そこから発生する熱量は強制空冷
の手段等で冷却できる限界を超えてきている。Conventionally, in semiconductor devices such as high-speed data processing equipment, in order to improve the performance of the device, the elements have been highly integrated and the packaging density has been increased, and the amount of heat generated from this has been cooled by forced air cooling. I have exceeded the limits of what I can do.
このため、特に大型計算機等では、特開昭６０−１６０
１５１号公報に開示されているような液体を用いた冷却
装置が提案されている。この種の装置では、半導体チッ
プからの熱を高効率に取り除くために。For this reason, especially for large computers, etc.,
A cooling device using a liquid as disclosed in Japanese Patent No. 151 has been proposed. This type of equipment is used to remove heat from semiconductor chips with high efficiency.
両者の間を良熱伝導体で結合する必要がある。と同時に
、基板の変形等に対応できるように結合部に柔軟性をも
たる必要がある。これらの条件を満たし、かつ、最も冷
却性能を高められる構造の従来案を第４図に示す１図に
おいて、２１はハウジング、２２はフランジ、２３はベ
ローズ、２４は冷却板、２５は熱伝導グリース、２６は
半導体パッケージ、２７は低融点半田、−２８は配線基
板、２９はリードである。冷却板２４は循環されている
冷却水によって直接冷やされており、半導体チップから
発生した熱は、パッケージ容器と熱伝導グリース２５を
通って冷却板２４に伝えられる。It is necessary to connect the two with a good thermal conductor. At the same time, it is necessary that the bonding portion be flexible to accommodate deformation of the substrate. A conventional structure that satisfies these conditions and maximizes the cooling performance is shown in Figure 4, in which 21 is a housing, 22 is a flange, 23 is a bellows, 24 is a cooling plate, and 25 is thermal conductive grease. , 26 is a semiconductor package, 27 is a low melting point solder, -28 is a wiring board, and 29 is a lead. The cooling plate 24 is directly cooled by the circulating cooling water, and heat generated from the semiconductor chip is transferred to the cooling plate 24 through the package container and thermally conductive grease 25.
この場合の冷却性能は、熱伝導グリースの伝熱特性、及
び、その厚さと冷却板、及び、パッケージの伝熱特性、
冷却板から水への伝熱特性によって決定されるが、最も
大きな要因は熱伝導グリースの厚さとその特性である。In this case, the cooling performance is determined by the heat transfer characteristics of the thermal conductive grease, its thickness and cooling plate, and the heat transfer characteristics of the package.
It is determined by the heat transfer characteristics from the cooling plate to the water, but the biggest factor is the thickness of the thermal grease and its properties.
（発明が解決しようとする問題点〕
第４図の冷却構造において、冷却性能を高めるためには
、冷却板とパツケニジの間隙を小さくし、熱伝導度の悪
いグリースの厚みを極力薄くすることが必要である。こ
のため、基板のそりやパッケージのリード形状の不揃い
、あるいは、半田接合のばらつき等に起因するパッケー
ジの傾きや高さのばらつきに合わせて、冷却板の位置を
調整する必要があるが、実際問題として、冷却装置を組
立て後、多数個のものをすべて数十μｍ以下の精度で調
整することは困難である。一方、塑性加工等でつくられ
る通常のベローズでは、大きな繰返しの変形に対して長
い寿命をもたせるため、弾性変形領域を広くして変形量
を大きく採れるように降伏強度、あるいは、耐力を大き
くして用いている。(Problems to be solved by the invention) In order to improve the cooling performance of the cooling structure shown in Fig. 4, it is necessary to reduce the gap between the cooling plate and the package and to reduce the thickness of the grease, which has poor thermal conductivity, as much as possible. Therefore, it is necessary to adjust the position of the cooling plate according to variations in package tilt and height caused by board warpage, uneven package lead shapes, or solder joint variations. However, as a practical matter, after assembling a cooling device, it is difficult to adjust all the components with an accuracy of several tens of micrometers or less.On the other hand, ordinary bellows made by plastic working etc. are subject to large repeated deformations. In order to have a long life, the elastic deformation region is widened and the yield strength or yield strength is increased so that a large amount of deformation can be achieved.
このようなベローズを用いた冷却装置の場合、すべての
冷却板がパッケージの上面に接触するようにして組立て
ると、各冷却板とパッケージの初期の最大間隙差分だけ
ベローズを圧縮させた荷重が□特定のパッケージに残存
して組立てられることになる。この場合、パッケージと
配線基板の半田接続部の疲労寿命が大きく低下するとい
う問題がある。特に、半田接続部がＣＣＢ接続のように
小型化してくると増々大きな問題となってくる。In the case of a cooling device using such bellows, when assembled with all the cooling plates in contact with the top surface of the package, the load that compresses the bellows by the initial maximum gap difference between each cooling plate and the package is specified. It will remain in the package and be assembled. In this case, there is a problem in that the fatigue life of the solder connection between the package and the wiring board is significantly reduced. In particular, as solder connections become smaller, such as CCB connections, this becomes an increasingly serious problem.
他の方法として、ハウジングとベローズの継手構造を第
５図に示すように挿入する構造とし、冷却板３４を各パ
ッケージ３６に合わせた状態でハウジング３２とベロー
ズ３３を最後に接合組立てる方法が考えられるが、この
場合はパッケージ３６、あるいは、基板を損傷しないた
めに接合材料として低融点の半田材３９．あるいは、接
着剤のようなものしか用いることができず、耐食性、あ
るいは、気密性などに問題がある。Another possible method is to insert the joint structure between the housing and the bellows as shown in FIG. 5, and finally assemble the housing 32 and the bellows 33 with the cooling plate 34 aligned with each package 36. However, in this case, in order not to damage the package 36 or the board, a low melting point solder material 39 is used as the bonding material. Alternatively, only adhesives can be used, and there are problems with corrosion resistance, airtightness, etc.
本発明の目的は、半導体装置の冷却装置として配線基板
上に搭載されたチップやパッケージの高さ、あるいは、
傾きに応じてベローズ長を容易に調整可能な冷却装置及
び半導体モジュールの組立て方法を提供し、これによっ
て半導体素子の冷却性能に優れ、かつ、半田接続部に残
存する応力が小さくて疲労寿命に優れる半導体モジュー
ルを提供することにある。An object of the present invention is to reduce the height of a chip or package mounted on a wiring board as a cooling device for a semiconductor device, or to
Provides a cooling device and a method for assembling a semiconductor module in which the length of the bellows can be easily adjusted according to the inclination, thereby achieving excellent cooling performance for semiconductor elements, and low stress remaining in soldered joints, resulting in excellent fatigue life. Our goal is to provide semiconductor modules.
上記目的は、使用するべ°ローズとして塑性加工によっ
てつくられたベローズ、あるいは、圧延板を加工し溶接
や接合してつくられたベローズを一度所定の温度で焼鈍
処理したものを用いることによって達成される。The above objective can be achieved by using bellows made by plastic working, or bellows made by processing rolled plates and welding or joining them, which have been annealed at a predetermined temperature. Ru.
さらには、冷却装置を半導体装置↓こ搭載して半導体モ
ジュールを組立てる際に、ベローズを一度伸長加工した
後、冷却板をチップやチップキャリア、あるいは、パッ
ケージに押し付けて全ベローズを圧縮して塑性変形させ
、冷却板が半導体部品の背面の高さや傾きに合うような
ベローズ長補正加工して組立てることによって達成され
る。Furthermore, when assembling a semiconductor module by mounting a cooling device on a semiconductor device, the bellows are stretched once and then the cooling plate is pressed against the chip, chip carrier, or package to compress the entire bellows and cause plastic deformation. This is achieved by correcting the bellows length so that the cooling plate matches the height and inclination of the back surface of the semiconductor component and then assembling the cooling plate.
第３図は、従来のベローズのバネ特性曲線を示す、従来
のベローズ１は、弾性変形範囲を広くするため、冷間加
工によって降伏強度、あるいは、耐力を高めており、降
伏後の変位−荷重曲線も高い傾きをもっている。このた
め、従来ベローズを用いて組立てた冷却装置では、ＬＳ
Ｉチップ３やチップキャリアをＣＣＢ半田接合した半導
体基板５に冷却装置を押し付けて、ベローズを塑性変形
させて長さを調整した場合、チップに対して強い力が加
わるため、チップ３やＣＣＢ半田接合部４に亀裂等の損
傷を伴う恐れがある。また、チップ高さにδだけ差があ
った場合、塑性変形させないでＡ、Ｈのチップと冷却板
２を接触させるとＢのチップにはσの荷重が加わる。一
方、塑性変形させた場合、具体的には第３図のＡ’ 、
Ｂ’点まで変形を加えてから荷重を取り除き、Ａ、Ｂが
共にチップと冷却板２を接触させる状態にしたとき、降
伏後の変位−荷重曲線の傾き（Ａ’−Ｂ’線の傾き）が
大きいため塑性加工によるベローズ１の長の調整が十分
できず、σ′という高い荷重がＢのチップ３に加わる。Figure 3 shows the spring characteristic curve of a conventional bellows.In order to widen the range of elastic deformation, the conventional bellows 1 has its yield strength or yield strength increased by cold working, and the displacement after yielding - load The curve also has a high slope. For this reason, in conventional cooling devices assembled using bellows, the LS
When the cooling device is pressed against the semiconductor substrate 5 to which the I-chip 3 and the chip carrier are CCB-soldered and the bellows is plastically deformed to adjust the length, a strong force is applied to the chip, causing the chip 3 and the CCB-solder-bonded There is a possibility that damage such as cracks may occur in the portion 4. Further, when there is a difference in chip height by δ, when chips A and H are brought into contact with the cooling plate 2 without plastic deformation, a load of σ is applied to chip B. On the other hand, in the case of plastic deformation, specifically A' in Fig. 3,
When the load is removed after applying deformation to point B' and both A and B are in contact with the chip and cooling plate 2, the slope of the displacement-load curve after yielding (the slope of the A'-B' line) Since the length of the bellows 1 is large, the length of the bellows 1 cannot be sufficiently adjusted by plastic working, and a high load of σ' is applied to the tip 3 of B.
これに対して、焼鈍処理を施して素材を軟化させ、降伏
強度、または、耐力を下げたベローズのバネ特性曲線を
第１図に示す。焼鈍によってヤング率（変位−荷重直線
の傾き）はそれほど変化しないが、降伏強度、並びに、
降伏直後の変位−荷重直線の傾きは共に小さくなる。従
って、Ａ、 Ｂのベローズに対してＡ’、’Ｂ’点まで
変形を加えた後、荷重を取り去り、Ａ、Ｂ共にチップ３
と冷却板２が接触する状態にしたときには、σ′という
小さい荷重しかチップＢには加わらないことになる。On the other hand, FIG. 1 shows the spring characteristic curve of a bellows which has been subjected to an annealing treatment to soften the material and lower its yield strength or yield strength. Although the Young's modulus (the slope of the displacement-load line) does not change much due to annealing, the yield strength and
Immediately after yielding, the slopes of the displacement-load lines become smaller. Therefore, after deforming the bellows of A and B to points A' and 'B', the load is removed and the tip 3 of both A and B is deformed.
When the cooling plate 2 is brought into contact with the chip B, only a small load of σ' is applied to the chip B.
このように焼鈍処理を施したベローズを用いた場合には
、チップ高さに応じたベローズ長の調整が簡単に行え、
すべてのチップと冷却板の接触を良くした場合でも、チ
ップに残存する荷重を小さくできるため、半田接合部の
疲労寿命を損うことなく冷却性能の優れた半導体モジュ
ールを得ることができる。When using bellows annealed in this way, the bellows length can be easily adjusted according to the chip height.
Even when all the chips are in good contact with the cooling plate, the load remaining on the chips can be reduced, making it possible to obtain a semiconductor module with excellent cooling performance without impairing the fatigue life of the solder joints.
以下、本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図は、本発明による冷却モジュールの組立て手順を
示す図である。（ａ）の工程ではハウジング６、フラン
ジ７、焼鈍ベローズ８．冷却板９が溶接、ろう付、ある
いは、拡散接合の手段によって組立てられ、焼鈍ベロー
ズ８が引き伸ばされる。（ｂ）の工程では、他の工程で
組立てられたチップ１２と配線基板１４と半田接合部１
３から成る半導体基板に、（ａ）の工程でつくられた冷
却装置が搭載され、すべてのベローズ８が塑性変形領域
に達するまで圧縮変形させられる。その後で、冷却装置
を持ち上げて、半導体基板と離す。FIG. 2 is a diagram showing the assembly procedure of the cooling module according to the present invention. In the step (a), the housing 6, flange 7, annealed bellows 8. The cooling plate 9 is assembled by means of welding, brazing or diffusion bonding, and the annealed bellows 8 is stretched. In the step (b), the chip 12, the wiring board 14, and the solder joint 1 assembled in another step are assembled.
The cooling device made in step (a) is mounted on the semiconductor substrate 3, and all the bellows 8 are compressively deformed until they reach the plastic deformation region. Thereafter, the cooling device is lifted and separated from the semiconductor substrate.
最後に（Ｃ）の工程で、チップ１２と冷却板９の間に熱
伝導性の良いグリース１９を挿入し、ハウジング６と配
線基板１４の間隙が、各チップ１２と冷却板９が完全に
接触し、かつ、チップ１２に加わる荷重が最も小さくな
る高さに調整し、基板周辺に気密封止用の側壁１８を配
置して低融点半田１６．１７で封止して組立てている。Finally, in step (C), grease 19 with good thermal conductivity is inserted between the chips 12 and the cooling plate 9, and the gap between the housing 6 and the wiring board 14 is adjusted so that each chip 12 and the cooling plate 9 are in complete contact with each other. The height is adjusted so that the load applied to the chip 12 is minimized, side walls 18 for airtight sealing are placed around the substrate, and the assembly is performed by sealing with low melting point solder 16 and 17.
本実施例によれば、水を循環させる冷却装置を溶接やろ
う付、あるいは、拡散接合等の高品質継手で気密に組立
てた後で、ベローズ長を容易にチップの高さや傾きに合
せて調整可能であるため、気密信頼性及び耐食信頼性に
優れた冷却装置を用いて、チップの冷却性能が高く、し
かも、半田接合部の疲労寿命を劣化させないマルチチッ
プの半導体モジュールを容易に得ることができる。また
、本実施例によれば、冷却装置と半導体基板を別々の工
程でつくり、両者の組立工程も容易であるため、生産性
の向上が図れ、製造コストを下げることができる。According to this embodiment, the bellows length can be easily adjusted to match the height and inclination of the chip after the water-circulating cooling device is airtightly assembled using high-quality joints such as welding, brazing, or diffusion bonding. Therefore, it is possible to easily obtain a multi-chip semiconductor module that has high chip cooling performance and does not deteriorate the fatigue life of the solder joints by using a cooling device with excellent airtight reliability and corrosion-resistant reliability. can. Furthermore, according to this embodiment, the cooling device and the semiconductor substrate are manufactured in separate processes, and the assembly process for both is easy, so productivity can be improved and manufacturing costs can be reduced.
第６図は、本発明による冷却装置を用いて各種パッケー
ジ寸法の半導体基板を冷却する半導体モジュールの断面
構造を示す。配線基板４８には寸法の異なるメモリパッ
ケージ４５と論理ＬＳＩのパッケージ４６が半田接合４
７により搭載されている。冷却装置のパッケージ冷却部
は、冷却水の供給・排出口をもつ冷却ブロック４２が二
個のベローズ４１によってハウジング４０に連結されて
おり、冷却ブロック４２内の流水通路には底部から流れ
の方向に沿った微細なフィン４３が設けられている。給
水口４９から入った冷却水は、各冷却ブロックを通過し
た後、排水口５０から排出される。ここで用いている焼
鈍ベローズ４１は拡散接合によって製造されており、ハ
ウジング４０及び冷却ブロック４２との組立てもベロー
ズ製造時に拡散接合によって同時に組立てられている。FIG. 6 shows a cross-sectional structure of a semiconductor module in which semiconductor substrates of various package sizes are cooled using a cooling device according to the present invention. A memory package 45 and a logic LSI package 46 of different sizes are soldered together 4 on a wiring board 48.
It is installed by 7. In the package cooling part of the cooling device, a cooling block 42 having a cooling water supply/discharge port is connected to a housing 40 by two bellows 41, and a water passage in the cooling block 42 is provided with a water passage from the bottom in the direction of flow. Fine fins 43 are provided along the line. Cooling water entering from the water supply port 49 is discharged from the drain port 50 after passing through each cooling block. The annealed bellows 41 used here is manufactured by diffusion bonding, and the housing 40 and cooling block 42 are assembled together by diffusion bonding at the same time when the bellows is manufactured.
図中４４は熱伝導グリース、５１は水流である。各ベロ
ーズの山数、及び、肉厚は同一仕様である。In the figure, 44 is thermally conductive grease, and 51 is a water stream. The number of threads and wall thickness of each bellows have the same specifications.
冷却装置と半導体基の組立ては、第２図で実施したのと
同じプロセスで行なっている。The assembly of the cooling device and the semiconductor substrate is carried out using the same process as carried out in FIG.
本実施例によれば、冷却装置の各接合部が拡散接合によ
って接合されているため、接合部の強度耐食性、気密性
等で信頼性の高い冷却装置となっている。また、パッケ
ージの寸法が異なりパッケージ上面の高さが数Ｉ程度と
大きく違っている場合でも、冷却ブロックの高さを簡単
なプロセスで容易にパッケージ面に合せることができる
ため、半導体モジュールの組立性を向上でき、生産性の
向上、及び、製造コストの低減を図ることができる。ま
た、パッケージの冷却性能並びに半田接合部の疲労寿命
がいずれも良好な半導体モジュールを得ることができる
等の効果がある。According to this embodiment, since each joint of the cooling device is joined by diffusion bonding, the cooling device has high reliability due to strength, corrosion resistance, airtightness, etc. of the joint. In addition, even if the dimensions of the package differ and the height of the top surface of the package differs greatly by several meters, the height of the cooling block can be easily adjusted to the package surface with a simple process, making it easier to assemble the semiconductor module. This makes it possible to improve productivity and reduce manufacturing costs. Further, it is possible to obtain a semiconductor module having good cooling performance of the package and good fatigue life of the solder joints.
本発明によれば、半導体チップの冷却性能に優れ、かつ
、半田接続部に残存する荷重が小さくて疲労寿命に優れ
た半導体モジュールが得られる。According to the present invention, it is possible to obtain a semiconductor module that has excellent cooling performance for semiconductor chips, has a small load remaining in the solder joints, and has an excellent fatigue life.
第１図は、本発明の一実施例の焼鈍ベローズの変位−荷
重特性曲線図、第２図は、半導体モジュールの組立手順
図、第３図は、従来ベローズの変位−荷重特性曲線図、
第４図は半導体モジュールの従来構造図、第５図は別の
半導体モジュールの従来構造を示す図、第６図は本発明
による冷却装置を用いた半導体モジュールの断面図であ
る。
１・・・ベローズ、２・・・冷却板、３・・・チップ、
４・・・半田接合部、５・・・配線基板、６・・・ハウ
ジング、７・・・Ｍ ｌ 図
Ｍ ２ 図
第 ３ 圃
Ｍ ４ 図FIG. 1 is a displacement-load characteristic curve diagram of an annealed bellows according to an embodiment of the present invention, FIG. 2 is an assembly procedure diagram of a semiconductor module, and FIG. 3 is a displacement-load characteristic curve diagram of a conventional bellows.
FIG. 4 is a diagram showing a conventional structure of a semiconductor module, FIG. 5 is a diagram showing another conventional structure of a semiconductor module, and FIG. 6 is a sectional view of a semiconductor module using a cooling device according to the present invention. 1... Bellows, 2... Cooling plate, 3... Chip,
4...Solder joint, 5...Wiring board, 6...Housing, 7...Ml Figure M2 Figure 3 Field M4 Figure
Claims (1)
個別に液冷できる構造で、冷媒を供給排出するダクトを
設けたハウジングと、前記ＬＳＩチップあるいは前記Ｌ
ＳＩチップを搭載したチップキャリアに接触あるいはは
んだ接合して熱を冷媒に伝達する冷却ブロックと、前記
ハウジングと前記冷却ブロックをフレキシブル、かつ、
気密性を保つて連結するベローズからなり、前記ベロー
ズに焼鈍処理を施こしたことを特徴とする半導体装置の
冷却装置。 ２、特許請求の範囲第１項において、前記ベローズを一
度伸長加工した後、前記冷却ブロックを前記基板に搭載
した前記ＬＳＩチップ、あるいは前記チップキャリアに
押し当て、全ベローズが塑性変形領域に達するまで圧縮
変形させることにより、ベローズ長及び前記冷却ブロッ
クの傾きを対応する前記ＬＳＩチップあるいは前記チッ
プキャリアの高さ及び傾きに合せて加工したことを特徴
とする半導体装置の冷却装置。[Scope of Claims] 1. A housing having a structure capable of individually liquid cooling a plurality of LSI chips mounted on a multilayer wiring board, including a housing provided with a duct for supplying and discharging a coolant, and the LSI chips or the LSI chips.
a cooling block that transfers heat to a coolant by contacting or soldering to a chip carrier on which an SI chip is mounted, and the housing and the cooling block are flexible, and
1. A cooling device for a semiconductor device, comprising a bellows connected while maintaining airtightness, the bellows being annealed. 2. In claim 1, after the bellows is once stretched, the cooling block is pressed against the LSI chip mounted on the substrate or the chip carrier until all the bellows reach a plastic deformation region. A cooling device for a semiconductor device, characterized in that the length of the bellows and the inclination of the cooling block are processed to match the height and inclination of the corresponding LSI chip or the chip carrier by compression deformation.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62263856A JPH01107564A (en) | 1987-10-21 | 1987-10-21 | Cooler for semiconductor device |
| US07/258,609 US4996589A (en) | 1987-10-21 | 1988-10-17 | Semiconductor module and cooling device of the same |
| KR1019880013523A KR890007419A (en) | 1987-10-21 | 1988-10-17 | Semiconductor module and its cooling device |
| DE3835767A DE3835767A1 (en) | 1987-10-21 | 1988-10-20 | COOLING DEVICE FOR SEMICONDUCTOR MODULE |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62263856A JPH01107564A (en) | 1987-10-21 | 1987-10-21 | Cooler for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01107564A true JPH01107564A (en) | 1989-04-25 |
Family
ID=17395184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62263856A Pending JPH01107564A (en) | 1987-10-21 | 1987-10-21 | Cooler for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01107564A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007145352A (en) * | 2005-11-25 | 2007-06-14 | Kao Corp | cap |
| US7663883B2 (en) | 2004-02-13 | 2010-02-16 | Fujitsu Limited | Heat transfer mechanism, heat dissipation system, and communication apparatus |
-
1987
- 1987-10-21 JP JP62263856A patent/JPH01107564A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7663883B2 (en) | 2004-02-13 | 2010-02-16 | Fujitsu Limited | Heat transfer mechanism, heat dissipation system, and communication apparatus |
| JP2007145352A (en) * | 2005-11-25 | 2007-06-14 | Kao Corp | cap |
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