JPH01105298A - Matrix display device - Google Patents

Abstract

PURPOSE: To make the capacity of a storage means small and prevent a disturbance, such as a step-out, to a display image by providing a storage means which stores pixel information as signals in pixel units and reads and output pixel information of one line to a driving circuit in synchronism with the scanning of a scanning circuit. CONSTITUTION: A 1st shift register 5 and a 1st latch circuit 3 form a 1st driving circuit 9 for one column and a 2nd shift register 6 and a 2nd latch circuit 4 form a 2nd driving circuit 10 for one line as well. A storage means (delay circuit 7) is provided which stores the pixel information sent sequentially according to positions on a screen as signals in pixel units and reads and outputs pixel information of one line to driving circuits 9 and 10 in synchronism with the scanning of the scanning circuit. Consequently, low time-division (one-half the number of lateral electrodes) driving is enabled even with a video signal, etc., which is sent sequentially without coding display information, the capacity of the storage means 7 may be small, and synchronism with the display scanning is obtained, so the display image is not disordered.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Field of Application The B11N is particularly related to an NT liquid crystal matrix display device whose screen is divided into upper and lower halves.

Conventional technology Conventionally, when driving a liquid crystal in a time division manner, the responsiveness of the liquid crystal is poor, so a low time division ratio of 1/9 to 1/16 duty is used.
It is said that it is not suitable for graphic display because it requires a drive.

The ninth way to improve n is generally to reduce the duty of the liquid crystal and to devise an electrode pattern. By facing each other, two pixels can be displayed simultaneously and the display period can be quadrupled.However, in this case, there is a drawback that the wiring of the vertical electrodes Y1 and Y1' is complicated.The purpose of reducing the magnification duty is to For example, it is possible to divide the busy screen into multiple parts according to JP-A-49-342QE! It is shown in the official gazette and has coded and refined display information, and the signal is distributed to the divided column part w1 circuit at the timing when the display 1# information is converted into pixel information by a character signal generator, and the duty is set. 1/(number of divisions). However, this method requires a character signal generator that can take out pixel information of a predetermined row at any time, as well as a large-capacity random access memory. However, it cannot be used as a display device for devices that sequentially transmit pixel information such as video signals.

2) Problems to be solved by the invention The major invention is to provide a matrix display device that eliminates the above-mentioned disadvantages. The pixel information is stored as a pixel-by-pixel signal, and the pixel information is sent sequentially according to the position of one screen for each display device button that is simultaneously scanned in the same direction. The memory means that outputs the data to the readout circuit is of the order of magnitude.

(e) Effect: This allows the display information to be encoded and sent in multiple orders, such as a video signal, and can be used in a low time division (accumulation count/Z), and the storage means can be used at least as well. It requires only a small capacity for the number of pixels equivalent to half a screen, and since it is synchronized with display scanning, no sludge appears on the displayed image.

The second reason for implementation is that in Figure 1, which is a prescribed block diagram explaining the basic operation of the great invention, (1) is a liquid crystal display panel.
Electrode & (x1~X+) and vertical electrode (Y\~Y;1) (Yl
The liquid crystals (3 not shown) located between Y11) and Y11) are each displayed as a pixel. The horizontal electrodes (X1 to XS) are divided into two groups of four trees on the top and bottom, of which (Xl) and (x6)
.

(XI (' (X6), (XI) (X7)
, (X4) (' (XI) H-scanning circuit together!2
Connected to 1.

Vertical [& (Yl ~ Yll) (Y'l - Y'll)
t4 each 1st. The latch circuit +31141 connected to the second latch circuit l13f3114+ is connected to the first and second shift registers +51+61, and the first shift register (5) and the first latch circuit Wt (31) are connected to 1 drive circuit (forming the second shift register fi
+ and the 1st Ratsuchiro 14) G and the 2nd line of the same line
9 circuits +1α are formed.

(7) is a delay circuit, which is half of all pixels, 8×11÷2
=44 pixel information is output after a predetermined time delay n. This circuit (71 is composed of a storage means such as a 44-bit shift register, for example), and shifts its contents in synchronization with a clock signal (CP).

FIG. 3 is a timing chart showing the operation of FIG. 2, and the operation will be explained below. Signal (al Lr1 pixel information, display signal. If the signal lights up all pixels 8Xll = 88, all the signals will be high during one display cycle (TI), and if the entire screen does not light up, all will be low (T2). Normally, characters, numbers, etc. are displayed using the combination of high and low, and if the number of pixels is large, a graphic display is performed.This pixel information is sent from the upper left to the lower right of the screen.

The signal (a) is applied to the first shift register (5) and the delay circuit [7], and is shifted in synchronization with the clock pulse (cp). The contents of the first shift register (5 + C are generated from 11 shift stages) are updated every 11 pulses of the clock pulse (CP), but the latch signal (b) is sent to the latch circuit (31) every 11 pulses. Therefore, each time the output of 11 is applied to the latch circuit 131, Vci is memorized.
It is held for the next latch signal (b). In other words, every 11 pieces of pixel information is latched 1i5 times at a time as information for one time.
+3! It will be stored in the memory. Second shift register (61 and @
The latch circuit No. 2 (41) operates in the same manner.

The signal 9(a) is transmitted through a delay circuit 17) for 44 pixels.

In other words, the signal is delayed by 4 lines (C half a screen) and becomes a signal. Until the output of the delay circuit (7) comes out (1°0).

The first shift register; 51 and the class I launch circuit (3
) between tpA (TO5, electrode (Y
The scanning circuit (2
From 1 onwards, only a low signal for scanning is output, but virtually no display is performed.

Pixel information is given to the second shift resistor 161 from the period (delay circuit 17 in the TO mode), that is, 44 pixels, that is, half screen delay A7, and the signal (a), that is, the screen information of the lower half, is given to the second shift register 161 at the same time. Give and receive.Followed by period (TO)
At the end of 1, the pixel information of the 5th row from the top is shifted into the Ic@l shift register 111 by one shift f'L, and the pixel information of the 1st row from the top is shifted into the second shift register (61). - After the shift of the property, the pixel information of the @1 line and the 5th line is stored in the second latch circuit t41 and the first latch path (31) by the latch as(a), and the subsequent scanning signal ( dl) displays -lines.

Shift register +fil f61 during scanning signal (dl)
The pixel information of @6th row and 2nd row is shifted by n, after shifting by - rows, the latch signal (- is stored in @1.2nd latch time lid +31141 and then shifted by one row of °C) Period (C2) K is displayed.Sequentially, the 7th line and @3rd line are displayed, the 8th and 4th lines are displayed, and the @ of signal (a) is displayed for more than one display period. The first pixel information (T1) is displayed during the display period (al).Similarly, the second pixel information (T2) is displayed during the display period (C2), and thereafter the display is repeated (repeatedly). Ruru.

In the above explanation, the output of the scanning circuit 12) is low, and the first,
The liquid crystal is designed to light up when the output of the second launch circuit +31+41 is high, but it would be fine if the pixels had polarity like a light emitting diode matrix.It is desirable for the liquid crystal itself to be AC m motion, so It is necessary to divide the display period into two, to change the scanning signal (ax-C4) from low to low, and to provide a level inversion circuit f2 so that the latch circuit +31+41 changes from high to low. FIG. 4 is a circuit diagram showing an example of a level inverting circuit, in which the latch circuit 13+1
Let one output of 4+ be (f), (AI) (A2) is an andgoo), (INI)-t inverter.

Next, an embodiment of the great invention will be described. FIG. 5 is a block diagram for lighting for the entire period, and the same reference numeral 8- is used for the same parts as in the Z diagram. FIG. 6 is a timing chart explaining one of the works shown in @5.

The output of the delay circuit ()) is Antogame) (A4) (AI
S) K given ra 几・signal (a) is also and goo)
(Aa) (As)! It is given. The AND gates (A4) and (A6) are opened and closed by the signal (β), and the AND gates (Aa) and (As) are opened and closed by the signal (m11) via the inverter (rN2), which is an inverted signal of the signal (g). The signal (hl) given to the first shift register (5) via the (ORI)
The lower half of the screen is repeated and becomes the f'L7'j signal, and the second
．． Shift register (6) K given nru signal 8 (h2) i
j The lower half of the screen becomes the repeated -r belief.

As described above, in the tree embodiment, the sequential display is repeated every half screen on both the upper and lower sides, thereby solving the drawbacks of the first embodiment. However, the scanning circuit (8) is arranged to output a scanning signal (11q4).

The delay circuit (7) in the above example is not limited to a shift register, but a delay line, random access memory, etc. can also be used if synchronization is taken into account.

When lighting with a te liquid crystal and displaying not only the contrast but also the intermediate tone, it is possible to use the analog signal storage delay element 1, for example, a 1ft BBD element, as a KFi delay circuit (7).

g) Effects of the invention According to the above, wiring? without making it complicated.

Furthermore, the timing for reading out pixel information from the storage means (delay circuit) can be easily obtained, and the capacity of the storage means is relatively small even if it is called pixel memory.

Even if the number of pixels increases, it is not necessary to drive the display panel at an unnecessarily high duty ratio, and disturbances such as synchronization with one displayed image do not occur.

[Brief explanation of the drawing]

1a is a pattern diagram of a conventional matrix electric object, 2nd
The figure is a block diagram for explaining the basic work of the present invention, Figure 3 is a timing chart showing the operation of Figure 2, Figure 4 is a diagram showing the level reversal route, and Figure 5 is a large FIG. 1 is a block diagram showing an embodiment of the invention. FIG. 6 is a timing chart of FIG. 5. ill is the liquid crystal display panel, +2181 is the scanning circuit,
+31 (41 is the latch circuit Wt-+51f8+i shift register, (7) is the delay circuit, and 1911α is the drive circuit. Applicant: 1 other person from Sanyo Electric Co., Ltd. Representative Patent Attorney Hisashi Nishino (1 other person) Figure 1 Figure 2 Pier Figure 3-C11iC2''''-1

Claims (1)

[Scope of Claims] 1) substantially orthogonal to each of the first and second horizontal electrode groups so that the intersection with the first and second horizontal electrode groups provided separately above and below the screen forms a pixel; a display panel for matrix display having vertical electrode groups placed above and below the screen; a scanning circuit that simultaneously scans each of the first and second horizontal electrode groups in the same direction; In a matrix display device that has first and second drive circuits that are connected to the top and bottom and each store and output pixel information for one row, pixel information is sent sequentially from the top to the bottom of the screen. is stored as a pixel-by-pixel signal, and 1 is synchronized with the scanning of the scanning circuit.
A matrix display device comprising a storage means for reading and outputting pixel information for a row to the drive circuit.