JPH01103937U - - Google Patents
Info
- Publication number
- JPH01103937U JPH01103937U JP19781287U JP19781287U JPH01103937U JP H01103937 U JPH01103937 U JP H01103937U JP 19781287 U JP19781287 U JP 19781287U JP 19781287 U JP19781287 U JP 19781287U JP H01103937 U JPH01103937 U JP H01103937U
- Authority
- JP
- Japan
- Prior art keywords
- volume
- error
- circuit
- digital audio
- parity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図はこの考案の一実施例によるデイジタル
音声復調デイジタル音声復調回路を示すブロツク
図、第２図は従来のデイジタル音声復調回路を示
すブロツク図である。
１……ＱＰＳＫ検波出力の入力端子、２……デ
イマルチプレクサ、３……パリテイエラー検出回
路、５……Ｄ／Ａコンバータ、７……音声コント
ロール回路、９……アンプ、１２……音量制限ス
イツチ、１６……エラーカウンタ、１７……音量
制限回路制御信号。なお、図中の同一符号は同一
または相当部分を示す。
FIG. 1 is a block diagram showing a digital audio demodulation circuit according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional digital audio demodulation circuit. 1...Input terminal for QPSK detection output, 2...Day multiplexer, 3...Parity error detection circuit, 5...D/A converter, 7...Audio control circuit, 9...Amplifier, 12...Volume limit Switch, 16...Error counter, 17...Volume limit circuit control signal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
イエラーを検出するパリテイエラー検出回路と、
この検出回路による検出パリテイエラーの回数を
計数してエラー頻度を計測するエラーカウンタと
、このエラーカウンタによるエラー頻度が所定の
レベル以上になつたとき音声コントロール回路へ
の音量制御信号の入力を音量が小さくなるように
制御する音量制限回路とを具備したことを特徴と
するデイジタル音声復調回路。 a parity error detection circuit for detecting parity errors in the digital audio day multiplexer;
An error counter measures the error frequency by counting the number of parity errors detected by this detection circuit, and when the error frequency by this error counter exceeds a predetermined level, a volume control signal is input to the audio control circuit. 1. A digital audio demodulation circuit comprising: a volume limiting circuit for controlling the volume so that the volume is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19781287U JPH01103937U (en) | 1987-12-26 | 1987-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19781287U JPH01103937U (en) | 1987-12-26 | 1987-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01103937U true JPH01103937U (en) | 1989-07-13 |
Family
ID=31488346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19781287U Pending JPH01103937U (en) | 1987-12-26 | 1987-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01103937U (en) |
-
1987
- 1987-12-26 JP JP19781287U patent/JPH01103937U/ja active Pending
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