JPH01102674A - Multi-processor control system - Google Patents

Abstract

PURPOSE:To minimize the deterioration of the processing speed of a multi- processor control system by securing such a constitution where a medium-speed microprogram taking a degenerating operation into consideration is set resident when an initial microprogram is loaded and a working microprogram is automatically switched for operation via the simple hardware even when a secondary processor has abnormality. CONSTITUTION:A secondary processor starting microprogram 21 is stored in a control storage 3 together with a secondary processor substitute microprogram 22 which performs the substitute degeneration processing to the secondary processor function via a main processor 5 only against the occurrence of an unrecoverable hardware fault of a secondary processor 10. Then the subsequent microaddresses are switched by the fault report signal received from the processor 10. An instruction received from the software is not branched out to the start part of the processor 10 at the conversion of microaddresses and branched out automatically to the storing area of the microprogram 22 for succession of the processing execution. In such a way, a degenerating operation is carried out without causing much deterioration of the processing speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a control method for a multiprocessor system, and in particular to a multiprocessor control method suitable for degenerate system operation by automatic microaddress switching in the event of a subprocessor failure. It is related to.

[Conventional technology]

Although the present invention is functionally different, it is
50 r Microprogram control data processing It is a multiprocessor system similar to that used by everyone, and when started by the main processor, the sub-processor is operated to perform high-speed processing on specific instructions.

An example of a conventional multiplex four processor control system is
0-129845 "Control method for information processing equipment".

JP-A-59-114637 r Data Processing Device" and other related methods can be found. JP-A-59-114637
In the data processing method described in No. 129845, in which the main processor alone performs data processing when a failure occurs on the sub-processor, if an unrecoverable hardware error occurs in the sub-processor, the main After the processor transfers information between the control memories, the main processor performs independent control in the other control memory according to the start address on the old control memory, but it is stopped once before re-execution and the 5th time starts. Up until now, procedures such as migration of information in the control memory and control have become complicated.

Furthermore, in Japanese Patent Application Laid-Open No. 59-114637, microprograms for sub-processor operation and disconnection operation are arranged in an overlay structure in control memory, and one normal control memory is stored according to the microaddress modification register (pace register). By using a method that modifies the entire address (shifting the address), the amount of hardware for the address determination circuit increases, resulting in a somewhat large-scale design.
It had to be Mono K.

[Problems to be Solved by the Invention] The above-mentioned conventional technology does not take into account the simplification of system migration during degraded operation, such as the need to temporarily stop the subprocessor and transfer control memory amount information when there is a failure. In some cases, the amount of hardware required for sub-processor separation processing has not been sufficiently considered.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to continue degenerate operation when a subprocessor is abnormal using a minimum amount of hardware and without stopping the system.

[Means for solving problems]

The above purpose is to use SRAM technology, which has been increasing in capacity in recent years, as a control memory, to store a microprogram for starting a sub-processor, and to prevent the occurrence of an irrecoverable hardware failure in the sub-processor by using only the main processor. A microprogram for alternative degradation processing of the subprocessor function is also kept resident, and the subsequent microaddresses are switched in response to a failure report signal from the subprocessor, and instructions from the software are branched to the subprocessor startup part when converting the microaddress. This is achieved by automatically branching to one alternative microprogram storage area and continuing execution of the process.

[Effect]

The multiprocessor control method according to the present invention connects a subprocessor having a control memory and a microprogram sequencer within its own unit to a main processor,
It decodes the value of the microaddress sent from the main processor and starts processing if it is within a specific address range.When the subprocessor finishes processing an instruction, the subprocessor reports completion to the main processor, and at the same time the subprocessor It also reports whether an unrecoverable hardware failure has occurred within the processor.

When the main processor receives an error report from the sub-processor, it switches the micro-address sent to the sub-processor to generate a micro-address as a result of the primary instruction decoding, makes it unselected (disconnected state), and controls within the main processor. The address of the replacement microprogram for the cicada in memory is selected, and the system can be continued without interruption by medium-speed microprogram processing instead of low-speed processing by the software interpreter.

〔Example〕

An embodiment of the present invention will be explained below with reference to the drawings.

FIG. 1 is a schematic diagram of a microprogram-controlled multiprocessor system according to an embodiment of the present invention. As shown in FIG. 1, a main processor 5 and a sub-processor 10 are
It has control memories 3 and 8 for storing microinstructions that control the respective operations, and executes microinstructions read out according to the addresses sequentially indicated by the microsequencers 1 and 6.

The control memory 3 that stores microinstructions for the main processor is as shown in FIG. 2: (1) Only the main processor 5 is used to execute instructions. Or main processor 5. Basic unit 20 that performs processing when an abnormality occurs due to execution of the subprocessor 10
．． (2) microprogram storage area 21 for subprocessor startup, which is used when an instruction uses the subprocessor 10 in instruction decoding, and (3) when an unrecoverable failure occurs in the subprocessor. It is composed of a rigid processor-alternative microprogram storage area 22 for degeneration, which combines and executes only the functions of the main processor without operating the processor.

Activation of the sub-processor and degeneracy operation when an error occurs will be explained with reference to FIGS. 1 to 3.

Instructions issued by software are sent to the subprocessor 10.
If the instruction uses
A branch is made to any of the sub-processor starting micro areas 21 (100) to (101).

At the same time, the address detection unit 7 on the sub-processor side recognizes the instruction as one that uses the sub-processor 10, activates the sub-processor side micro in the 1 control memory 8, and thereafter the instruction is processed by the micro-sequencer 6 on the sub-processor side. When the instruction processing is completed and the completion of instruction processing is reported to the main processor 5, whether or not an unrecoverable failure has occurred in the republican sub-processor is also reported to the main processor 5 via the error report line 11. If there is nothing, the next instruction is decoded and further processing continues. However, if an unrecoverable error occurs during instruction processing in the sub-processor 10, an error is returned from the sub-processor 10 via the error report line 11. By the error signal,
The sub-processor error flag 12 on the main processor 5 side is set, and the microaddress output from the microsequencer 1 is automatically set by a simple circuit combining an AND circuit and an exclusive OR circuit as shown in FIG. When switching occurs and an instruction to use the subsequent processor 10 is issued, the bit 23 indicated by C8AD11-PL is inverted for the addresses (10X) and (IIX), and the microprogram storage area 21 for starting the subprocessor is inverted. By branching the instructions to be branched to the subprocessor alternative microprogram storage area 22 that is kept resident for degeneracy, the functions of the main processor 5 are combined to optimize the processing of instructions to be processed by the subprocessor 10. By having only the main processor 5 execute the processing, the system will not be stopped even when the sub-processor 5 is abnormal, and the processing speed will not be significantly reduced as would be the case when using a software interpreter.

Instruction processing can be continued through degraded operation.

In this way, by effectively utilizing SRAM, which has been increasing in capacity in recent years, and using elements with a depth of 16 KB or more, it is now possible to reload and use medium-speed microprograms from an external storage medium when a subprocessor error occurs. In the case of a multiprocessor system, which was unavoidable, a medium-speed microprogram designed for degenerate operation is kept resident at the time of initial microprogram load, and even if a subprocessor fails, simple hardware can automatically execute the microprogram. It becomes possible to switch between programs and provide a multiprocessor system with minimal reduction in processing speed.

〔Effect of the invention〕

According to the present invention, even in the event of an unrecoverable hardware failure in a sub-processor, the running system does not have to be stopped, the sub-processor is isolated using the minimum necessary node hardware, and the sub-processor is Although the speed is low, it is possible to execute the most suitable microprogram with one alternative microprogram without having to microload the control memory again, and there is no significant reduction in processing speed caused by the software interpreter, which has the effect of allowing degenerate operation. .

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a microprogram-controlled multiprocessor system that is an embodiment of the present invention;
This figure is a diagram for explaining switching to an alternative microprogram address, and FIG. 3 is a diagram showing a circuit for switching the microprogram address. 2...Address switching section, 3...Control memory. 5... Main processor, 7... Address detection unit. 8... Control memory, 10... Sub-processor. 11...Error reporting theory. 12...Sub-processor error flag.

Claims (1)

[Claims] 1. The main processor has a microprogram-controlled main processor and a microprogram-controlled sub-processor, and the main processor has a first control memory that stores a microprogram for the main processor and a microprogram for activating the sub-processor. In a multiprocessor system, the sub-processor is activated by the main processor, performs processing under the control of a microprogram stored in a second control memory, and reports the results to the main processor. is provided with a microprogram for substituting the processing of the sub-processor in a first control memory, and a micro-program for starting the sub-processor when the main processor receives a report of a failure from the sub-processor is stored in the first control memory. A control method for a microprocessor, characterized in that the alternative microprogram is executed by switching an address in a control memory.