JPH0110030Y2 - - Google Patents
Info
- Publication number
- JPH0110030Y2 JPH0110030Y2 JP1982130087U JP13008782U JPH0110030Y2 JP H0110030 Y2 JPH0110030 Y2 JP H0110030Y2 JP 1982130087 U JP1982130087 U JP 1982130087U JP 13008782 U JP13008782 U JP 13008782U JP H0110030 Y2 JPH0110030 Y2 JP H0110030Y2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- fet
- source
- antenna input
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000035945 sensitivity Effects 0.000 claims description 21
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000009429 electrical wiring Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Description
【考案の詳細な説明】
〈本考案の技術分野〉
本考案はラジオ受信機の同調感度設定回路に関
するものである。[Detailed Description of the Invention] <Technical Field of the Present Invention> The present invention relates to a tuning sensitivity setting circuit for a radio receiver.
〈従来技術〉
従来のラジオ受信機における同調感度の切換制
御は、例えば、フロントエンドと中間周波増幅器
との間に設けたDX−LOCAL間で可変な可変抵
抗器或いはDX／LOCALの切換スイツチの操作
により直接制御する構成となつているため、信号
ラインの引き回し、及び同調感度設定用のDX−
LOCAL回路の挿入等によつて感度低下を起す等
種々のトラブルを引き起こす欠点を有している。<Prior art> Tuning sensitivity switching control in conventional radio receivers is performed, for example, by operating a variable resistor between the front end and the intermediate frequency amplifier that is variable between DX and LOCAL, or by operating a DX/LOCAL switch. Since it is configured to be directly controlled by the DX-
It has the disadvantage of causing various troubles such as a decrease in sensitivity due to the insertion of a LOCAL circuit.
〈本考案の目的〉
本考案はこのような従来のラジオ受信機におけ
る問題点に鑑みて考案されたものであり、ラジオ
受信機におけるアンテナとフロントエンドのRF
アンプとの間のアンテナ入力回路にデユアルゲー
トのFET（電界効果トランジスタ）と感度設定器
としての可変抵抗器又は切換スイツチを設け、高
周波領域におけるFETの持つ優位性に着目して、
斯るFETのゲートをDC電圧で制御することによ
りFETを減衰器として利用し、アンテナ入力信
号を制御して同調感度の設定をせんとするもので
ある。<Purpose of the present invention> The present invention was devised in view of the problems in conventional radio receivers.
The antenna input circuit between the amplifier and the antenna is equipped with a dual-gate FET (field effect transistor) and a variable resistor or switch as a sensitivity setting device, focusing on the superiority of FETs in the high frequency range.
The FET is used as an attenuator by controlling the gate of the FET with a DC voltage, and the antenna input signal is controlled to set the tuning sensitivity.
〈本考案の構成〉
以下、本考案の一実施例を添付図面に従つて詳
細に説明する。<Configuration of the present invention> An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
第１図は本考案に係る同調感度設定回路を備え
たラジオ受信機の要部の電気的結線図にして、図
中１は図示しないアンテナからのアンテナ入力信
号を受け入れるアンテナ入力端子、２はゲートが
２つある、即ち、デユアルゲートの電界効果トラ
ンジスタ（以下、FETと云う）にして、第１の
ゲートG1は上記アンテナ入力端子１にコンデン
サC1を介して接続されると共に抵抗R2を介して
定電圧源＋Ｂに接続されている。 Figure 1 is an electrical wiring diagram of the main parts of a radio receiver equipped with a tuning sensitivity setting circuit according to the present invention, in which 1 is an antenna input terminal that receives an antenna input signal from an antenna (not shown), and 2 is a gate. There are two dual-gate field effect transistors (hereinafter referred to as FETs), and the first gate G1 is connected to the antenna input terminal 1 via a capacitor C1 and a resistor R2 . It is connected to a constant voltage source +B via.
又、ドレーンＤはコンデンサC4を介してラジ
オ回路のフロントエンド部におけるRFアンプ３
に接続されると共にチヨークコイルL1を介して
上記定電圧源＋Ｂに接続されている。 In addition, the drain D is connected to the RF amplifier 3 in the front end section of the radio circuit via the capacitor C4 .
It is also connected to the constant voltage source +B via the chiyoke coil L1 .
又、第２のゲートG2は抵抗R1，R4及び感度設
定器としての可変抵抗器VOLを介して上記定電圧
源＋Ｂに接続されると共に抵抗R5、コンデンサ
C2を介してアースされている。 The second gate G 2 is connected to the constant voltage source +B via resistors R 1 and R 4 and a variable resistor V OL as a sensitivity setting device, and is also connected to the constant voltage source +B through resistors R 5 and a capacitor.
Grounded through C2 .
又、ソースＳは抵抗R6を介して上記定電圧源
＋Ｂに接続されると共に抵抗R7とR8の直列回路
とコンデンサC3を介してアースされている。 Further, the source S is connected to the constant voltage source +B via a resistor R6 , and is grounded via a series circuit of resistors R7 and R8 and a capacitor C3 .
そして、又、このソースＳは上記抵抗R7とR8
間に中点にコレクタ端子を接続した制御用トラン
ジスタTrのオン、オフで即ち、AM時とFM時で
アースとの間の抵抗値を切り換えられることによ
りソース電圧VSを変化させられ、上記可変抵抗
器VOLによる感度切換の可変範囲を変化させるべ
く成つている。 Also, this source S is the resistor R 7 and R 8
By turning on and off the control transistor Tr, whose collector terminal is connected to the midpoint between them, the resistance value between ground and ground can be changed between AM and FM, thereby changing the source voltage VS. It is designed to change the variable range of sensitivity switching using the resistor VOL .
要するに、例えば、AM時にモード切換スイツ
チ４を接点４Ａにオンして定電圧源＋Ｂの電圧を
抵抗R9を介してトランジスタTrのベースに加え
て該トランジスタTrをオンすることにより、ソ
ースＳとアース間の抵抗値を抵抗R7に委ねて小
さくしソース電圧VSを下げる。又、FM時にモー
ド切換スイツチ４を接点４Ｆにオンしてトランジ
スタTrをオフすることにより、ソースＳとアー
ス間の抵抗値を抵抗R7，R8に委ねて大きくしソ
ース電圧VSを上げるべく成つている。 In short, for example, during AM, the mode selector switch 4 is turned on to the contact 4A, the voltage of the constant voltage source +B is applied to the base of the transistor Tr via the resistor R9 , and the transistor Tr is turned on, thereby connecting the source S and the ground. By entrusting the resistance value between the two to the resistor R7 , the source voltage V S is lowered. Also, during FM, by turning on the mode changeover switch 4 to contact 4F and turning off the transistor Tr, the resistance value between the source S and the ground is entrusted to the resistors R 7 and R 8 to increase, and the source voltage V S is increased. It is completed.
〈本考案の作用〉
以上のような構成により、FET２の第１及び
第２のゲートG1，G2、ドレーンＤ、ソースＳに
加えるDC電圧を夫々VG1，VG2，VD及びVSとする
と、第１のゲートのゲート電圧VG1は固定バイア
スと成ると共にソース電圧VSはトランジスタTr
のオン、オフに伴う２つの電圧値での固定バイア
スと成り、第２のゲートのゲート電圧VG2はDX
−LOCAL間で抵抗値の可変な上記可変抵抗器
VOLにより変化させられることゝなる。<Operation of the present invention> With the above configuration, the DC voltages applied to the first and second gates G 1 , G 2 , drain D, and source S of FET 2 are set to V G1 , V G2 , V D and V S , respectively. Then, the gate voltage V G1 of the first gate becomes a fixed bias, and the source voltage V S becomes the transistor Tr.
The gate voltage V G2 of the second gate is DX
The above variable resistor whose resistance value is variable between -LOCAL
It will be changed by VOL .
そして、このような条件においてFET２は第
２図の電力利得線図より明らかな如く
VG2−VS＞０の時、正の利得を持つ
VG2−VS＜０の時、負の利得を持つ
VG2−VS＝０の時、利得なし（cdb）
との電力利得を示し、従つて、ソース電圧VSを
モード切換スイツチ４の操作によるトランジスタ
Trのオン、オフで所定値に設定した上で、第２
のゲート電圧VG2を可変抵抗器VOLで変化させる
ことにより、FET２の利得を変化させることが
できる。 Under these conditions, FET2 has a positive gain when V G2 −V S >0, and a negative gain when V G2 −V S <0, as is clear from the power gain diagram in Figure 2. When V G2 −V S = 0, it shows a power gain with no gain (cdb), and therefore, the source voltage V S can be changed to
After setting the Tr to a predetermined value by turning it on and off,
By changing the gate voltage V G2 of FET2 using a variable resistor VOL , the gain of FET2 can be changed.
これより明らかなようにFET２の利得が負の
時FET２は減衰器として動作してアンテナ入力
信号を制御する。例えば、上記第２図の特性上直
線領域内でFET２の利得が可変抵抗器VOLのDX
時に0db、LOCAL時に−20dbとなるように第２
のソース電圧VG2とソース電圧VSを設定すれば第
２のゲート電圧VG2の電圧変化に対して略々直線
的に利得が変化することゝなり、可変抵抗器VOL
と共に感度の設定に寄与してアンテナ入力端子１
に入力してくるアンテナ入力信号を制御してドレ
ーンＤより次段のRFアンプ３に供給する。 As is clear from this, when the gain of FET2 is negative, FET2 operates as an attenuator to control the antenna input signal. For example, in the linear region of the characteristics shown in Figure 2 above, the gain of FET2 is DX of the variable resistor V OL .
The second
If the source voltage V G2 and the source voltage V S are set, the gain will change approximately linearly with respect to the voltage change of the second gate voltage V G2 , so the variable resistor V OL
The antenna input terminal 1 also contributes to the sensitivity setting.
The antenna input signal input to the RF amplifier 3 is controlled and supplied from the drain D to the RF amplifier 3 at the next stage.
尚、本考案において、上記可変抵抗器VOLの代
りに第３図に示す如くDXとLOCALを択一的に
切り換えられる切換スイツチSWをFET２の第２
のゲートG2と抵抗R1との間に設け、この切換ス
イツチSWをDX又はLOCAL位置にオンさせて定
電圧源＋ＢのDC電圧を抵抗R10に介さずに又は介
して第２のゲートG2に与えることによつてもソ
ース電圧VSと共にFET２の利得を変化させアン
テナ入力信号を制御することができる。 In the present invention, instead of the variable resistor VOL , as shown in Fig. 3, a changeover switch SW capable of selectively switching between DX and LOCAL is used as the second switch of FET2.
The switch SW is turned on to the DX or LOCAL position to apply the DC voltage of the constant voltage source +B to the second gate G without or through the resistor R10 . 2 , the antenna input signal can be controlled by changing the gain of FET 2 together with the source voltage V S .
〈本考案の効果〉
以上の如く本考案は、アンテナ入力信号が入力
されるアンテナ入力回路中にデユアルゲートの
FETを設け、該FETの第１のゲートに上記アン
テナ入力信号を入力させると共に第２のゲートに
感度設定器を介して定電圧源を接続し、他方上記
FETのソースにはAM・FMのモード切換スイツ
チの操作に伴いソース電圧を切換える回路部を接
続し、上記感度設定器により上記FETの第２の
ゲートのゲート電圧をDC制御して該FETのドレ
ーンより感度制御したアンテナ入力信号を出力す
る構成としたものであるから、従来のようにフロ
ントエンドの後方における信号ラインの引き回わ
しが無いためラジオ回路内におけるノイズによる
影響がなくなり、しかもAM・FMの切換えによ
つて決まる可変範囲内において感度設定器により
アンテナ入力信号に対する感度を設定でき、安定
した感度で同調することができる。<Effects of the present invention> As described above, the present invention has a dual gate in the antenna input circuit to which the antenna input signal is input.
A FET is provided, the antenna input signal is inputted to the first gate of the FET, and a constant voltage source is connected to the second gate via a sensitivity setting device, and the other
A circuit section that switches the source voltage according to the operation of the AM/FM mode selector switch is connected to the source of the FET, and the gate voltage of the second gate of the FET is DC controlled by the sensitivity setting device, and the drain of the FET is Since the configuration outputs the antenna input signal with better sensitivity control, there is no need to route the signal line behind the front end as in the past, eliminating the influence of noise in the radio circuit. The sensitivity to the antenna input signal can be set using the sensitivity setter within the variable range determined by the switching of the antenna, and tuning can be performed with stable sensitivity.
第１図は本考案に係る同調感度設定回路を備え
たラジオ受信機の要部を示す電気的結線図、第２
図はFETのゲート電圧とソース電圧との電位差
と電力利得の関係を示す特性線図、第３図は本考
案の同調感度設定回路の他の実施例を備えたラジ
オ受信機の要部を示す電気的結線図である。
１：アンテナ入力端子、２：FET、G1，G2：
第１、第２のゲート、Ｄ：ドレーン、Ｓ：ソー
ス、VOL：可変抵抗器、SW：切換スイツチ。
Figure 1 is an electrical wiring diagram showing the main parts of a radio receiver equipped with a tuning sensitivity setting circuit according to the present invention;
The figure is a characteristic diagram showing the relationship between the potential difference between the gate voltage and the source voltage of the FET and the power gain, and Figure 3 shows the main parts of a radio receiver equipped with another embodiment of the tuning sensitivity setting circuit of the present invention. It is an electrical wiring diagram. 1: Antenna input terminal, 2: FET, G 1 , G 2 :
First and second gates, D: drain, S: source, VOL : variable resistor, SW: changeover switch.
Claims (1)
路中にデユアルゲートのFETを設け、 該FETの第１のゲートに上記アンテナ入力信
号を入力させると共に第２のゲートに感度設定器
を介して定電圧源を接続し、 他方、上記FETのソースにはAM・FMのモー
ド切換スイツチの操作に伴い該FETのソースの
ソース電圧を切換える回路部を接続し、 上記感度設定器により上記FETの第２のゲー
トのゲート電圧をDC制御して該FETのドレーン
より感度制御したアンテナ入力信号を出力する構
成としたことを特徴とするラジオ受信機の同調感
度設定回路。[Claim for Utility Model Registration] A dual-gate FET is provided in the antenna input circuit into which the antenna input signal is input, and the antenna input signal is input to the first gate of the FET, and the sensitivity is set to the second gate. On the other hand, a circuit section that switches the source voltage of the FET source according to the operation of the AM/FM mode selector switch is connected to the source of the FET mentioned above, and the sensitivity setting device A tuning sensitivity setting circuit for a radio receiver, characterized in that the gate voltage of the second gate of the FET is DC-controlled and a sensitivity-controlled antenna input signal is output from the drain of the FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13008782U JPS5936638U (en) | 1982-08-27 | 1982-08-27 | Radio receiver tuning sensitivity setting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13008782U JPS5936638U (en) | 1982-08-27 | 1982-08-27 | Radio receiver tuning sensitivity setting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5936638U JPS5936638U (en) | 1984-03-07 |
| JPH0110030Y2 true JPH0110030Y2 (en) | 1989-03-22 |
Family
ID=30294550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13008782U Granted JPS5936638U (en) | 1982-08-27 | 1982-08-27 | Radio receiver tuning sensitivity setting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5936638U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5547716A (en) * | 1978-07-27 | 1980-04-04 | Texas Instruments Deutschland | High frequency amplifier |
-
1982
- 1982-08-27 JP JP13008782U patent/JPS5936638U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5547716A (en) * | 1978-07-27 | 1980-04-04 | Texas Instruments Deutschland | High frequency amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5936638U (en) | 1984-03-07 |
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