JP2617506B2 - Receiving sensitivity switching circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to switching of reception sensitivity of an AM receiver, and
The present invention relates to switching of reception sensitivity of an RF amplifier circuit using T.

[Conventional technology]

Many AM receivers, especially in-vehicle AM receivers, have a function for excluding broadcasts with weak electric field strength, and these functions have been achieved by switching the reception sensitivity.

FIG. 2 shows a conventional example. When the reception sensitivity is switched, the switch 4 is turned on and the transistor 3 is operated to lower the base potential of the transistor 17. As a result, the transistor 17 is turned off and the transistors 15 and 16 are turned on. The signal is divided by the emitter area ratio of the transistors 15 and 16, and the signal passing through the transistor 16 is sent to the mixing circuit through the coil 10. Here, if the emitter area ratio of the transistor 15 and the transistor 16 is set to a desired division ratio, the required sensitivity can be switched.

[Problems to be solved by the invention]

Although the conventional example does not suffer from the drawbacks of the conventional example shown in FIG. 2, the drain voltage of the FET 8 is lower than the conventional example shown in FIG.
When the voltage of 2 is low, or when the pinch-off voltage of the FET 8 is large, the voltage between the drain and the source of the FET 8 becomes small and the use condition is deteriorated.

[Means for solving the problem]

The switching circuit according to the present invention includes a first transistor and a second transistor each having an emitter connected to a drain of a FET and a collector connected to a coil, and a third transistor having an emitter connected to the drain and a collector connected to a power supply. Connecting a first current mirror circuit between a power supply and a first output of the differential amplifier, connecting an output of the first current mirror circuit to a base of the first transistor, and via a first resistor. Connect the second current mirror circuit between the power supply and the second output of the differential amplifier, connect the output of the second current mirror circuit to the bases of the second and third transistors, A control circuit connected via a second resistor to control a base potential of the differential amplifier; and a current control type AGC circuit connected to a common emitter of the differential amplifier.

〔Example〕

 Next, an embodiment will be described with reference to FIG.

In the embodiment shown in FIG. 1, the division ratio is determined by the emitter area ratio of the transistors 15 and 16, as in the conventional example shown in FIG. Also, the output currents of the transistors 25 and 26 are If it is set larger, the transistor becomes saturated when the transistor 25 or the transistor 26 operates, and the base potential of the transistors 15, 16, 17 becomes (voltage of the power supply 29) −
(V _{CE (sat)} of the transistors 25 and 26 _{) and} the drain-source voltage of the FET 8 can be increased even when the voltage of the power supply 29 is low or the pinch-off voltage of the FET 8 is large. The disadvantages of the example are solved.

〔The invention's effect〕

As described above, the present invention provides a cascode transistor
By biasing the bases of the transistors 15, 16, 17 with the transistors 25, 26, there is an effect that the reception sensitivity can be switched regardless of the characteristics of the FET 8 and regardless of the impedance of the antenna 1.

[Brief description of the drawings]

FIG. 1 is a diagram of an embodiment of the present invention, and FIG. 2 is a diagram of a conventional example. 1 ... antenna, 2 ... resistor, 4 ... switch, 5,11,1
2,29 ... Power supply, 6 ... Coupling capacitor, 7,13,1
9, 20, 27, 28 ... bias resistor, 8 ... FET, 9 ... cascode transistor, 10 ... coil, 14 ... AGC circuit,
3,15,16,17,21,22,25,26 …… Transistor, 18,23,24…
…diode.

Claims (1)

(57) [Claims] 1. An FET having a gate connected to an antenna through a coupling capacitor and having a source grounded, first and second transistors having an emitter connected to a drain of the FET and a collector connected to a coil, and a drain connected to the FET. A third transistor having an emitter connected to the collector and a collector connected to a power supply, and a first current mirror circuit connected between the power supply and a first output of the differential amplifier, and an output of the first current mirror circuit connected to the third transistor. A second current mirror circuit connected between a power supply and a second output of the differential amplifier, wherein the second current mirror circuit is connected to a base of the first transistor and grounded via a first resistor; The output of the circuit is
A control circuit for controlling the base potential of the differential amplifier connected to the base of the transistor and grounded via a second resistor, and a current-controlled automatic gain control connected to a common emitter of the differential amplifier And a receiving sensitivity switching circuit.