JP7736675B2 - Method for manufacturing solar cell and solar cell - Google Patents

Description

The present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell and a back electrode type solar cell.

Solar cells that use semiconductor substrates include double-sided electrode solar cells, in which electrodes are formed on both the light-receiving and back-side surfaces, and back-side electrode solar cells, in which electrodes are formed only on the back-side surface. In double-sided electrode solar cells, electrodes are formed on the light-receiving surface, which blocks sunlight. On the other hand, back-side electrode solar cells do not have electrodes on the light-receiving surface, so they have a higher sunlight reception rate than double-sided electrode solar cells. Patent Document 1 discloses a back-side electrode solar cell.

The solar cell described in Patent Document 1 comprises a semiconductor substrate, a first conductivity type semiconductor layer and a first electrode layer stacked in this order on the back surface of the semiconductor substrate, and a second conductivity type semiconductor layer and a second electrode layer stacked in this order on another portion of the back surface of the semiconductor substrate. The first electrode layer and the second electrode layer are separated from each other to prevent short circuits.

JP 2013-131586 A

Generally, for the purpose of improving the light confinement effect and/or light recovery efficiency in a semiconductor substrate, the semiconductor substrate has a pyramidal fine uneven structure called a texture structure on the light-receiving surface side and/or back surface side.

Also, generally, each of the first electrode layer and the second electrode layer includes a metal electrode layer.

The present inventors have devised a method of forming a metal electrode layer using a plating method in order to simplify the manufacturing process of such solar cells. However, according to the inventors' findings, with this method of manufacturing solar cells, due to the uneven structure on the back side of the semiconductor substrate, when the metal electrode layer grows, the metal electrode layer growing obliquely, particularly in the valleys of the uneven structure, presses against each other, which can cause cracks to form in the metal electrode layer.

If cracks occur in the metal electrode layer, the etching solution used to pattern the metal electrode layer can seep into the cracks and damage the semiconductor layer. This reduces the performance of the solar cell and its reliability.

The present invention aims to provide a solar cell manufacturing method and a solar cell that can suppress performance degradation and reliability degradation of the solar cell while simplifying the manufacturing process.

The solar cell manufacturing method according to the present invention is a method for manufacturing a back electrode solar cell comprising a semiconductor substrate having an uneven structure on one main surface side, a first conductivity type semiconductor layer and a first metal electrode layer stacked in this order in a first region that is a part of the one main surface side of the semiconductor substrate, and a second conductivity type semiconductor layer and a second metal electrode layer stacked in this order in a second region that is another part of the one main surface side of the semiconductor substrate, wherein the solar cell comprises a resin film disposed on at least the end of the first metal electrode layer and the second metal electrode layer on the boundary side between the first region and the second region, and each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer, and the solar cell manufacturing method comprises: and a base layer forming step of forming a series of base layer material films on the first region and the second region on the second conductive type semiconductor layer, the base layer material film being formed across the first region and the second region; a resist forming step of forming a resist on the base layer material film at the boundary between the first region and the second region; a plating layer forming step of forming a patterned plating layer on the base layer material film in each of the first region and the second region using a plating method that uses the resist as a mask; a resist removing step of removing the resist; and a base layer forming step of forming a patterned base layer in each of the first region and the second region by etching the base layer material film using an etching method that uses the plating layer as a mask. In the base layer material film formation process, a base layer material film having a concave-convex structure corresponding to the concave-convex structure of the semiconductor substrate is formed; in the resist formation process, a pattern printing method is used to print and harden a printing material containing a resin material and a solvent to form a patterned resist, thereby placing the resin film formed by the resin material seeping out into the valleys of the concave-convex structure at least at the end of the base layer; and in the plating layer formation process, the plating layer is formed on the resin film in the valleys of the concave-convex structure at least at the end of the base layer and on the peaks of the concave-convex structure of the base layer.

The solar cell of the present invention is a back-electrode solar cell comprising: a semiconductor substrate having a concave-convex structure on one principal surface side; a first conductivity-type semiconductor layer and a first metal electrode layer stacked in this order in a first region that is a portion of the one principal surface side of the semiconductor substrate; and a second conductivity-type semiconductor layer and a second metal electrode layer stacked in this order in a second region that is another portion of the one principal surface side of the semiconductor substrate. Each of the first metal electrode layer and the second metal electrode layer has a resin film disposed at least at the end portion on the boundary side between the first region and the second region. Each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer. The underlayer has a concave-convex structure corresponding to the concave-convex structure of the semiconductor substrate. The peaks of the concave-convex structure in the underlayer are in contact with the plating layer. The resin film is interposed between the valleys of the concave-convex structure at least at the end portion of the underlayer and the plating layer.

Another solar cell according to the present invention is a back-electrode solar cell comprising a semiconductor substrate having a textured structure on one main surface side, a first conductivity-type semiconductor layer and a first metal electrode layer stacked in that order in a first region that is a portion of the one main surface side of the semiconductor substrate, and a second conductivity-type semiconductor layer and a second metal electrode layer stacked in that order in a second region that is another portion of the one main surface side of the semiconductor substrate, wherein the first metal electrode layer and the second metal electrode layer each have an underlayer and a plating layer, the underlayer having a textured structure that corresponds to the textured structure of the semiconductor substrate, the peaks of the textured structure in the underlayer being in contact with the plating layer, and a space exists below the plating layer in the valleys of the textured structure at least at the end of each of the first metal electrode layer and the second metal electrode layer on the boundary side between the first region and the second region.

According to the present invention, it is possible to suppress deterioration in the performance and reliability of solar cells even while simplifying the solar cell manufacturing process.

FIG. 2 is a view of the solar cell according to the embodiment as viewed from the back surface side. 2 is a cross-sectional view of the solar cell shown in FIG. 1 taken along line II-II. 3 is an enlarged cross-sectional view of a portion III in the solar cell shown in FIG. 2. 3A to 3C are diagrams illustrating a semiconductor layer forming step in the solar cell manufacturing method according to the present embodiment. 1A to 1C are diagrams illustrating a transparent electrode layer material film forming step and a metal electrode layer underlayer material film forming step in the solar cell manufacturing method according to the present embodiment. 3A to 3C are diagrams illustrating a resist formation step in the solar cell manufacturing method according to the present embodiment. 3A to 3C are diagrams illustrating a step of forming a plating layer of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment. 1A to 1C are diagrams illustrating a resist removal step in the solar cell manufacturing method according to the present embodiment. 3A to 3C are diagrams illustrating a transparent electrode layer forming step and a base layer forming step for a metal electrode layer in the solar cell manufacturing method according to the present embodiment. 4C and 4D in the step of forming a resist and the step of forming a plating layer of a metal electrode layer. FIG. 1A and 1B are diagrams for explaining problems with the plating layer formation step of the metal electrode layer in a solar cell manufacturing method using a conventional plating method (subtract method). 4 is a partially enlarged cross-sectional view of the solar cell according to the embodiment shown in FIG. 3, and corresponds to a portion III shown in FIG. 2. FIG. 3 is a partially enlarged cross-sectional view of a solar cell according to a modified example of the present embodiment, corresponding to a portion III shown in FIG. 2. FIG. 3 is a partially enlarged cross-sectional view of a solar cell according to a modified example of the present embodiment, corresponding to a portion III shown in FIG. 2. FIG. 3 is a partially enlarged cross-sectional view of a solar cell according to a modified example of the present embodiment, corresponding to a portion III shown in FIG. 2. FIG.

An example of an embodiment of the present invention will be described below with reference to the attached drawings. Note that the same or equivalent parts in each drawing will be designated by the same reference numerals. For convenience, hatching and component reference numerals may be omitted. In such cases, reference should be made to other drawings.

(solar cells)
Fig. 1 is a view of a solar cell according to this embodiment as seen from the back surface side, and Fig. 2 is a cross-sectional view of the solar cell shown in Fig. 1 taken along line II-II. Fig. 3 is an enlarged cross-sectional view of part III in the solar cell shown in Fig. 2. The solar cell 1 shown in Figs. 1 to 3 is a back electrode type (also called a back contact type or back junction type) heterojunction solar cell.

The solar cell 1 comprises a semiconductor substrate 11 with two principal surfaces, each of which has a first region 7 and a second region 8. Hereinafter, the principal surface of the semiconductor substrate 11 that receives light will be referred to as the light-receiving surface, and the principal surface of the semiconductor substrate 11 opposite the light-receiving surface (one principal surface) will be referred to as the back surface.

The first region 7 has a so-called comb-like shape and includes multiple finger portions 7f corresponding to the comb teeth and busbar portions 7b corresponding to the support portions of the comb teeth. The busbar portions 7b extend in a first direction (X direction) along one side of the semiconductor substrate 11, and the finger portions 7f extend from the busbar portions 7b in a second direction (Y direction) that intersects with the first direction.

Similarly, the second region 8 has a so-called comb-like shape and includes multiple finger portions 8f corresponding to the teeth of the comb and busbar portions 8b corresponding to the supports for the teeth of the comb. The busbar portions 8b extend in the first direction (X direction) along one side of the semiconductor substrate 11 that faces the other side, and the finger portions 8f extend in the second direction (Y direction) from the busbar portions 8b.

The finger portions 7f and 8f are strip-shaped and extend in the second direction (Y direction) and are arranged alternately in the first direction (X direction). The first region 7 and the second region 8 may also be formed in a stripe pattern.

As shown in Figure 2, solar cell 1 includes a passivation layer 13 and an optical adjustment layer 15 stacked in this order on the light-receiving surface side of semiconductor substrate 11. Solar cell 1 also includes a passivation layer 23, a first conductivity-type semiconductor layer 25, and a first electrode layer 27 stacked in this order on a portion (first region 7) of the back surface side of semiconductor substrate 11. Solar cell 1 also includes a passivation layer 33, a second conductivity-type semiconductor layer 35, and a second electrode layer 37 stacked in this order on another portion (second region 8) of the back surface side of semiconductor substrate 11.

The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. The semiconductor substrate 11 may also be a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant. An example of an n-type dopant is phosphorus (P). An example of a p-type dopant is boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates photocarriers (electrons and holes).

By using crystalline silicon as the material for the semiconductor substrate 11, the dark current is relatively small, and a relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of the incident light is low.

The semiconductor substrate 11 has a pyramidal, finely textured structure on its backside, known as a textured structure. This increases the recovery efficiency of light that passes through the semiconductor substrate 11 without being absorbed.

The semiconductor substrate 11 may also have a pyramidal micro-convex structure, known as a texture structure, on the light-receiving surface side. This reduces the reflection of incident light on the light-receiving surface and improves the light trapping effect of the semiconductor substrate 11.

The passivation layer 13 is formed on the light-receiving surface side of the semiconductor substrate 11. The passivation layer 23 is formed in the first region 7 on the back side of the semiconductor substrate 11. The passivation layer 33 is formed in the second region 8 on the back side of the semiconductor substrate 11. The passivation layers 13, 23, and 33 are formed, for example, from a material whose main component is intrinsic (i-type) amorphous silicon material. The passivation layers 13, 23, and 33 suppress the recombination of carriers generated in the semiconductor substrate 11 and increase the carrier recovery efficiency.

The optical adjustment layer 15 is formed on the passivation layer 13 on the light-receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an anti-reflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light-receiving surface side of the semiconductor substrate 11 and the passivation layer 13. The optical adjustment layer 15 is formed from an insulating material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

The first conductivity type semiconductor layer 25 is formed on the passivation layer 23, i.e., in the first region 7 on the back surface side of the semiconductor substrate 11. On the other hand, the second conductivity type semiconductor layer 35 is formed on the passivation layer 33, i.e., in the second region 8 on the back surface side of the semiconductor substrate 11. That is, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 have a strip-like shape and extend in the Y direction. The first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 are arranged alternately in the X direction. A portion of the second conductivity type semiconductor layer 35 may overlap a portion of an adjacent first conductivity type semiconductor layer 25 (not shown).

The first conductivity type semiconductor layer 25 is formed, for example, from an amorphous silicon material. The first conductivity type semiconductor layer 25 is, for example, a p-type semiconductor layer formed by doping an amorphous silicon material with a p-type dopant (for example, the above-mentioned boron (B)).

The second conductivity type semiconductor layer 35 is formed, for example, from an amorphous silicon material. The second conductivity type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an n-type dopant (for example, the above-mentioned phosphorus (P)) is doped into an amorphous silicon material. Note that the first conductivity type semiconductor layer 25 may be an n-type semiconductor layer, and the second conductivity type semiconductor layer 35 may be a p-type semiconductor layer.

The first electrode layer 27 is formed on the first conductivity type semiconductor layer 25, i.e., in the first region 7 on the back side of the semiconductor substrate 11. On the other hand, the second electrode layer 37 is formed on the second conductivity type semiconductor layer 35, i.e., in the second region 8 on the back side of the semiconductor substrate 11. That is, the first electrode layer 27 and the second electrode layer 37 are strip-shaped and extend in the Y direction. The first electrode layer 27 and the second electrode layer 37 are arranged alternately in the X direction.

The first electrode layer 27 has a first transparent electrode layer 28 and a first metal electrode layer 29 stacked in this order on the first conductivity-type semiconductor layer 25. On the other hand, the second electrode layer 37 has a second transparent electrode layer 38 and a second metal electrode layer 39 stacked in this order on the second conductivity-type semiconductor layer 35. The first metal electrode layer 29 has a two-layer structure consisting of an underlayer 29l and a plating layer 29u, and the second metal electrode layer 39 has a two-layer structure consisting of an underlayer 39l and a plating layer 39u.

The first transparent electrode layer 28 and the second transparent electrode layer 38 are formed from a transparent conductive material. Examples of transparent conductive materials include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide) and ZnO (Zinc Oxide).

The base layer 29l in the first metal electrode layer 29 and the base layer 39l in the second metal electrode layer 39 contain a metal material such as silver, copper, or aluminum, formed using a PVD method such as sputtering. On the other hand, the plating layer 29u in the first metal electrode layer 29 and the plating layer 39u in the second metal electrode layer 39 contain a metal material such as silver, copper, or nickel, formed using a plating method.

The first electrode layer 27 and the second electrode layer 37 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). That is, the first transparent electrode layer 28 and the second transparent electrode layer 38 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). Furthermore, the first metal electrode layer 29 and the second metal electrode layer 39 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). The first transparent electrode layer 28 and the second transparent electrode layer 38 are separated from each other, and the first metal electrode layer 29 and the second metal electrode layer 39 are also separated from each other.

As shown in Figure 3, a resin film 41 is unevenly distributed between the base layer 29l and the plating layer 29u in the first metal electrode layer 29, at least at the end on the boundary side between the first region 7 and the second region 8.

More specifically, the base layer 29l is relatively thin and has a concave-convex structure corresponding to the concave-convex structure (texture structure) of the semiconductor substrate 11. The resin film 41 is interposed between the plating layer 29u and the valleys of the concave-convex structure at least at the ends of the base layer 29l. The resin film 41 may be formed in a sea-like (i.e., continuous) or island-like (i.e., discontinuous) form of the sea-island structure. It is preferable that the valleys of the concave-convex structure at least at the ends of the base layer 29l be flattened by the resin film 41.

On the other hand, the peaks of the uneven structure at least at the ends of the base layer 29l are in contact with the plating layer 29u. Furthermore, the valleys and peaks of the uneven structure other than the ends of the base layer 29l are in contact with the plating layer 29u.

Similarly, a resin film 41 is unevenly distributed at least at the end of the second metal electrode layer 39 between the base layer 39l and the plating layer 39u on the boundary side between the first region 7 and the second region 8.

More specifically, the base layer 39l is relatively thin and has a concave-convex structure corresponding to the concave-convex structure (texture structure) of the semiconductor substrate 11. The resin film 41 is interposed between the plating layer 39u and the valleys of the concave-convex structure at least at the edges of the base layer 39l. The resin film 41 may be formed in a sea-like (i.e., continuous) or island-like (i.e., discontinuous) form of the sea-island structure. It is preferable that the valleys of the concave-convex structure at least at the edges of the base layer 39l be flattened by the resin film 41.

On the other hand, the peaks of the uneven structure at least at the ends of the base layer 39l are in contact with the plating layer 39u. Furthermore, the valleys and peaks of the uneven structure other than the ends of the base layer 39l are in contact with the plating layer 39u.

(Method for manufacturing solar cells)
Next, a method for manufacturing a solar cell according to this embodiment will be described with reference to Figures 4A to 4F. Figure 4A is a diagram illustrating a semiconductor layer formation step in the method for manufacturing a solar cell according to this embodiment, and Figure 4B is a diagram illustrating a transparent electrode layer material film formation step and a metal electrode layer underlayer material film formation step in the method for manufacturing a solar cell according to this embodiment. Figure 4C is a diagram illustrating a resist formation step in the method for manufacturing a solar cell according to this embodiment, and Figure 4D is a diagram illustrating a plating layer formation step for a metal electrode layer in the method for manufacturing a solar cell according to this embodiment. Figure 4E is a diagram illustrating a resist removal step in the method for manufacturing a solar cell according to this embodiment, and Figure 4F is a diagram illustrating a transparent electrode layer formation step and a metal electrode layer underlayer formation step in the method for manufacturing a solar cell according to this embodiment. Figures 4A to 4F show the back side of semiconductor substrate 11, and the front side of semiconductor substrate 11 is omitted.

4A, a passivation layer 23 and a first conductivity type semiconductor layer 25 are formed on a portion of the back surface of the semiconductor substrate 11, specifically in the first region 7 (semiconductor layer formation process). For example, a passivation layer material film and a first conductivity type semiconductor layer material film may be formed on the entire back surface of the semiconductor substrate 11 using a CVD or PVD method, and then the passivation layer 23 and the first conductivity type semiconductor layer 25 may be patterned using an etching method that uses a resist or a metal mask generated using photolithography or printing technology.

Etching solutions for p-type semiconductor layer material films include, for example, acidic solutions such as hydrofluoric acid containing ozone or a mixture of nitric acid and hydrofluoric acid, while etching solutions for n-type semiconductor layer material films include, for example, alkaline solutions such as an aqueous potassium hydroxide solution.

Alternatively, when using the CVD or PVD method to stack a passivation layer and a first conductivity type semiconductor layer on the back side of the semiconductor substrate 11, a mask may be used to simultaneously form and pattern the passivation layer 23 and the first conductivity type semiconductor layer 25.

Next, a passivation layer 33 and a second conductivity type semiconductor layer 35 are formed on another portion of the back surface of the semiconductor substrate 11, specifically in the second region 8 (semiconductor layer formation process). For example, as described above, a passivation layer material film and a second conductivity type semiconductor layer material film may be formed on the entire back surface of the semiconductor substrate 11 using a CVD or PVD method, and then the passivation layer 33 and the second conductivity type semiconductor layer 35 may be patterned using an etching method that uses a resist or a metal mask generated using photolithography or printing technology.

Alternatively, when using the CVD or PVD method to stack a passivation layer and a second conductivity type semiconductor layer on the back side of the semiconductor substrate 11, a mask may be used to simultaneously form and pattern the passivation layer 33 and the second conductivity type semiconductor layer 35.

In addition, during this semiconductor layer formation process, a passivation layer 13 may be formed over the entire light-receiving surface side of the semiconductor substrate 11 (not shown).

Next, as shown in FIG. 4B, a continuous transparent electrode layer material film 28Z is formed on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, spanning the first region 7 and the second region 8 (transparent electrode layer material film formation process). The transparent electrode layer material film 28Z can be formed by, for example, CVD or PVD.

Next, a series of base layer material films 29lZ is formed on the transparent electrode layer material film 28Z, i.e., on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, spanning the first region 7 and the second region 8 (base layer material film formation process). The base layer material film 29lZ is formed, for example, by a PVD method such as sputtering.

Next, as shown in Figure 4C, a resist 40 is formed on the underlayer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist formation process). Methods for forming the resist 40 include press printing such as screen printing or gravure printing, or pattern printing methods such as ejection printing such as inkjet printing.

In the pattern printing method, a printing material containing a resin material and a solvent is printed and baked (cured) to form a patterned resist 40. At this time, as shown in Figure 5, a resin film 41 formed by the resin material seeping out of the printing material is formed in the valleys of the uneven structure (texture structure) of the base layer material film 29lZ.

The resin film 41 may be formed in the valleys of the uneven structure between the resist 40, i.e., in all of the first region 7 and the second region 8, as shown in Figure 5, or may be formed in the valleys of the uneven structure between the resist 40 at the end of the boundary between the first region 7 and the second region 8, as shown in Figure 3.

Next, as shown in Figure 4D, a plating method using resist 40 as a mask is used to form a patterned plating layer 29u on the underlayer material film 29lZ in the first region 7, and a patterned plating layer 39u on the underlayer material film 29lZ in the second region 8 (plated metal electrode layer formation process). Specifically, as shown in Figure 5, the plating layer 29u is formed on the resin film 41 in the valleys of the uneven structure at least at the end of the underlayer material film 29lZ, and on the peaks of the uneven structure of the underlayer material film 29lZ.

Next, as shown in Figure 4E, the resist 40 is removed (resist removal process). An alkaline aqueous solution such as a sodium hydroxide solution is used as the resist removal solution.

Next, as shown in FIG. 4F, the underlayer material film 29lZ and the transparent electrode layer material film 28Z are etched using an etching method that uses the plating layer 29u and plating layer 39u as masks to form a patterned first transparent electrode layer 28 and underlayer 29l in the first region 7, and a patterned second transparent electrode layer 38 and underlayer 39l in the second region 8 (transparent electrode layer formation process and underlayer formation process). This results in the formation of a first metal electrode layer 29 consisting of the underlayer 29l and plating layer 29u, and a second metal electrode layer 39 consisting of the underlayer 39l and plating layer 39u. Furthermore, a first electrode layer 27 consisting of the first transparent electrode layer 28 and first metal electrode layer 29, and a second electrode layer 37 consisting of the second transparent electrode layer 38 and second metal electrode layer 39 are formed.

An example of an etching solution for simultaneous etching of the underlayer material film 29lZ and the transparent electrode layer material film 28Z is a mixed solution of an oxidizing agent such as ammonium persulfate (ammonium persulfate) and an acidic solution such as hydrochloric acid (HCl) when, for example, the transparent electrode layer material film 28Z is ITO and the underlayer material film 29lZ is copper.

The technique of forming a plating layer on a relatively thin underlayer is also known as the subtraction method. In this subtraction method, instead of the resist formation process, plating layer formation process, and resist removal process described above (Figures 4C to 4E), a series of plating layers are formed and then patterned using resist. Because the underlayer is relatively thin, it has a concave-convex structure corresponding to the concave-convex structure (texture structure) of the semiconductor substrate. Therefore, as shown in Figure 6, when plating layer 29u grows on underlayer material film 29lZ, the plating layers growing diagonally, particularly in the valleys of the concave-convex structure, may push against each other (see arrows), causing cracks in the plating layer.

If cracks occur in the plating layer, for example, etching solutions used to pattern the metal electrode layer and transparent electrode layer can seep into the cracks, dissolving the underlayer material film and transparent electrode layer material film and damaging the semiconductor layer. Thin underlayer material films, in particular, have small crystal grains and are relatively easily dissolved in acidic solutions such as sulfuric acid. This reduces the performance of the solar cell and its reliability.

In this regard, in this embodiment, as shown in FIG. 5, during the resist formation process, a resin film 41 exuded from the resist 40 is disposed in the valleys of the uneven structure of the base layer material film 29lZ. It is preferable that the valleys of the uneven structure of the base layer material film 29lZ be planarized (smoothed) by the resin film 41. This prevents the plating layer 29u growing obliquely, particularly in the valleys of the uneven structure, from pressing against each other, thereby preventing cracks from forming in the plating layer. This prevents damage to the semiconductor layer, for example, caused by the penetration of an etching solution used for patterning the metal electrode layer and transparent electrode layer into cracks in the plating layer. This prevents a decrease in the performance of the solar cell. It also prevents a decrease in the reliability of the solar cell.

Then, an optical adjustment layer 15 (not shown) is formed over the entire light-receiving surface of the semiconductor substrate 11. Through the above steps, the back electrode type solar cell 1 of this embodiment shown in Figures 1 and 2 is obtained.

As described above, according to the solar cell manufacturing method of this embodiment, the metal electrode layers 29, 39 are formed using a plating method. This simplifies the solar cell manufacturing process and reduces costs.

Furthermore, according to the solar cell manufacturing method of this embodiment, a plating method uses a pattern printing method to directly (film formation and patterning are performed simultaneously) form the plating layer 29u using a resist 40 formed by printing and baking (hardening) a printing material containing a resin material and a solvent. As a result, a resin film 41 exuded from the printing material is disposed in the valleys of the uneven structure of the base layer material film 29lZ. It is preferable that the valleys of the uneven structure of the base layer material film 29lZ are planarized (smoothed) by the resin film 41. This can prevent cracks from occurring in the plating layer and suppress damage to the semiconductor layer caused by cracks in the plating layer. This can prevent degradation of the solar cell's performance. It can also prevent degradation of the solar cell's reliability.

Furthermore, according to the solar cell manufacturing method of this embodiment, a relatively inexpensive metal, such as Cu (e.g., a film formed using a PVD method such as sputtering followed by wet etching) can be used as the material for the metal electrode layers 29, 39 instead of the relatively expensive, well-known Ag paste. This allows for lower costs for solar cells.

While the above describes an embodiment of the present invention, the present invention is not limited to the above embodiment and various modifications and variations are possible. For example, the above embodiment illustrates a solar cell in which the resin film 41 is unevenly distributed in the valleys of the uneven structure between the base layer 29l and the plating layer 29u in the first metal electrode layer 29 and between the base layer 39l and the plating layer 39u in the second metal electrode layer 39, as shown in FIG. 3. However, the present invention is not limited to this, and various solar cells can be conceived depending on the degree of etching in the solar cell manufacturing process. For comparison with the comparative solar cell described below, FIG. 7A shows a partial enlarged cross-sectional view of the solar cell according to this embodiment shown in FIG. 3, which is an enlarged cross-sectional view of portion III shown in FIG. 2. FIG. 7A shows the first conductivity-type semiconductor layer 25 and passivation layer 23 together in FIG. 3. FIGS. 7B to 7D are partial enlarged cross-sectional views of solar cells according to variations of this embodiment, corresponding to portion III shown in FIG. 2.

As shown in Figure 7B, in the solar cell 1, the resin film 41 that was unevenly distributed in the valleys of the uneven structure between the base layer 29l and the plating layer 29u in the first metal electrode layer 29 and between the base layer 39l and the plating layer 39u in the second metal electrode layer 39 may be etched and removed. For example, the resin film 41 is etched and removed in the resist removal process described above.

As a result, in the solar cell 1, a space may exist below the plating layer 29u in the valleys of the uneven structure at least at the end of the first metal electrode layer 29 on the boundary side between the first region 7 and the second region 8. More specifically, at least at the end of the first metal electrode layer 29, a base layer 29l may exist below the plating layer 29u in the valleys of the uneven structure, and a space may exist between the base layer 29l and the plating layer 29u in the valleys of the uneven structure without a resin film 41 interposed therebetween.

Similarly, in solar cell 1, at least at the end of second metal electrode layer 39 on the boundary side between first region 7 and second region 8, a space may exist below plating layer 39u in the valleys of the uneven structure. More specifically, at least at the end of second metal electrode layer 39, a base layer 39l may exist below plating layer 39u in the valleys of the uneven structure, and a space may exist between base layer 39l and plating layer 39u in the valleys of the uneven structure without resin film 41 interposed therebetween.

Alternatively, as shown in Figure 7C, in the solar cell 1, the base layers 29l and 39l may be etched and removed, and the transparent electrode layers 28 and 38 may be etched and removed. For example, in the transparent electrode layer forming process and base layer forming process described above, the base layers 29l and 39l and the transparent electrode layers 28 and 38 are etched and removed.

As a result, in the solar cell 1, at least at the end of the first metal electrode layer 29, the resin film 41 and the base layer 29l are not present below the plating layer 29u in the valleys of the uneven structure, and spaces may exist. Alternatively, in the solar cell 1, at least at the end of the first metal electrode layer 29, the resin film 41, the base layer 29l, and the transparent electrode layer 28 are not present below the plating layer 29u in the valleys of the uneven structure, and spaces may exist.

Similarly, in solar cell 1, at least at the end of second metal electrode layer 39, the resin film 41 and underlayer 39l may not be present below plating layer 39u in the valleys of the uneven structure, and spaces may exist. Alternatively, in solar cell 1, at least at the end of second metal electrode layer 39, the resin film 41, underlayer 39l, and transparent electrode layer 38 may not be present below plating layer 39u in the valleys of the uneven structure, and spaces may exist.

7D, in the solar cell 1, the resin film 41 unevenly distributed in the valleys of the uneven structure between the base layer 29l and the plating layer 29u in the first metal electrode layer 29 and between the base layer 39l and the plating layer 39u in the second metal electrode layer 39 may remain unetched, while the base layers 29l and 39l may be etched and removed, and further, the transparent electrode layers 28 and 38 may be etched and removed. As described above, for example, in the transparent electrode layer formation process and base layer formation process, the base layers 29l and 39l and the transparent electrode layers 28 and 38 are etched and removed.

As a result, in the solar cell 1, at least at the end of the first metal electrode layer 29, the resin film 41 may be present below the plating layer 29u in the valleys of the uneven structure, the base layer 29l may not be present, and spaces may exist below the resin layer 41 in the valleys of the uneven structure. Alternatively, in the solar cell 1, at least at the end of the first metal electrode layer 29, the resin film 41 may be present below the plating layer 29u in the valleys of the uneven structure, the base layer 29l and the transparent electrode layer 28 may not be present, and spaces may exist below the resin layer 41 in the valleys of the uneven structure.

Similarly, in solar cell 1, at least at the end of second metal electrode layer 39, a resin film 41 may be present below plating layer 39u in the valleys of the uneven structure, with no base layer 39l present, and spaces may exist below resin layer 41 in the valleys of the uneven structure. Alternatively, in solar cell 1, at least at the end of second metal electrode layer 39, a resin film 41 may be present below plating layer 39u in the valleys of the uneven structure, with no base layer 39l or transparent electrode layer 38 present, and spaces may exist below resin layer 41 in the valleys of the uneven structure.

In addition, in the above-described embodiment, a solar cell having an electrode layer including a transparent electrode layer and a metal electrode layer was exemplified. However, the present invention is not limited to this and can also be applied to a solar cell having an electrode layer including only a metal electrode layer.

In addition, while the above-described embodiment illustrates a solar cell 1 made of crystalline silicon material, this is not limiting. For example, various materials such as gallium arsenide (GaAs) may be used as the material for the solar cell.

In addition, in the above-described embodiment, a heterojunction solar cell 1 is illustrated as shown in Figure 2. However, the present invention is not limited to this and can also be applied to various solar cells, such as homojunction solar cells.

REFERENCE SIGNS LIST 1 solar cell 7 first region 7f finger portion 7b busbar portion 8 second region 8f finger portion 8b busbar portion 11 semiconductor substrate 13, 23, 33 passivation layer 15 optical adjustment layer 25 first conductivity type semiconductor layer 27 first electrode layer 28 first transparent electrode layer 28Z transparent electrode layer material film 29 first metal electrode layer 29l underlayer 29lZ underlayer material film 29u plating layer 35 second conductivity type semiconductor layer 37 second electrode layer 38 second transparent electrode layer 39 second metal electrode layer 39l underlayer 39u plating layer 40 resist 41 resin film

Claims (13)

A back electrode type solar cell including: a semiconductor substrate having an uneven structure on one main surface side; a first conductivity type semiconductor layer and a first metal electrode layer stacked in this order in a first region which is a part of the one main surface side of the semiconductor substrate; and a second conductivity type semiconductor layer and a second metal electrode layer stacked in this order in a second region which is another part of the one main surface side of the semiconductor substrate,
a resin film disposed at least at an end of each of the first metal electrode layer and the second metal electrode layer on a boundary side between the first region and the second region;
each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer;
the underlayer has a concave-convex structure corresponding to the concave-convex structure of the semiconductor substrate,
the peaks of the concave-convex structure of the underlayer are in contact with the plating layer,
the resin film is interposed between the plating layer and a valley of the concave-convex structure at least at the end of the base layer;
Solar cell. The solar cell according to claim 1 , wherein valleys of the uneven structure of the base layer other than the end portions are in contact with the plating layer. The solar cell described in claim 1 or 2, wherein each of the first metal electrode layer and the second metal electrode layer contains copper as a primary component. a first transparent electrode layer laminated between the first conductive type semiconductor layer and the first metal electrode layer in the first region;
a second transparent electrode layer laminated between the second conductive type semiconductor layer and the second metal electrode layer in the second region;
The solar cell according to any one of claims 1 to 3, further comprising: A back electrode type solar cell including: a semiconductor substrate having an uneven structure on one main surface side; a first conductivity type semiconductor layer and a first metal electrode layer stacked in this order in a first region which is a part of the one main surface side of the semiconductor substrate; and a second conductivity type semiconductor layer and a second metal electrode layer stacked in this order in a second region which is another part of the one main surface side of the semiconductor substrate,
each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer;
the underlayer has a concave-convex structure corresponding to the concave-convex structure of the semiconductor substrate,
the peaks of the concave-convex structure of the underlayer are in contact with the plating layer,
a space exists below the plating layer in a valley portion of the uneven structure of the semiconductor substrate at least at an end portion of each of the first metal electrode layer and the second metal electrode layer on a boundary side between the first region and the second region;
Solar cell. At least at the end,
the underlayer is present under the plating layer in the valleys of the uneven structure of the semiconductor substrate ,
a resin film is not interposed between the base layer and the plating layer in the valley portion of the concave-convex structure of the semiconductor substrate , but the space is interposed between the base layer and the plating layer.
The solar cell according to claim 5 . At least at the end, the resin film and the underlayer are not present under the plating layer in the valleys of the concave-convex structure of the semiconductor substrate , and the space is present.
The solar cell according to claim 5 . At least at the end,
a resin film is present under the plating layer in the valleys of the uneven structure of the semiconductor substrate ,
the space exists under the resin film in the valley portion of the concave-convex structure of the semiconductor substrate ;
The solar cell according to claim 5 . At least at the end, the underlayer is not present under the plating layer in the valleys of the concave-convex structure of the semiconductor substrate .
The solar cell according to claim 8 . a transparent electrode layer laminated between the first conductive type semiconductor layer and the first metal electrode layer in the first region and between the second conductive type semiconductor layer and the second metal electrode layer in the second region;
At least at the end, the transparent electrode layer is not present under the plating layer in the valleys of the concave-convex structure of the semiconductor substrate .
The solar cell according to claim 7 or 9. 11. The solar cell according to claim 5, wherein the underlayer and the plating layer are in contact with each other in valleys of the uneven structure of the semiconductor substrate other than the end portion. The solar cell described in any one of claims 5 to 11, wherein each of the first metal electrode layer and the second metal electrode layer contains copper as a primary component. A method for manufacturing a back electrode type solar cell including: a semiconductor substrate having an uneven structure on one main surface side; a first conductivity type semiconductor layer and a first metal electrode layer stacked in this order in a first region that is a part of the one main surface side of the semiconductor substrate; and a second conductivity type semiconductor layer and a second metal electrode layer stacked in this order in a second region that is another part of the one main surface side of the semiconductor substrate,
the solar cell includes a resin film disposed at least at an end portion of each of the first metal electrode layer and the second metal electrode layer on a boundary side between the first region and the second region,
each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer;
The method for manufacturing a solar cell includes:
an underlayer material film forming step of forming a series of underlayer material films on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer on the one main surface side of the semiconductor substrate, spanning the first region and the second region;
a resist forming step of forming a resist on the material film of the underlayer at the boundary between the first region and the second region;
a plating layer forming step of forming a patterned plating layer on the material film of the base layer in each of the first region and the second region by using a plating method using the resist as a mask;
a resist removal step of removing the resist;
an underlayer forming step of etching a material film of the underlayer using an etching method that uses the plating layer as a mask, thereby forming a patterned underlayer in each of the first region and the second region;
Including,
In the underlayer material film forming step, a material film of the underlayer having a concavo-convex structure corresponding to the concavo-convex structure of the semiconductor substrate is formed,
In the resist forming step, a printing material containing a resin material and a solvent is printed and cured using a pattern printing method to form a patterned resist, whereby the resin film formed by the resin material seeping out is disposed in valleys of the uneven structure at least at the end of the base layer;
In the plating layer forming step, the plating layer is formed on the resin film in the valleys of the concave-convex structure at least at the end of the base layer and on the peaks of the concave-convex structure of the base layer.
How solar cells are manufactured.