JP7700153B2 - 直接取り付けられたディスパッチを使用した、分離されたスイッチ制御経路 - Google Patents

直接取り付けられたディスパッチを使用した、分離されたスイッチ制御経路 Download PDF

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JP7700153B2
JP7700153B2 JP2022574299A JP2022574299A JP7700153B2 JP 7700153 B2 JP7700153 B2 JP 7700153B2 JP 2022574299 A JP2022574299 A JP 2022574299A JP 2022574299 A JP2022574299 A JP 2022574299A JP 7700153 B2 JP7700153 B2 JP 7700153B2
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packet
function
functions
host
embedded
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JP2023529831A5 (cg-RX-API-DMAC7.html
JP2023529831A (ja
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ミリンド ミッタル，
ジャイディープ ダスティダー，
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Xilinx Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Logic Circuits (AREA)
JP2022574299A 2020-06-05 2021-02-18 直接取り付けられたディスパッチを使用した、分離されたスイッチ制御経路 Active JP7700153B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/894,446 2020-06-05
US16/894,446 US11386031B2 (en) 2020-06-05 2020-06-05 Disaggregated switch control path with direct-attached dispatch
PCT/US2021/018540 WO2021247103A1 (en) 2020-06-05 2021-02-18 Disaggregated switch control path with direct-attached dispatch

Publications (3)

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JP2023529831A JP2023529831A (ja) 2023-07-12
JP2023529831A5 JP2023529831A5 (cg-RX-API-DMAC7.html) 2024-02-28
JP7700153B2 true JP7700153B2 (ja) 2025-06-30

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US (1) US11386031B2 (cg-RX-API-DMAC7.html)
EP (1) EP4104060A1 (cg-RX-API-DMAC7.html)
JP (1) JP7700153B2 (cg-RX-API-DMAC7.html)
KR (1) KR20230019828A (cg-RX-API-DMAC7.html)
CN (1) CN115836282A (cg-RX-API-DMAC7.html)
WO (1) WO2021247103A1 (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12360937B2 (en) 2021-07-18 2025-07-15 Avago Technologies International Sales Pte. Limited Compute express Link™ (CXL) over ethernet (COE)
US12386751B2 (en) 2021-07-18 2025-08-12 Avago Technologies International Sales Pte. Limited Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC and extensible via cxloverethernet (COE) protocols

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US20090083471A1 (en) 2007-09-20 2009-03-26 Bradly George Frey Method and apparatus for providing accelerator support in a bus protocol
WO2018003629A1 (ja) 2016-06-28 2018-01-04 日本電気株式会社 パケット処理装置、及び、パケット処理方法
JP2019530100A (ja) 2016-09-29 2019-10-17 アマゾン テクノロジーズ インコーポレイテッド 複数の再構成可能な領域を有する構成可能な論理プラットフォーム

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US6914907B1 (en) 1999-08-05 2005-07-05 Alcatel Canada Inc. Method and apparatus for providing multi-cast transmissions using a distributed router
US7027397B1 (en) * 2001-02-15 2006-04-11 Cisco Technology, Inc. Method and apparatus for accumulating and distributing traffic and flow control information in a packet switching system
US7251704B2 (en) 2002-08-23 2007-07-31 Intel Corporation Store and forward switch device, system and method
US8223650B2 (en) * 2008-04-02 2012-07-17 Intel Corporation Express virtual channels in a packet switched on-chip interconnection network
JP4734374B2 (ja) 2008-06-04 2011-07-27 アラクサラネットワークス株式会社 ネットワーク中継装置、および、ネットワーク中継装置方法
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JP5561620B2 (ja) 2011-05-27 2014-07-30 日立金属株式会社 ネットワークシステム及びネットワークシステムの運用方法
US8825910B2 (en) * 2012-04-06 2014-09-02 International Business Machines Corporation Pass-through converged network adaptor (CNA) using existing ethernet switching device
JP5776618B2 (ja) 2012-04-16 2015-09-09 日立金属株式会社 ネットワークスイッチ
JP5935666B2 (ja) 2012-11-22 2016-06-15 日立金属株式会社 通信システムおよびネットワーク中継装置
US20140372660A1 (en) * 2013-06-14 2014-12-18 National Instruments Corporation Packet Routing Based on Packet Type in Peripheral Component Interconnect Express Bus Systems
CN104734993B (zh) 2013-12-24 2018-05-18 杭州华为数字技术有限公司 数据分流方法及分流器
JP6278800B2 (ja) 2014-04-03 2018-02-14 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 中継システムおよびスイッチ装置
JP6189783B2 (ja) 2014-04-08 2017-08-30 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 中継システムおよびスイッチ装置
CA2948036A1 (en) * 2014-05-26 2015-12-03 Zomojo Pty Ltd A trading system
US20160188519A1 (en) * 2014-12-27 2016-06-30 Intel Corporation Method, apparatus, system for embedded stream lanes in a high-performance interconnect
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Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US20050005084A1 (en) 2001-10-31 2005-01-06 Burger Douglas C. Scalable processing architecture
US20090083471A1 (en) 2007-09-20 2009-03-26 Bradly George Frey Method and apparatus for providing accelerator support in a bus protocol
WO2018003629A1 (ja) 2016-06-28 2018-01-04 日本電気株式会社 パケット処理装置、及び、パケット処理方法
JP2019530100A (ja) 2016-09-29 2019-10-17 アマゾン テクノロジーズ インコーポレイテッド 複数の再構成可能な領域を有する構成可能な論理プラットフォーム

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Publication number Publication date
CN115836282A (zh) 2023-03-21
US20210382838A1 (en) 2021-12-09
JP2023529831A (ja) 2023-07-12
WO2021247103A1 (en) 2021-12-09
EP4104060A1 (en) 2022-12-21
US11386031B2 (en) 2022-07-12
KR20230019828A (ko) 2023-02-09

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