CN115836282A - 具有直接连接调度的分解式交换机控制路径 - Google Patents

具有直接连接调度的分解式交换机控制路径 Download PDF

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Publication number
CN115836282A
CN115836282A CN202180040261.4A CN202180040261A CN115836282A CN 115836282 A CN115836282 A CN 115836282A CN 202180040261 A CN202180040261 A CN 202180040261A CN 115836282 A CN115836282 A CN 115836282A
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China
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packet
host
function block
function
data
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CN202180040261.4A
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English (en)
Chinese (zh)
Inventor
M·米塔尔
J·达斯蒂达
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Xilinx Inc
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Xilinx Inc
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Publication of CN115836282A publication Critical patent/CN115836282A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Logic Circuits (AREA)
CN202180040261.4A 2020-06-05 2021-02-18 具有直接连接调度的分解式交换机控制路径 Pending CN115836282A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/894,446 2020-06-05
US16/894,446 US11386031B2 (en) 2020-06-05 2020-06-05 Disaggregated switch control path with direct-attached dispatch
PCT/US2021/018540 WO2021247103A1 (en) 2020-06-05 2021-02-18 Disaggregated switch control path with direct-attached dispatch

Publications (1)

Publication Number Publication Date
CN115836282A true CN115836282A (zh) 2023-03-21

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CN202180040261.4A Pending CN115836282A (zh) 2020-06-05 2021-02-18 具有直接连接调度的分解式交换机控制路径

Country Status (6)

Country Link
US (1) US11386031B2 (cg-RX-API-DMAC7.html)
EP (1) EP4104060A1 (cg-RX-API-DMAC7.html)
JP (1) JP7700153B2 (cg-RX-API-DMAC7.html)
KR (1) KR20230019828A (cg-RX-API-DMAC7.html)
CN (1) CN115836282A (cg-RX-API-DMAC7.html)
WO (1) WO2021247103A1 (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12360937B2 (en) 2021-07-18 2025-07-15 Avago Technologies International Sales Pte. Limited Compute express Link™ (CXL) over ethernet (COE)
US12386751B2 (en) 2021-07-18 2025-08-12 Avago Technologies International Sales Pte. Limited Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC and extensible via cxloverethernet (COE) protocols

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CN107925616A (zh) * 2015-08-20 2018-04-17 英特尔公司 用于在虚拟机之间路由分组的技术

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US7027397B1 (en) * 2001-02-15 2006-04-11 Cisco Technology, Inc. Method and apparatus for accumulating and distributing traffic and flow control information in a packet switching system
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JP5561620B2 (ja) 2011-05-27 2014-07-30 日立金属株式会社 ネットワークシステム及びネットワークシステムの運用方法
JP5776618B2 (ja) 2012-04-16 2015-09-09 日立金属株式会社 ネットワークスイッチ
JP5935666B2 (ja) 2012-11-22 2016-06-15 日立金属株式会社 通信システムおよびネットワーク中継装置
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JP6278800B2 (ja) 2014-04-03 2018-02-14 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 中継システムおよびスイッチ装置
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Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090083471A1 (en) * 2007-09-20 2009-03-26 Bradly George Frey Method and apparatus for providing accelerator support in a bus protocol
US20130268694A1 (en) * 2012-04-06 2013-10-10 International Business Machines Corporation Pass-through converged network adaptor (cna) using existing ethernet switching device
US20140372660A1 (en) * 2013-06-14 2014-12-18 National Instruments Corporation Packet Routing Based on Packet Type in Peripheral Component Interconnect Express Bus Systems
WO2015179895A1 (en) * 2014-05-26 2015-12-03 Zomojo Pty Ltd A trading system
CN107003971A (zh) * 2014-12-27 2017-08-01 英特尔公司 用于高性能互连中的嵌入式流通道的方法、装置、系统
CN107925616A (zh) * 2015-08-20 2018-04-17 英特尔公司 用于在虚拟机之间路由分组的技术

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JP7700153B2 (ja) 2025-06-30
US20210382838A1 (en) 2021-12-09
JP2023529831A (ja) 2023-07-12
WO2021247103A1 (en) 2021-12-09
EP4104060A1 (en) 2022-12-21
US11386031B2 (en) 2022-07-12
KR20230019828A (ko) 2023-02-09

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