JP7660141B2 - メモリにおける推論 - Google Patents

メモリにおける推論 Download PDF

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Publication number
JP7660141B2
JP7660141B2 JP2022570688A JP2022570688A JP7660141B2 JP 7660141 B2 JP7660141 B2 JP 7660141B2 JP 2022570688 A JP2022570688 A JP 2022570688A JP 2022570688 A JP2022570688 A JP 2022570688A JP 7660141 B2 JP7660141 B2 JP 7660141B2
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memory
subset
data
expansion
memory module
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JP2023527770A5 (enExample
JP2023527770A (ja
Inventor
ヨアブ・ヘンダーソン
ダニエル・キャンベル
ライアン・ペニントン
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クアルコム,インコーポレイテッド
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284Multiple user address space allocation, e.g. using different base addresses
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0207Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/109Address translation for multiple virtual address spaces, e.g. segmentation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629Configuration or reconfiguration of storage systems
    • G06F3/0631Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0647Migration mechanisms
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083Techniques for rebalancing the load in a distributed system
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00Machine learning
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1041Resource optimization
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65Details of virtual memory and virtual address translation
    • G06F2212/657Virtual address space management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Medical Informatics (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Computing Systems (AREA)
  • Artificial Intelligence (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Stored Programmes (AREA)
JP2022570688A 2020-05-26 2021-05-20 メモリにおける推論 Active JP7660141B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/883,869 2020-05-26
US16/883,869 US12056382B2 (en) 2020-05-26 2020-05-26 Inference in memory
PCT/US2021/033436 WO2021242608A1 (en) 2020-05-26 2021-05-20 Inference in memory

Publications (3)

Publication Number Publication Date
JP2023527770A JP2023527770A (ja) 2023-06-30
JP2023527770A5 JP2023527770A5 (enExample) 2024-05-16
JP7660141B2 true JP7660141B2 (ja) 2025-04-10

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Application Number Title Priority Date Filing Date
JP2022570688A Active JP7660141B2 (ja) 2020-05-26 2021-05-20 メモリにおける推論

Country Status (9)

Country Link
US (1) US12056382B2 (enExample)
EP (1) EP4158485A1 (enExample)
JP (1) JP7660141B2 (enExample)
KR (1) KR20230015334A (enExample)
CN (1) CN115516436B (enExample)
BR (1) BR112022023193A2 (enExample)
PH (1) PH12022553472A1 (enExample)
TW (1) TWI881126B (enExample)
WO (1) WO2021242608A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12493410B2 (en) * 2020-05-22 2025-12-09 Intel Corporation Accelerating system boot times via host-managed device memory
US12504999B2 (en) * 2022-06-10 2025-12-23 Dell Products L.P. LCS workload in-band service management system
CN119816819A (zh) * 2022-09-15 2025-04-11 谷歌有限责任公司 减少硬件加速器中的存储器体冲突
US20240184464A1 (en) * 2022-12-06 2024-06-06 Macronix International Co., Ltd. Method for operating memory device and memory device
US20240319880A1 (en) * 2023-03-21 2024-09-26 Micron Technology, Inc. Compute express link dram + nand system solution

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008052370A (ja) 2006-08-22 2008-03-06 Elpida Memory Inc 半導体記憶装置及び半導体装置
JP2012234334A (ja) 2011-04-28 2012-11-29 Toshiba Corp メモリ装置
US20160357703A1 (en) 2015-06-04 2016-12-08 Fujitsu Limited Parallel computing apparatus, compiling apparatus, and parallel processing method
JP2018073414A (ja) 2016-10-27 2018-05-10 三星電子株式会社Samsung Electronics Co.,Ltd. プロセッサ、及び複数のメモリ装置を含む分散計算システム内のワークフローを制御する方法
JP2019179411A (ja) 2018-03-30 2019-10-17 株式会社デンソー 情報処理装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185704B1 (en) 1997-04-11 2001-02-06 Texas Instruments Incorporated System signaling schemes for processor and memory module
JP3507314B2 (ja) * 1997-11-19 2004-03-15 株式会社日立製作所 メモリコントローラおよびコンピュータシステム
US8359281B2 (en) 2008-06-04 2013-01-22 Nec Laboratories America, Inc. System and method for parallelizing and accelerating learning machine training and classification using a massively parallel accelerator
US8713379B2 (en) * 2011-02-08 2014-04-29 Diablo Technologies Inc. System and method of interfacing co-processors and input/output devices via a main memory system
US8495654B2 (en) * 2011-11-07 2013-07-23 International Business Machines Corporation Intranode data communications in a parallel computer
US8904068B2 (en) 2012-05-09 2014-12-02 Nvidia Corporation Virtual memory structure for coprocessors having memory allocation limitations
CN103747274B (zh) * 2013-12-18 2016-08-17 北京邮电大学 一种增设缓存集群的视频数据中心及其缓存资源调度方法
US10025747B2 (en) * 2015-05-07 2018-07-17 Samsung Electronics Co., Ltd. I/O channel scrambling/ECC disassociated communication protocol
EP3308349B1 (en) * 2015-06-10 2025-01-29 Mobileye Vision Technologies Ltd. Image processor and methods for processing an image
KR101923661B1 (ko) * 2016-04-04 2018-11-29 주식회사 맴레이 플래시 기반 가속기 및 이를 포함하는 컴퓨팅 디바이스
US10521389B2 (en) * 2016-12-23 2019-12-31 Ati Technologies Ulc Method and apparatus for accessing non-volatile memory as byte addressable memory
US10268389B2 (en) * 2017-02-22 2019-04-23 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10467159B2 (en) * 2017-07-14 2019-11-05 Arm Limited Memory node controller
US11347643B2 (en) * 2018-06-29 2022-05-31 Intel Corporation Control logic and methods to map host-managed device memory to a system address space
US10649927B2 (en) 2018-08-20 2020-05-12 Intel Corporation Dual in-line memory module (DIMM) programmable accelerator card

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008052370A (ja) 2006-08-22 2008-03-06 Elpida Memory Inc 半導体記憶装置及び半導体装置
JP2012234334A (ja) 2011-04-28 2012-11-29 Toshiba Corp メモリ装置
US20160357703A1 (en) 2015-06-04 2016-12-08 Fujitsu Limited Parallel computing apparatus, compiling apparatus, and parallel processing method
JP2018073414A (ja) 2016-10-27 2018-05-10 三星電子株式会社Samsung Electronics Co.,Ltd. プロセッサ、及び複数のメモリ装置を含む分散計算システム内のワークフローを制御する方法
JP2019179411A (ja) 2018-03-30 2019-10-17 株式会社デンソー 情報処理装置

Also Published As

Publication number Publication date
CN115516436B (zh) 2026-02-06
WO2021242608A1 (en) 2021-12-02
BR112022023193A2 (pt) 2022-12-20
US20210373790A1 (en) 2021-12-02
TW202201236A (zh) 2022-01-01
KR20230015334A (ko) 2023-01-31
US12056382B2 (en) 2024-08-06
EP4158485A1 (en) 2023-04-05
PH12022553472A1 (en) 2024-05-13
JP2023527770A (ja) 2023-06-30
TWI881126B (zh) 2025-04-21
CN115516436A (zh) 2022-12-23

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