PH12022553472A1 - Inference in memory - Google Patents

Inference in memory

Info

Publication number
PH12022553472A1
PH12022553472A1 PH1/2022/553472A PH12022553472A PH12022553472A1 PH 12022553472 A1 PH12022553472 A1 PH 12022553472A1 PH 12022553472 A PH12022553472 A PH 12022553472A PH 12022553472 A1 PH12022553472 A1 PH 12022553472A1
Authority
PH
Philippines
Prior art keywords
data
processing system
addressable memory
host processing
memory
Prior art date
Application number
PH1/2022/553472A
Other languages
English (en)
Inventor
Daniel Campbell
Joab Henderson
Ryan Pennington
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of PH12022553472A1 publication Critical patent/PH12022553472A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0647—Migration mechanisms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Medical Informatics (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Computing Systems (AREA)
  • Artificial Intelligence (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Stored Programmes (AREA)
PH1/2022/553472A 2020-05-26 2021-05-20 Inference in memory PH12022553472A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/883,869 US12056382B2 (en) 2020-05-26 2020-05-26 Inference in memory
PCT/US2021/033436 WO2021242608A1 (en) 2020-05-26 2021-05-20 Inference in memory

Publications (1)

Publication Number Publication Date
PH12022553472A1 true PH12022553472A1 (en) 2024-05-13

Family

ID=76641760

Family Applications (1)

Application Number Title Priority Date Filing Date
PH1/2022/553472A PH12022553472A1 (en) 2020-05-26 2021-05-20 Inference in memory

Country Status (9)

Country Link
US (1) US12056382B2 (enExample)
EP (1) EP4158485A1 (enExample)
JP (1) JP7660141B2 (enExample)
KR (1) KR20230015334A (enExample)
CN (1) CN115516436B (enExample)
BR (1) BR112022023193A2 (enExample)
PH (1) PH12022553472A1 (enExample)
TW (1) TWI881126B (enExample)
WO (1) WO2021242608A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12493410B2 (en) * 2020-05-22 2025-12-09 Intel Corporation Accelerating system boot times via host-managed device memory
US12504999B2 (en) * 2022-06-10 2025-12-23 Dell Products L.P. LCS workload in-band service management system
CN119816819A (zh) * 2022-09-15 2025-04-11 谷歌有限责任公司 减少硬件加速器中的存储器体冲突
US20240184464A1 (en) * 2022-12-06 2024-06-06 Macronix International Co., Ltd. Method for operating memory device and memory device
US20240319880A1 (en) * 2023-03-21 2024-09-26 Micron Technology, Inc. Compute express link dram + nand system solution

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185704B1 (en) 1997-04-11 2001-02-06 Texas Instruments Incorporated System signaling schemes for processor and memory module
JP3507314B2 (ja) * 1997-11-19 2004-03-15 株式会社日立製作所 メモリコントローラおよびコンピュータシステム
JP4205743B2 (ja) * 2006-08-22 2009-01-07 エルピーダメモリ株式会社 半導体記憶装置及び半導体装置
US8359281B2 (en) 2008-06-04 2013-01-22 Nec Laboratories America, Inc. System and method for parallelizing and accelerating learning machine training and classification using a massively parallel accelerator
US8713379B2 (en) * 2011-02-08 2014-04-29 Diablo Technologies Inc. System and method of interfacing co-processors and input/output devices via a main memory system
JP2012234334A (ja) * 2011-04-28 2012-11-29 Toshiba Corp メモリ装置
US8495654B2 (en) * 2011-11-07 2013-07-23 International Business Machines Corporation Intranode data communications in a parallel computer
US8904068B2 (en) 2012-05-09 2014-12-02 Nvidia Corporation Virtual memory structure for coprocessors having memory allocation limitations
CN103747274B (zh) * 2013-12-18 2016-08-17 北京邮电大学 一种增设缓存集群的视频数据中心及其缓存资源调度方法
US10025747B2 (en) * 2015-05-07 2018-07-17 Samsung Electronics Co., Ltd. I/O channel scrambling/ECC disassociated communication protocol
JP6432450B2 (ja) * 2015-06-04 2018-12-05 富士通株式会社 並列計算装置、コンパイル装置、並列処理方法、コンパイル方法、並列処理プログラムおよびコンパイルプログラム
EP3308349B1 (en) * 2015-06-10 2025-01-29 Mobileye Vision Technologies Ltd. Image processor and methods for processing an image
KR101923661B1 (ko) * 2016-04-04 2018-11-29 주식회사 맴레이 플래시 기반 가속기 및 이를 포함하는 컴퓨팅 디바이스
US10732866B2 (en) * 2016-10-27 2020-08-04 Samsung Electronics Co., Ltd. Scaling out architecture for DRAM-based processing unit (DPU)
US10521389B2 (en) * 2016-12-23 2019-12-31 Ati Technologies Ulc Method and apparatus for accessing non-volatile memory as byte addressable memory
US10268389B2 (en) * 2017-02-22 2019-04-23 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10467159B2 (en) * 2017-07-14 2019-11-05 Arm Limited Memory node controller
JP7080698B2 (ja) * 2018-03-30 2022-06-06 株式会社デンソー 情報処理装置
US11347643B2 (en) * 2018-06-29 2022-05-31 Intel Corporation Control logic and methods to map host-managed device memory to a system address space
US10649927B2 (en) 2018-08-20 2020-05-12 Intel Corporation Dual in-line memory module (DIMM) programmable accelerator card

Also Published As

Publication number Publication date
CN115516436B (zh) 2026-02-06
WO2021242608A1 (en) 2021-12-02
BR112022023193A2 (pt) 2022-12-20
US20210373790A1 (en) 2021-12-02
TW202201236A (zh) 2022-01-01
KR20230015334A (ko) 2023-01-31
US12056382B2 (en) 2024-08-06
JP7660141B2 (ja) 2025-04-10
EP4158485A1 (en) 2023-04-05
JP2023527770A (ja) 2023-06-30
TWI881126B (zh) 2025-04-21
CN115516436A (zh) 2022-12-23

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