JP7595331B2 - Gaming Machines - Google Patents

Description

The present invention relates to gaming machines.

Pachinko machines and slot machines are known as types of gaming machines. In these gaming machines, a lottery is held when a certain lottery condition is met, and a bonus is awarded to the player depending on the result of the lottery. It is also common for the machines to be configured to provide effects that allow the player to predict or recognize the result of the lottery. These gaming machines are equipped with a circuit board on which electronic components for progressing the game and electronic components for executing effects are mounted.

Specific examples of pachinko machines include a lottery held when a gaming ball enters a ball entry section in the game area, a changing display of pictures on the display screen of the display device, and if the lottery results in a winning result, a combination of specific pictures is displayed in a final stopped state on the display screen, and the machine transitions to a special game state that is advantageous to the player. When the machine transitions to the special game state, for example, a ball entry device or the like in the game area starts opening and closing, and game balls are paid out based on the entry of the ball into the ball entry device (see, for example, Patent Document 1).

JP 2012-170465 A

Here, in gaming machines such as those exemplified above, electronic components need to be suitably mounted on the circuit board, and there is still room for improvement in this regard.

The present invention was made in consideration of the above-mentioned circumstances, and aims to provide an amusement machine that allows electronic components to be suitably mounted on a board.

In order to solve the above problem, the present invention provides a gaming machine having a predetermined substrate on which a predetermined electronic component is surface -mounted using a reflow process ,
the predetermined electronic component includes a pair of electrodes, that is, a first predetermined electrode and a second predetermined electrode,
The predetermined substrate is
a first predetermined connection portion to which the first predetermined electrode is electrically connected;
a first predetermined wiring pattern extending from the first predetermined connection portion;
a second predetermined connection portion to which the second predetermined electrode is electrically connected;
a second predetermined wiring pattern extending from the second predetermined connection portion;
Equipped with
a direction in which a side of the first predetermined connection portion, from which the first predetermined wiring pattern is drawn, exists when viewed from a center of the first predetermined connection portion is the same as a direction in which a side of the second predetermined connection portion, from which the second predetermined wiring pattern is drawn, exists when viewed from a center of the second predetermined connection portion ;
the first predetermined connection portion is electrically connected to a first metal region having an area larger than that of the first predetermined connection portion via the first predetermined wiring pattern;
The second predetermined connection portion is electrically connected to a second metal region having an area larger than that of the second predetermined connection portion via the second predetermined wiring pattern .

The present invention makes it possible to mount electronic components on a substrate in an optimal manner.

1 is a front view of a pachinko machine according to a first embodiment. 1 is an exploded perspective view showing the main components of a pachinko machine. FIG. 1 is an exploded perspective view showing the main components of a pachinko machine. FIG. FIG. 2 is a front view showing the configuration of the game board. An explanatory diagram to explain the configuration regarding the discharge of game balls that have flowed down the game area. FIG. This is a front view of the pachinko machine with the decorative cover and decorative board removed. (a) is a plan view showing the first mounting surface, which is the plate surface on one side of the first decorative substrate; (b) is a plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the peripheral area of a bypass capacitor mounted on the first decorative substrate; and (c) is a plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the peripheral area of a small chip resistor mounted on the first decorative substrate. 8(a) is a cross-sectional view taken along line AA in FIG. (a) is a plan view showing the first mounting surface, which is the plate surface on one side of the second decorative substrate; (b) is a plan view of the first mounting surface of the second decorative substrate showing an enlarged view of the peripheral area of a bypass capacitor mounted on the second decorative substrate; and (c) is a plan view of the first mounting surface of the second decorative substrate showing an enlarged view of the peripheral area of a small chip resistor mounted on the second decorative substrate. A wiring diagram of the first light-emitting circuit section on the first decorative substrate. (a) is an oblique view of the first mounting surface side of the first decorative substrate showing an enlarged view of the bypass capacitor and its surroundings, and (b) is an oblique view of the first mounting surface side of the first decorative substrate showing an enlarged view of the small chip resistor and its surroundings. (a) is a plan view of the first mounting surface of the first decorative board showing an enlarged view of the peripheral area of the bypass capacitor; (b) is an explanatory diagram for explaining the relationship between the pads in the peripheral area and the solder resist; (c) is an explanatory diagram for explaining possible movement patterns of the bypass capacitor; and (d) is an explanatory diagram for explaining possible movement patterns of the bypass capacitor in the comparative example. (a) is a plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the peripheral area of the small chip resistor; (b) is an explanatory diagram for explaining the relationship between the pads in the peripheral area and the solder resist; (c) is an explanatory diagram for explaining possible movement patterns of the small chip resistor; and (d) is an explanatory diagram for explaining possible movement patterns of the small chip resistor in the comparative example. (a) is a plan view showing the second mounting surface of the first decorative substrate, and (b) is a plan view showing an enlarged rear area of the first light-emitting circuit section of the second mounting surface of the first decorative substrate. FIG. 1A is a cross-sectional view of a first decorative substrate, and FIG. 1B is a cross-sectional view of a first decorative substrate in a comparative example. FIG. 2A is a plan view showing a first plate surface of the collective substrate; FIG. 2B is an explanatory diagram for explaining valley division of the collective substrate; and FIG. 2C is an explanatory diagram for explaining mountain division of the collective substrate. FIG. 2A is a perspective view of a dividing jig used to divide the aggregate substrate, FIG. 2B is a front view of the dividing jig, and FIG. 2C is an explanatory diagram for explaining how the aggregate substrate is divided using the dividing jig. FIG. 2 is a block diagram showing the electrical configuration of the pachinko machine. FIG. 13 is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. 4 is a flowchart showing a main process executed by a main CPU. 11 is a flowchart showing a timer interrupt process executed by a main CPU. 13 is a flowchart showing a special chart special power control process executed by the main CPU. This is a flowchart showing the special chart change start processing executed by the main CPU. (a) A plan view showing the first mounting surface of the first decorative substrate in the second embodiment, and (b) a plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the surrounding area of a bypass capacitor mounted on the first decorative substrate. FIG. 13 is a plan view of a first light-emitting surface of a light-emitting substrate in a third embodiment. 4 is a plan view of a second light-emitting surface of the light-emitting substrate. FIG. 13A is a plan view of a first light-emitting surface of a light-emitting substrate in a fourth embodiment, and FIG. 13B is a plan view of the first light-emitting surface of the light-emitting substrate showing an enlarged view of a peripheral area of a bypass capacitor. 1A is a plan view of a second light-emitting surface of the light-emitting substrate, and FIG. 1B is a plan view of the second light-emitting surface of the light-emitting substrate showing an enlarged view of the surrounding area of the power supply terminal and the GND terminal.

First Embodiment
A first embodiment of a pachinko machine 10, which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a front view of the pachinko machine 10, and Figs. 2 and 3 are perspective views showing the main components of the pachinko machine 10 in an expanded form. For convenience, Fig. 2 omits the components within the game area of the pachinko machine 10, and Fig. 3 omits the components of the main control device 60, which will be described later, on the rear side of the pachinko machine 10.

As shown in FIG. 1, a pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a gaming machine main body 12 that is attached to the outer frame 11 so that it can rotate forward. The outer frame 11 is made of wooden boards connected at all four sides and has a rectangular frame shape. The pachinko machine 10 is installed in an amusement hall by attaching and fixing the outer frame 11 to an island facility. Note that the outer frame 11 is not a required component of the pachinko machine 10, and the outer frame 11 may be attached to the island facility of the amusement hall.

As shown in Figures 2 and 3, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine main body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 can be rotated forward with the left side as the base end of rotation and the right side as the tip end of rotation when viewed from the front.

The front door frame 14 is rotatably supported by the inner frame 13, and can be rotated forward with the left side as the base end and the right side as the tip end when viewed from the front. The back pack unit 15 is rotatably supported by the inner frame 13, and can be rotated backward with the left side as the base end and the right side as the tip end when viewed from the front.

The gaming machine main body 12 is provided with a locking device at its rotating tip, which has the function of locking the gaming machine main body 12 so that it cannot be opened relative to the outer frame 11, and also has the function of locking the front door frame 14 so that it cannot be opened relative to the inner frame 13. Each of these locked states is released by using an unlocking key to perform an unlocking operation on the cylinder lock 17 exposed on the front of the pachinko machine 10.

<Front side configuration>
Next, the configuration of the front side of the gaming machine main body 12 will be described.

The inner frame 13 is mainly composed of a resin base 21 whose outer shape is almost the same as that of the outer frame 11. A roughly elliptical window hole 23 is formed in the center of the resin base 21. A game board 24 is removably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front side of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

<Game board configuration>
The structure of the game board 24 will now be described with reference to Fig. 4. Fig. 4 is a front view of the game board 24.

An inner rail section 25 and an outer rail section 26 are attached to the game board 24 so as to define a part of the outer edge of the game area PA, and the inner rail section 25 and the outer rail section 26 form a guide rail as a guide means. Game balls launched from a game ball launching mechanism 27 (see Figure 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

The game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeder 27b that supplies game balls stored in the upper tray 54a (described later) onto the launching rail 27a, and a solenoid 27c, which is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. The solenoid 27c is driven and controlled by rotating a launching operation device (or operation handle) 28 provided on the front door frame 14, and the game balls are launched.

The game board 24 has multiple openings of various sizes that penetrate in the front-to-rear direction. Each opening is provided with a general winning port 31, a special electric winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special chart unit 37, and a general chart unit 38. There are a total of four general winning ports 31, and one of each of the others.

Even if a ball enters the through gate 35, no game balls are paid out. On the other hand, when balls enter the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls are paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball is paid out, when one game ball enters the general winning opening 31, ten prize balls are paid out, and when one game ball enters the special electric winning device 32, fifteen prize balls are paid out.

The number of prize balls is arbitrary. For example, the second actuation port 34 may be configured to have a smaller number of prize balls than the first actuation port 33, or the second actuation port 34 may be configured to have a larger number of prize balls than the first actuation port 33.

In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various winning holes are discharged from the game area PA through the outlet 24a. In addition, numerous nails 24b are planted on the game board 24 to appropriately disperse and adjust the falling direction of the game balls, and various components such as windmills are also arranged.

Here, "ball entry" means that the game ball passes through a specified opening, and includes not only the case where the game ball passes through an opening and is discharged from the game area PA, but also the case where the game ball continues to flow down the game area PA without being discharged from the game area PA after passing through an opening. However, in the following explanation, in order to clearly distinguish from the game ball entering the outlet 24a, the game ball entering the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the through gate 35 will also be referred to as "winning."

The first actuation port 33 and the second actuation port 34 are united as an actuation port device and installed on the game board 24. Both the first actuation port 33 and the second actuation port 34 are open upward. In addition, both actuation ports 33, 34 are lined up vertically with the first actuation port 33 facing upward. The second actuation port 34 is provided with a normal power device 34a as a guide piece consisting of a pair of movable pieces on the left and right. When the normal power device 34a is in a closed state, the game ball cannot enter the second actuation port 34, but when the normal power device 34a is in an open state, the game ball can enter the second actuation port 34.

A through gate 35 is provided upstream of the second operating port 34 in the direction in which the game ball flows down. The through gate 35 has a through hole (not shown) that runs vertically through it, and the game ball that enters the through gate 35 flows down the game area PA after entering the game. This makes it possible for the game ball that enters the through gate 35 to enter the second operating port 34.

When a ball wins the through gate 35, the normal power role 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is held when a ball wins the through gate 35, and a changing image is displayed on the normal map display section 38a of the normal map unit 38, which is located in the lower right corner of the play area PA, an area where the game ball does not pass through. If the result of the internal lottery is a winning electric role release, the stop result corresponding to that result is displayed, and the changing display on the normal map display section 38a ends, the normal power open state is entered. In the normal power open state, the normal power role 34a is opened in a predetermined manner.

The map display unit 38a is configured with a segment display in which a number of LED display segments are arranged in a predetermined manner, but is not limited to this and may be configured with other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display. The pattern displayed on the map display unit 38a may be a number of different characters, a number of symbols, a number of characters, or a number of colors that are switched between.

In the normal map unit 38, a normal map reserve display section 38b is provided adjacent to the normal map display section 38a. A maximum of four game balls that enter the through gate 35 are reserved, and the number of reserved balls is displayed by lighting up the normal map reserve display section 38b.

A winning lottery is triggered by the entry into the first actuation port 33 or the second actuation port 34. The lottery result is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

Regarding the special pattern unit 37 in detail, the special pattern unit 37 is provided with a special pattern display section 37a. The display area of the special pattern display section 37a is narrower than the display surface 41a of the pattern display device 41. In the special pattern display section 37a, a winning lottery is held by triggering the winning of the first operating port 33 or the winning of the second operating port 34, and a variable display of the pattern or a predetermined display is performed. Then, the result corresponding to the lottery result is displayed. The special pattern display section 37a is composed of a segment display in which a plurality of display segments using LEDs are arranged in a predetermined manner, but is not limited to this, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display device. In addition, the pattern displayed on the special pattern display section 37a may be a configuration in which multiple types of letters are displayed, a configuration in which multiple types of symbols are displayed, a configuration in which multiple types of characters are displayed, or a configuration in which multiple types of colors are displayed.

In the special chart unit 37, a special chart reserve display section 37b is provided adjacent to the special chart display section 37a. The number of game balls that enter the first operating port 33 or the second operating port 34 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the special chart reserve display section 37b.

Regarding the pattern display device 41 in detail, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described later. Note that the pattern display device 41 is not limited to a liquid crystal display device, and may be other display devices having a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display device.

In the pattern display device 41, when the special pattern display unit 37a displays a variable or predetermined pattern based on the winning of the first operation port 33 or the winning of the second operation port 34, the pattern display device 41 displays a variable or predetermined pattern accordingly. For example, the display surface 41a of the pattern display device 41 has three pattern rows, an upper row, a middle row, and a lower row, set as a plurality of display areas, and in each pattern row, main patterns numbered "1" to "9" are scrolled and displayed in ascending or descending order. In this scroll display, the scroll display of all pattern rows is started first, and the scroll display is switched to standby display in the order of the upper pattern row → the lower pattern row → the middle pattern row, and finally, the scroll display is ended in a state where a predetermined pattern is statically displayed in each pattern row. Then, in a game round in which the game result is a jackpot result, a combination of predetermined patterns is displayed stationary on a valid line set in advance on the display surface 41a of the pattern display device 41. Specifically, in the case of the most favorable jackpot result described below, the same odd number symbol combination is displayed, in the case of a low probability jackpot result described below, the same even number symbol combination is displayed, and in the case of a low prize high probability jackpot result described below, a symbol combination that is not the same but would not be displayed in the case of a low prize high probability jackpot result is displayed.

The pattern display device 41 not only performs display effects triggered by winning the first or second operating port 33 or 34, but also performs display effects during the opening and closing execution mode to which the game is switched after a winning combination is achieved. Also, based on winning the game in either operating port 33, 34, display is started on the special pattern display section 37a and the pattern display device 41, and one game round is played until a predetermined result is displayed and the game ends. Also, the manner of the variable display of the patterns on the pattern display device 41 is not limited to the above and is arbitrary, and the number of pattern rows, the direction of the variable display of the patterns in the pattern rows, the number of patterns in each pattern row, etc. can be changed as appropriate. Also, the patterns displayed by the pattern display device 41 are not limited to the above patterns, and for example, a configuration in which only numbers are displayed as patterns may be used.

When a big jackpot is won in a lottery based on winning the first operating port 33 or the second operating port 34, the mode transitions to an open/close execution mode in which winning is possible in the special electric winning device 32. The special electric winning device 32 has a large winning port (not shown) that leads to the back side of the game board 24, and an open/close door 32a that opens and closes the large winning port. The open/close door 32a is arranged in either a closed state or an open state. Specifically, the open/close door 32a is normally in a closed state in which game balls cannot win, and is switched to an open state in which game balls can win if an internal lottery is selected to transition to the open/close execution mode. Incidentally, the open/close execution mode is a mode to which the mode transitions when a winning result is obtained. Note that while winning is not impossible in the closed state, it may be configured to be less likely to occur than in the open state.

<Configuration regarding the discharge of game balls>
FIG. 5 is an explanatory diagram for explaining the configuration regarding the discharge of game balls that have flowed down the game area PA.

As already explained, a game ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is discharged from the game area PA. In other words, a game ball that is launched from the game ball launching mechanism 27 and flows into the game area PA is discharged from the game area PA by entering any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a. A game ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is guided to the back side of the game board 24.

On the back of the game board 24, discharge passages 42-48 are formed corresponding to the general winning port 31, the special winning device 32, the first operating port 33, the second operating port 34, and the outlet 24a, respectively. Game balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48 and are guided to the lower end of the game board 24 on the back side of the game board 24, where they are collected in a discharge ball collection section (not shown). The game balls collected in the discharge ball collection section are then discharged to a ball circulation device in the island equipment where the pachinko machine 10 is installed in the game hall.

Each discharge passage section 42-48 is provided with various detection sensors 42a-48a for detecting game balls. These discharge passage sections 42-48 and detection sensors 42a-48a will be described below. As already explained, four general winning openings 31 are provided, and therefore discharge passage sections 42-44 exist corresponding to each of the four. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage section 42 corresponding to the leftmost general winning opening 31 and the second discharge passage section 43 corresponding to the general winning opening 31 adjacent to it on the right. Specifically, the first winning opening detection sensor 42a is provided so that its detection range is located midway through the first discharge passage section 42, and the second winning opening detection sensor 43a is provided so that its detection range is located midway through the second discharge passage section 43. A game ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage section 42, and a game ball that enters the general winning opening 31 adjacent to the left is detected by the second winning opening detection sensor 43a while passing through the second discharge passage section 43. In addition, a third discharge passage section 44 is provided for the two general winning openings 31 on the right side, which are formed so as to merge at an intermediate position. The third discharge passage section 44 has an entrance side area corresponding to each of the two general winning openings 31, and the entrance side areas merge at an intermediate position to form one exit side area. A third winning opening detection sensor 44a is provided so that a detection range exists at an intermediate position of the exit side area in the third discharge passage section 44. A game ball that enters either of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage section 44.

A fourth discharge passage section 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists at a midpoint of the fourth discharge passage section 45, and a game ball that enters the special electric winning device 32 is detected by the special electric detection sensor 45a while passing through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists at a midpoint of the fifth discharge passage section 46, and a game ball that enters the first operating port 33 is detected by the first operating port detection sensor 46a while passing through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operating port 34. A second actuation port detection sensor 47a is provided so that a detection range exists at a midpoint of the sixth discharge passage section 47, and a game ball that enters the second actuation port 34 is detected by the second actuation port detection sensor 47a as it passes through the sixth discharge passage section 47. A seventh discharge passage section 48 exists corresponding to the outlet 24a. An outlet detection sensor 48a is provided so that a detection range exists at a midpoint of the seventh discharge passage section 48, and a game ball that enters the outlet 24a is detected by the outlet detection sensor 48a as it passes through the seventh discharge passage section 48.

A gaming ball that is detected by any one of the various detection sensors 42a-48a will not be detected by the other detection sensors 42a-48a. A gate detection sensor 49a is also provided for the through gate 35, and a gaming ball that passes through the through gate 35 on its way down the play area PA is detected by the gate detection sensor 49a.

The various detection sensors 42a to 49a are all electromagnetic induction type proximity sensors, but any sensor can be used as long as it can detect game balls individually. The various detection sensors 42a to 49a are electrically connected to the main control device 60, which will be described later, and the detection results of the various detection sensors 42a to 49a are output to the main control device 60. Specifically, the various detection sensors 42a to 49a output a LOW level signal when they are not detecting a game ball, and output a HI level signal when they are detecting a game ball. However, this is not limited to the above, and the relationship between HI and LOW may be reversed.

As shown in FIG. 2, a front door frame 14 is provided to cover the entire front side of the inner frame 13 in which the game board 24 of the above configuration is attached to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 that allows almost the entire area of the game area PA to be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted into it. The window panel 52 is formed of glass and is colorless and transparent, but is not limited to this and may be formed of synthetic resin and is colorless and transparent, or may be formed of color and transparency as long as the game area PA can be viewed through the window panel 52 from the front of the pachinko machine 10.

Above the window 51, a pair of left and right speaker sections 53 are provided that output sound effects according to the game status. Below the window 51, an upper bulge 54 and a lower bulge 55 are arranged side by side, one above the other, and bulge toward the front. An upper tray 54a that opens upward is provided inside the upper bulge 54, and a lower tray 55a that also opens upward is provided inside the lower bulge 55. The upper tray 54a has the function of temporarily storing game balls paid out from the payout device described below, and guiding them to the game ball launching mechanism 27 while aligning them in a row. The lower tray 55a also has the function of storing surplus game balls in the upper tray 54a.

As shown in FIG. 1, on the front surface of the front door frame 14, a first decorative board 56 is provided at the lower left side of the window portion 51, and a second decorative board 57 is provided at the approximate center in the left-right direction on the upper side of the window portion 51. Each decorative board 56, 57 is mounted with a plurality of LED chips, and these decorative boards 56, 57 perform light emission effects corresponding to the game state. The front door frame 14 is provided with a first decorative cover 58 that covers the front of the first decorative board 56 and a second decorative cover 59 that covers the front of the second decorative board 57. These decorative covers 58, 59 are formed of a transparent or translucent resin that transmits the light emitted from the LED chips, and bulge toward the front of the pachinko machine 10. Details of the decorative boards 56, 57 and the decorative covers 58, 59 will be described later.

Next, we will explain the configuration on the back side of the gaming machine main body 12.

As shown in FIG. 2, the back of the inner frame 13 (specifically, the game board 24) is equipped with a main control device 60 that is responsible for the main control of the game. FIG. 6 is a front view of the main control device 60.

<Configuration of main control device 60>
As shown in FIG. 6, the main control device 60 is configured by housing a main control board 61 in a board box 60a. An MPU 62 is mounted on one of the board surfaces of the main control board 61, which is an element mounting surface. The board box 60a is formed transparent so that the MPU 62 housed in the board box 60a can be seen from the outside of the board box 60a. Although the board box 60a is formed colorless and transparent, it may be formed colored and transparent as long as the MPU 62 housed in the board box 60a can be seen from the outside of the board box 60a. The main control device 60 is mounted on the back surface of the resin base 21 so that the opposing wall portion 60b of the board box 60a that faces the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, by opening the gaming machine main body 12 toward the front of the pachinko machine 10 relative to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually observe the opposing wall portion 60b of the base box 60a and also to visually observe the MPU 62 through the opposing wall portion 60b.

The board box 60a is formed by combining a plurality of case bodies 60c in front and behind, and the plurality of case bodies 60c are provided with joints 60e for preventing separation of the case bodies 60c and for leaving a trace when the case bodies 60c are separated. The joints 60e are arranged in a row on one side of the board box 60a, which is substantially rectangular. As a result, even if some of the joints 60e are used to prevent separation of the case bodies 60c and the case bodies 60c are separated by destroying the part of the joints 60e, it is possible to prevent separation of the case bodies 60c again by connecting another joint 60e thereafter. In addition, since the joints 60e are destroyed when the case bodies 60c are separated and a trace is left, it is possible to visually check the joints 60e to see whether the separation of the case bodies 60c is being carried out illegally. In addition, a seal 60f is attached to the side of the board box 60a opposite to the side on which the joints 60e are arranged, so as to straddle the boundary between the case bodies 60c. When the seal 60f is peeled off, an adhesive layer remains on the case body 60c. This makes it possible to leave a trace when the seal 60f is peeled off when the case body 60c is separated.

In the main control device 60 configured as above, the main control board 61 is provided with a setting key insertion section 68a into which a setting key owned by the manager of the game parlor is inserted and turned on to trigger the setting state of the pachinko machine 10 to be changed within the range of "setting 1" to "setting 6", an update button 68b which is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion section 68a is turned on, a reset button 68c which is operated to clear the data in the main RAM 65 (described later) provided in the MPU 62 of the main control device 60, and first to third notification display devices 69a to 69c for notifying the results of the management of the game history. The setting state of the pachinko machine 10 is not limited to the six stages of "setting 1" to "setting 6", and may be any number of stages.

The setting key insertion section 68a, the update button 68b, the reset button 68c, and the first to third notification display devices 69a to 69c are all provided on the element mounting surface of the main control board 61. As already explained, the element mounting surface of the main control board 61 faces the opposing wall section 60b of the board box 60a, but the setting key insertion section 68a, the update button 68b, and the reset button 68c are not covered by the opposing wall section 60b. In other words, the opposing wall section 60b has separate openings in the areas facing the setting key insertion section 68a, the update button 68b, and the reset button 68c. This makes it possible to insert a setting key into the setting key insertion section 68a, press the update button 68b, and press the reset button 68c without having to open the board box 60a.

By inserting a setting key into the setting key insertion section 68a and rotating it in a predetermined direction, the setting key insertion section 68a is turned ON. In this state, the supply of operating power to the pachinko machine 10 is started (i.e., the supply of operating power to the MPU 62 of the main control device 60 is started), and the setting state of the pachinko machine 10 is changed to a changeable state in which it is possible to change the setting state of the pachinko machine 10. In this state, the setting state of the pachinko machine 10 is changed by one step in ascending order in the range of "Setting 1" to "Setting 6" each time the update button 68b is pressed once. Note that if the update button 68b is operated in the "Setting 6" state, it is updated to "Setting 1". In addition, by rotating the setting key inserted in the setting key insertion section 68a from the ON operation position in the opposite direction to the predetermined direction and returning it to the initial position, the setting key insertion section 68a is turned OFF. When the setting key insertion section 68a is turned OFF, the changeable state ends, and the game is able to be played with the setting value at that time. In other words, even if you operate the update button 68b after the changeable state has ended, the setting value cannot be changed.

The ON operation of the setting key insertion section 68a is only valid when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the ON operation of the setting key insertion section 68a is performed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has ended, the setting value cannot be changed.

The setting state of the pachinko machine 10 determines the degree of advantage per unit time in the pachinko machine 10, and the larger the value of "setting n" (n is an integer from "1" to "6") (i.e., the higher the setting value), the higher the degree of advantage. As will be described in more detail later, there are two winning/losing lottery modes that determine the probability of winning a jackpot result: a low probability mode with a relatively low probability of winning and a high probability mode with a relatively high probability of winning, and the higher the setting value, the higher the probability of winning a jackpot result in the low probability mode. On the other hand, regardless of the setting value, the probability of winning a jackpot result in the high probability mode is constant.

As described above, the reset button 68c is operated to clear the data in the main RAM 65, but in order to clear the data, it is necessary to start the supply of operating power to the pachinko machine 10 while the reset button 68c is pressed (i.e., it is necessary to start the supply of operating power to the MPU 62 of the main control device 60). The ON operation of the reset button 68c is only valid when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the reset button 68c is pressed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has finished, the data in the main RAM 65 cannot be cleared.

The first to third notification display devices 69a to 69c are all segment displays in which seven LED display segments are arranged, but are not limited to this and may be a single light-emitting body of a multi-color type, a liquid crystal display device, or an organic EL display. The first to third notification display devices 69a to 69c are all installed so that their display surfaces face the direction in which the element mounting surface of the main control board 61 faces, and are covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed transparent, it is possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c housed within the board box 60a from outside the board box 60a. As already explained, the main control device 60 is mounted on the back surface of the resin base 21 with the opposing wall portion 60b, which faces the element mounting surface of the main control board 61 in the board box 60a, facing the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened toward the front of the pachinko machine 10 relative to the outer frame 11 and the rear surface of the resin base 21 is exposed toward the front of the pachinko machine 10, it becomes possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c through the opposing wall portion 60b.

The display surface of the first notification display device 69a displays not only the numbers "0" to "9" but also various characters including alphabetical characters. On the other hand, the second notification display device 69b and the third notification display device 69c display the numbers "0" to "9". The first to third notification display devices 69a to 69c are used to notify the results of the management of the game history. In addition, in a changeable state in which the setting state of the pachinko machine 10 can be changed, a value corresponding to the current setting value is displayed on the third notification display device 69c. Note that the value corresponding to the setting value may be displayed on the first notification display device 69a or on the second notification display device 69b. In addition, a configuration may be adopted in which the setting value before the changeable state is displayed on one of the first to third notification display devices 69a to 69c, and the current setting value is displayed on the other of the first to third notification display devices 69a to 69c.

A sound and light emission control device 81 is provided above the main control device 60 on the rear surface of the inner frame 13. The sound and light emission control device 81 performs sound output control, light emission control, and control of the display control device 82 in accordance with instructions from the main control device 60. The sound and light emission control device 81 also performs light emission control of the LED chips mounted on the first decorative substrate 56 and the second decorative substrate 57.

As shown in FIG. 3, the back pack unit 15 is installed to cover the back side of the inner frame 13, including the main control device 60 and the sound and light emission control device 81. The back pack unit 15 has a back pack 72 formed of a transparent synthetic resin, to which a dispensing mechanism 73 and a control device assembly unit 74 are attached.

The payout mechanism 73 includes a tank 75 to which game balls are successively replenished from the island equipment of the gaming hall, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged into the upper tray 54a or the lower tray 55a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power source of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power source on and off.

The control device assembly unit 74 is equipped with a payout control device 77 that has the function of controlling the payout device 76, and a power supply and launch control device 78 that generates and outputs the predetermined power required by various control devices, etc., and controls the launch of game balls in response to the player's operation of the launch operation device 28. The payout control device 77 and the power supply and launch control device 78 are stacked one behind the other, with the payout control device 77 at the rear of the pachinko machine 10.

Figure 7 is a front view of the pachinko machine 10 with the decorative covers 58, 59 and the decorative boards 56, 57 removed. As shown in Figure 1, the first decorative cover 58 has cylindrical cover fixing bosses 58a-58c formed integrally with the upper, lower left, and lower right parts of the back of the first decorative cover 58, which stand up toward the rear of the pachinko machine 10. The second decorative cover 59 has cylindrical cover fixing bosses 59a, 59b formed integrally with the left and right parts of the back of the second decorative cover 59, which stand up toward the rear of the pachinko machine 10. Screw holes (not shown) are formed at the ends of the upright ends of these cover fixing bosses 58a-58c, 59a, 59b. As shown in Figure 7, the front door frame 14 has through holes 14a-14e formed corresponding to these cover fixing bosses 58a-58c, 59a, 59b, which penetrate the front door frame 14 from front to rear. As shown in FIG. 1, the first decorative cover 58 and the second decorative cover 59 are fixed to the front door frame 14 by screwing the cover fixing bosses 58a-58c, 59a, and 59b from the rear side of the front door frame 14.

<Configuration of decorative substrates 56, 57>
Next, the configuration of the decorative substrates 56 and 57 will be described.

Figure 8(a) is a plan view showing the first mounting surface 84, which is the plate surface on one side of the first decorative substrate 56, Figure 8(b) is a plan view of the first mounting surface 84 of the first decorative substrate 56 showing an enlarged peripheral area 86 of a bypass capacitor 85 mounted on the first decorative substrate 56, Figure 8(c) is a plan view of the first mounting surface 84 of the first decorative substrate 56 showing an enlarged peripheral area 88 of a small chip resistor 87 mounted on the first decorative substrate 56, and Figure 9 is a cross-sectional view along line A-A in Figure 8(a). Also, FIG. 10(a) is a plan view showing the first mounting surface 89, which is the plate surface on one side of the second decorative substrate 57, FIG. 10(b) is a plan view of the first mounting surface 89 of the second decorative substrate 57 showing an enlarged peripheral area 98 of a bypass capacitor 97 mounted on the second decorative substrate 57, and FIG. 10(c) is a plan view of the first mounting surface 89 of the second decorative substrate 57 showing an enlarged peripheral area 102 of a small chip resistor 101 mounted on the second decorative substrate 57.

The decorative substrates 56 and 57 are four-layer substrates with a structure in which conductive layers and insulating layers are alternately laminated. The insulating layers are made of a composite material such as a glass cloth base material impregnated with a thermosetting epoxy resin. The conductive layers are formed by etching copper foil plates placed above or below the insulating layers.

As shown in FIG. 9, the first decorative board 56 includes, as conductive layers, a first wiring layer 91 arranged on the first mounting surface 84 side of the first decorative board 56, and a second wiring layer 92 arranged on the second mounting surface 95 side, which is the other plate surface of the first decorative board 56. The first decorative board 56 also includes, as conductive layers arranged between the first wiring layer 91 and the second wiring layer 92, a GND plane layer 93 (ground plane layer or ground plane layer) and a power plane layer 94. Lands and wiring patterns are formed on the first wiring layer 91 and the second wiring layer 92 by etching a copper foil plate.

Although not shown, the second decorative board 57, like the first decorative board 56, has a first wiring layer arranged on the first mounting surface 89 side as a conductive layer, and a second wiring layer arranged on the second mounting surface side, which is the other plate surface of the second decorative board 57. Also, like the first decorative board 56, the second decorative board 57 has a GND plane layer (ground plane layer or ground plane layer) and a power plane layer as conductive layers arranged between the first wiring layer and the second wiring layer. Lands and wiring patterns are formed on the first wiring layer and the second wiring layer by etching a copper foil plate.

As shown in FIG. 1, a stepped recess 56a is formed in the upper right side of the first decorative substrate 56, corresponding to the lower left side of the curved window portion 51. In addition, a notch 56b is formed in the lower left side of the first decorative substrate 56 to avoid the cover fixing boss 58b of the first decorative cover 58. By providing the notch 56b in the first decorative substrate 56, it is possible to install the first decorative substrate 56 in a wide area behind the first decorative cover 58 while avoiding the cover fixing boss 58b.

The first decorative substrate 56 is an irregularly shaped substrate having a stepped recess 56a and a notch 56b. The first decorative substrate 56 is neither a rectangular nor an approximately rectangular substrate. As shown in FIG. 8(a), the dimension of the first decorative substrate 56 in a first direction DR1 (the up-down direction in FIG. 8(a)) is greater than the dimension of the first decorative substrate 56 in a second direction DR2 (the left-right direction in FIG. 8(a)) perpendicular to the first direction DR1.

As shown in FIG. 10(a), the second decorative substrate 57 is shaped like a horizontally elongated, approximately elliptical shape. The second decorative substrate 57 is not a rectangular or approximately rectangular substrate. The dimension of the second decorative substrate 57 in the long axis direction LD (left-right direction in FIG. 10(a)) is greater than the dimension of the second decorative substrate 57 in the short axis direction SD (up-down direction in FIG. 10(a)).

As shown in FIG. 8(a), a protrusion 56c is provided at approximately the center in the vertical direction of the stepped recess 56a. Fixing through-holes 56d-56g are formed on the upper left end, protrusion 56c, lower left end, and lower right end of the first decorative board 56, penetrating the first decorative board 56 in the thickness direction to enable the first decorative board 56 to be screwed to the front surface of the front door frame 14. Also, as shown in FIG. 10(a), fixing through-holes 57a, 57b are formed on the left and right parts of the second decorative board 57, penetrating the second decorative board 57 in the thickness direction to enable the second decorative board 57 to be screwed to the front door frame 14.

As shown in FIG. 7, the front door frame 14 has cylindrical board fixing bosses 103-108 integrally formed on the front surface of the front door frame 14, which can fix the decorative boards 56, 57 (FIGS. 8(a) and 10(a)). The board fixing bosses 103-108 stand upright from the front surface of the front door frame 14 toward the front of the pachinko machine 10, and screw holes 103a-108a are formed at the ends of the board fixing bosses 103-108, which can screw the decorative boards 56, 57. The decorative boards 56, 57 are fixed to the front surface of the front door frame 14 as shown in FIG. 1, with the first mounting surfaces 84, 89 (FIGS. 8(a) and 10(a)) facing the front of the pachinko machine 10 by being screwed to the board fixing bosses 103-108 from the front of the pachinko machine 10.

As already explained, the light emission control of the LED chips mounted on the decorative substrates 56 and 57 and the sound output control of the speaker unit 53 are performed by the sound emission control device 81 (Fig. 3). As shown in Fig. 8(a), the first decorative substrate 56 has a first connector 111 and a second connector 112 mounted on a second mounting surface 95 (Fig. 9), which is the plate surface opposite to the first mounting surface 84. Also, as shown in Fig. 10(a), the second decorative substrate 57 has a third connector 113, a fourth connector 114, and a fifth connector 115 mounted on a second mounting surface, which is the plate surface opposite to the first mounting surface 89.

The first connector 111 is equipped with a harness (not shown) that electrically connects the sound and light emission control device 81 (FIG. 3) and the first decorative board 56. The second connector 112 and the third connector 113 are equipped with harnesses (not shown) that electrically connect the first decorative board 56 and the second decorative board 57. The fourth connector 114 and the fifth connector 115 are equipped with harnesses (not shown) that electrically connect the second decorative board 57 and the pair of left and right speaker units 53. The sound and light emission control device 81 outputs information to the first decorative board 56 for controlling the light emission of the LED chips mounted on the first decorative board 56. The sound and light emission control device 81 also outputs information to the second decorative board 57 via the first decorative board 56 for controlling the light emission of the LED chips mounted on the second decorative board 57 and information for controlling the sound output of the speaker unit 53.

As shown in FIG. 7, the front door frame 14 is formed with first to fifth connector insertion holes 14f to 14j that penetrate the front door frame 14 from front to rear in correspondence with the first to fifth connectors 111 to 115 (FIGS. 8(a) and 10(a)). The decorative boards 56, 57 (FIGS. 8(a) and 10(a)) are fixed to the front door frame 14 with the connectors 111 to 115 inserted into the corresponding connector insertion holes 14f to 14j and exposed on the rear side of the front door frame 14. The harnesses (not shown) are attached to and detached from the first to fifth connectors 111 to 115 from the rear side of the front door frame 14.

As shown in FIG. 8(a), the first decorative substrate 56 is provided with a first light-emitting circuit section 121, a second light-emitting circuit section 122, and a third light-emitting circuit section 123. As shown in FIG. 10(a), the second decorative substrate 57 is provided with a fourth light-emitting circuit section 124. These light-emitting circuit sections 121 to 124 are equipped with circuits for controlling the emission of light from multiple LED chips.

The specific configuration of the light-emitting circuit units 121 to 124 will be explained using the configuration of the first light-emitting circuit unit 121 as an example.

Figure 11 is a wiring diagram of the first light-emitting circuit section 121 in the first decorative board 56. As shown in Figure 11, the first light-emitting circuit section 121 includes an LED driver 126, a bypass capacitor 85, 16 LED chips 127-142, and eight small chip resistors 87, 143-149. Although not shown, the second to fourth light-emitting circuit sections 122-124 also include an LED driver, a bypass capacitor, multiple LED chips, and multiple small chip resistors. Note that the number of LED chips included in each of the light-emitting circuit sections 121-124 is arbitrary, and the number of small chip resistors included in each of the light-emitting circuit sections 121-124 is determined according to the connection mode between the LED driver and the LED chips.

As shown in FIG. 11, the LED driver 126 includes a power terminal 151, a clock terminal 152, a data terminal 153, a GND terminal 154 (ground terminal or ground terminal), and first to eighth output terminals 155 to 162. A wiring pattern 164 for inputting a clock signal received from the audio and light emission control device 81 is electrically connected to the clock terminal 152, and a wiring pattern 165 for inputting lighting control data received from the audio and light emission control device 81 is electrically connected to the data terminal 153. In addition, a second wiring pattern 172b for electrically connecting the LED driver 126 to the GND plane layer 93 (FIG. 9) is connected to the GND terminal 154, and a fourth wiring pattern 172d for supplying driving power to the LED driver 126 is electrically connected to the power terminal 151.

In this specification, a "terminal" refers to a linear metal part (e.g., the power terminal 151 and the GND terminal 154 (FIG. 8(b)) in the LED driver 126) provided on an electronic component (including small chip components described later) for electrical connection with a corresponding pad (or pad). In addition, an "electrode" in this specification, in a narrow sense, refers to a metal part (e.g., the first electrode 85a and the second electrode 85b (FIG. 8(b)) in the bypass capacitor 85) provided on an electronic component (including small chip components described later) for electrical surface connection with a corresponding pad (or pad), and does not include the above-mentioned "terminal". On the other hand, in a broad sense, an "electrode" in this specification refers to a metal part (e.g., the first electrode 85a and the second electrode 85b (FIG. 8(b)) provided on an electronic component (including small chip components described later) for electrical surface connection with a corresponding pad (or pad), and does not include the above-mentioned "terminal".

The LED driver 126 controls the light emission of the LED chips 127-142 connected to the first to eighth output terminals 155-162 based on the lighting control data received from the audio light emission control device 81. Two of the 16 LED chips 127-142 and one of the eight small chip resistors 87, 143-149 are electrically connected to each of the output terminals 155-162 of the LED driver 126. The small chip resistors 87, 143-149 are provided to limit the current flowing through the LED chips 127-142. The provision of the small chip resistors 87, 143-149 allows the LED chips 127-142 to be driven at or below the allowable current.

Figure 12(a) is a perspective view of the first mounting surface 84 of the first decorative substrate 56, showing an enlarged view of the bypass capacitor 85 and its periphery, and Figure 12(b) is a perspective view of the first mounting surface 84 of the first decorative substrate 56, showing an enlarged view of the small chip resistor 87 and its periphery. As shown in Figure 12(a), the bypass capacitor 85 is a surface-mounted chip capacitor, specifically a multilayer ceramic capacitor in which a large number of dielectrics and electrodes are stacked. The bypass capacitor 85 is roughly a rectangular parallelepiped, and has a pair of metallic first and second electrodes 85a and 85b at both ends in the longitudinal direction.

The bypass capacitor 85 is a small chip component whose dimension in the longitudinal direction (hereinafter also referred to as the "longitudinal direction of the bypass capacitor 85") along a plane perpendicular to the thickness direction of the bypass capacitor 85 is 0.1 mm or more and 0.9 mm or less. In this specification, a small chip component is an electronic component whose dimension in the longitudinal direction (hereinafter also referred to as the "longitudinal direction of the small chip component") of the small chip component is 0.1 mm or more and 0.9 mm or less. By making the longitudinal dimension of the small chip component 0.9 mm or less, the area occupied by the small chip component on the first decorative substrate 56 can be reduced. This makes it possible to secure a large area on the first decorative substrate 56 for mounting electronic components other than the small chip component. In addition, electronic components mounted between the first decorative substrate 56 and a substrate with a high mounting density of electronic components can be common to the small chip components. The longitudinal dimension of the small chip component is 0.1 mm or more, which can prevent the mechanical strength at the connection point between the small chip component and the first decorative substrate 56 and the mechanical strength of the small chip component itself from being excessively reduced. Here, the connection point of the small chip component includes the pad electrically connected to the electrode of the small chip component, the solder fillet electrically connecting the electrode and the pad, and the wiring pattern drawn from the pad. The longitudinal dimension of the small chip component is 0.1 mm or more, which can prevent it from becoming difficult to visually check whether or not the small chip component is missing from mounting. The longitudinal dimension of the small chip component is preferably 0.3 mm or more and 0.8 mm or less. The longitudinal dimension of the small chip component is 0.8 mm or less, which can reduce the area occupied by the small chip component on the first decorative substrate 56. The longitudinal dimension of the small chip component is 0.3 mm or more, which can increase the mechanical strength at the connection point between the small chip component and the first decorative substrate 56 and the mechanical strength of the small chip component itself. In addition, the process for checking for the presence or absence of missing small chip components can be simplified. The longitudinal dimension of the small chip components is more preferably 0.4 mm or more and 0.7 mm or less. By making the longitudinal dimension of the small chip components 0.7 mm or less, the area occupied by the small chip components on the first decorative substrate 56 can be further reduced. By making the longitudinal dimension of the small chip components 0.4 mm or more, the mechanical strength of the connection points between the small chip components and the first decorative substrate 56 and the mechanical strength of the small chip components themselves can be increased, and the possibility of the connection points being damaged can be reduced, as well as the possibility of the small chip components themselves being damaged. In addition, by making the longitudinal dimension of the small chip components 0.4 mm or more, the accuracy of checking for the presence or absence of missing small chip components can be improved when visually checking for the presence or absence of missing small chip components.

The bypass capacitor 85 is a small chip component having a longitudinal dimension of approximately 0.6 mm along a plane perpendicular to the thickness direction, and a transverse dimension (hereinafter also referred to as the "transverse direction") along a plane perpendicular to the thickness direction and a thickness direction of approximately 0.3 mm. Since the longitudinal dimension of the bypass capacitor 85 is 0.7 mm or less, the area occupied by the bypass capacitor 85 on the first decorative board 56 can be reduced. Since the longitudinal dimension of the bypass capacitor 85 is 0.4 mm or more, the mechanical strength of the connection point between the bypass capacitor 85 and the first decorative board 56 and the mechanical strength of the bypass capacitor 85 itself can be increased, and the possibility of the connection point being damaged can be reduced, and the possibility of the bypass capacitor 85 itself being damaged can be reduced. In addition, since the longitudinal dimension of the bypass capacitor 85 is 0.4 mm or more, the accuracy of confirmation when visually checking whether or not the bypass capacitor 85 is missing from installation can be improved. The bypass capacitor 85 may have a longitudinal dimension smaller than 0.6 mm (e.g., 0.4 mm), a lateral dimension smaller than 0.3 mm (e.g., 0.2 mm), or a thickness dimension smaller than 0.3 mm (e.g., 0.2 mm).

The first decorative board 56 is provided with a first pad 171a (or first pad) corresponding to the first electrode 85a of the bypass capacitor 85, and a second pad 171b (or second pad) corresponding to the second electrode 85b on the first mounting surface 84 side. The first pad 171a and the second pad 171b form a pair. Two wiring patterns 172a, 172b are led out from the first pad 171a, and two wiring patterns 172c, 172d are led out from the second pad 171b. These pads 171a, 171b and wiring patterns 172a to 172d are integrally formed by etching a single copper foil plate.

The bypass capacitor 85 is mounted on the first mounting surface 84 of the first decorative substrate 56 by soldering the electrodes 85a and 85b to the corresponding pads 171a and 171b. A solder fillet 173a is formed on the first pad 171a to electrically connect the first electrode 85a and the first pad 171a, and a solder fillet 173b is formed on the second pad 171b to electrically connect the second electrode 85b and the second pad 171b. The solder fillets 173a and 173b are formed by heating the solder paste applied to the pads 171a and 171b to melt solder, and then cooling and solidifying. In the longitudinal direction of the bypass capacitor 85, the first electrode 85a is fixed approximately at the center of the first pad 171a, and the second electrode 85b is fixed approximately at the center of the second pad 171b.

8(b), the first wiring pattern 172a drawn from the first pad 171a connected to the first electrode 85a of the bypass capacitor 85 is electrically connected to the GND plane layer 93 (FIG. 9) through a via hole 174 provided in the first decorative substrate 56, and the second wiring pattern 172b drawn from the first pad 171a is electrically connected to the GND terminal 154 of the LED driver 126. The third wiring pattern 172c drawn from the second pad 171b electrically connected to the second electrode 85b of the bypass capacitor 85 is electrically connected to the power plane layer 94 (FIG. 9) through a via hole 175 provided in the first decorative substrate 56, and the fourth wiring pattern 172d drawn from the second pad 171b is electrically connected to the power terminal 151 of the LED driver 126. In this way, the first pad 171a is arranged between the GND terminal 154 of the LED driver 126 and the GND plane layer 93, and the second pad 171b is arranged between the power terminal 151 of the LED driver 126 and the power plane layer 94.

The bypass capacitor 85 is capable of storing electric charge, and reduces the peaks of the noise components contained in the driving power supply of the LED driver 126 by charging, and reduces the valleys of the noise components by discharging. In this way, the bypass capacitor 85 absorbs the noise components contained in the driving power supply of the LED driver 126.

By arranging the bypass capacitor 85 between the power supply terminal 151 of the LED driver 126 and the power supply plane layer 94, the influence of the noise components contained in the driving power supplied from the sound light emission control device 81 to the LED driver 126 on the LED driver 126 can be reduced. As shown in FIG. 8B, the bypass capacitor 85 is arranged close to the power supply terminal 151 so that there are no other electronic components such as ICs between the bypass capacitor 85 and the power supply terminal 151 of the LED driver 126. This increases the possibility that the noise components contained in the driving power supplied to the power supply terminal 151 of the LED driver 126 are absorbed by the bypass capacitor 85, and reduces the possibility that the LED driver 126 will malfunction due to the influence of the noise components. Since there are no other ICs between the bypass capacitor 85 and the power supply terminal 151, the noise components generated by the LED driver 126 can be absorbed by the bypass capacitor 85, preventing the noise components from causing other ICs to malfunction. In addition, because there are no other electronic components between the bypass capacitor 85 and the power supply terminal 151, the noise components generated by the LED driver 126 are absorbed by the bypass capacitor 85, preventing the noise components from causing malfunctions in other electronic components.

As shown in FIG. 12(b), the small chip resistor 87 is a substantially rectangular parallelepiped, similar to the bypass capacitor 85 (FIG. 12(a)), and has a pair of metallic first electrodes 87a and second electrodes 87b at both ends in the longitudinal direction. The small chip resistor 87 is a small chip component having a longitudinal dimension (hereinafter also referred to as the "longitudinal direction of the small chip resistor 87") of 0.1 mm or more and 0.9 mm or less along a plane perpendicular to the thickness direction of the small chip resistor 87, similar to the bypass capacitor 85. The small chip resistor 87 is a small chip component having a longitudinal dimension of approximately 0.6 mm along a plane perpendicular to the thickness direction, and a transverse dimension (hereinafter also referred to as the "transverse direction") along a plane perpendicular to the thickness direction and a thickness direction dimension of approximately 0.3 mm. Since the longitudinal dimension of the small chip resistor 87 is 0.7 mm or less, the area occupied by the small chip resistor 87 on the first decorative substrate 56 can be reduced. By having the longitudinal dimension of the small chip resistor 87 be 0.4 mm or more, the mechanical strength at the connection point between the small chip resistor 87 and the first decorative substrate 56 and the mechanical strength of the small chip resistor 87 itself can be increased, and the possibility of the connection point being damaged can be reduced, and the possibility of the small chip resistor 87 itself being damaged can be reduced. In addition, by having the longitudinal dimension of the small chip resistor 87 be 0.4 mm or more, the accuracy of confirmation when visually checking whether or not the small chip resistor 87 is missing from mounting can be improved. Note that the longitudinal dimension of the small chip resistor 87 may be smaller than 0.6 mm (for example, a configuration of 0.4 mm), the short-side dimension of the small chip resistor 87 may be smaller than 0.3 mm (for example, a configuration of 0.2 mm), or the thickness dimension may be smaller than 0.3 mm (for example, a configuration of 0.2 mm).

The first decorative substrate 56 is provided with a first pad 176a (or first pad) corresponding to the first electrode 87a of the small chip resistor 87 and a second pad 176b (or second pad) corresponding to the second electrode 87b on the first mounting surface 84 side. The first pad 176a and the second pad 176b form a pair. One wiring pattern 181a is drawn out from the first pad 176a, and one wiring pattern 181b is drawn out from the second pad 176b. These pads 176a, 176b and wiring patterns 181a, 181b are integrally formed by etching a single copper foil plate.

The small chip resistor 87 is mounted on the first mounting surface 84 of the first decorative substrate 56 by soldering the electrodes 87a and 87b to the corresponding pads 176a and 176b. A solder fillet 177a is formed on the first pad 176a to electrically connect the first electrode 87a to the first pad 176a, and a solder fillet 177b is formed on the second pad 176b to electrically connect the second electrode 87b to the second pad 176b. The solder fillets 177a and 177b are formed by heating the solder paste applied to the pads 176a and 176b to melt solder, and then cooling and solidifying. In the longitudinal direction of the small chip resistor 87, the first electrode 87a is fixed approximately at the center of the first pad 176a, and the second electrode 87b is fixed approximately at the center of the second pad 176b.

As shown in FIG. 8(c), the LED chip 142 is a surface-mounted chip component. The LED chip 142 is a roughly rectangular parallelepiped, and is provided with a pair of metallic first and second electrodes 142a and 142b at both ends in the longitudinal direction. The first decorative substrate 56 is also provided with a first copper pad 178a (or first pad) corresponding to the first electrode 142a, and a second copper pad 178b (or second pad) corresponding to the second electrode 142b. The first pad 178a and the second pad 178b form a pair.

The first wiring pattern 181a extending from the first pad 176a of the small chip resistor 87 is electrically connected to the second pad 178b of the LED chip 142. In addition, the second wiring pattern 181b extending from the second pad 176b of the small chip resistor 87 is electrically connected to the eighth output terminal 162 of the LED driver 126.

As described above, electronic components such as connectors 111-115, LED driver 126, LED chips 127-142, bypass capacitors 85, 97, and small chip resistors 87, 101, 143-149 are mounted on the decorative substrates 56, 57. The outer dimensions of the small chip components (bypass capacitors 85, 97 and small chip resistors 87, 101, 143-149) among these electronic components are smaller than the outer dimensions of the other electronic components, and the contact area between the electrodes and pads (or pads) of the small chip components is smaller than the contact area between the electrodes and pads (or pads) of the other electronic components. For this reason, the connection points between the small chip components among the various electronic components mounted on the decorative substrates 56, 57 and the decorative substrates 56, 57 have lower mechanical strength than the connection points between the other electronic components and the decorative substrates 56, 57. In this specification, the connection points between the small chip components and the decorative substrates 56 and 57 include pads electrically connected to the electrodes of the small chip components, solder fillets electrically connecting the electrodes of the small chip components and the pads, and wiring patterns drawn from the pads. Specifically, the connection points between the bypass capacitor 85 and the first decorative substrate 56 include pads 171a and 171b electrically connected to the electrodes 85a and 85b of the bypass capacitor 85, solder fillets 173a and 173b electrically connecting the electrodes 85a and 85b of the bypass capacitor 85 and the pads 171a and 171b, and wiring patterns 172a to 172d drawn from the pads 171a and 171b. In addition, the connection points between the small chip resistor 87 and the first decorative substrate 56 include pads 176a, 176b that are electrically connected to the electrodes 87a, 87b of the small chip resistor 87, solder fillets 177a, 177b that electrically connect the electrodes 87a, 87b of the small chip resistor 87 to the pads 176a, 176b, and wiring patterns 181a, 181b that are drawn out from the pads 176a, 176b.

By using small chip components (bypass capacitors 85, 97 and small chip resistors 87, 101, 143-149) smaller than electronic components such as the LED driver 126 and the LED chips 127-142, the area occupied by the capacitors and resistors on the decorative substrate 56, 57 can be reduced, but there is a problem in that when the decorative substrate 56, 57 is distorted, the connection between the small chip components and the decorative substrate 56, 57 is easily damaged, and the small chip components themselves are easily damaged. In this specification, damage to the connection between the small chip components and the decorative substrate 56, 57 includes damage caused by cracks in the solder fillet that electrically connects the electrode of the small chip component to the pad (or pad), damage caused by peeling off the solder fillet, damage caused by peeling off the pad from the decorative substrate 56, 57, and damage caused by peeling off the wiring pattern around the pad from the decorative substrate 56, 57. In addition, in this specification, damage to the small chip component itself includes damage that causes cracks to form in the small chip component, and damage that destroys the internal structure of the small chip component (for example, the laminated structure of the bypass capacitors 85, 97).

Circumstances in which the decorative boards 56, 57 with the small chip components mounted on them may be distorted when the decorative boards 56, 57 are screwed to the front door frame 14, when a harness (not shown) is attached to and detached from the connectors 111-115 mounted on the second mounting surface 95 of the decorative boards 56, 57, and when electronic components such as the LED driver 126 and LED chips 127-142 mounted on the first decorative board 56 generate heat during use, causing thermal stress to act on the decorative boards 56, 57 due to the heat. In addition, in a manufacturing method in which electronic components including small chip components are mounted on an aggregate board including multiple decorative boards 56, 57 and then the aggregate board is divided to extract the multiple decorative boards 56, 57, distortion may also occur in the decorative boards 56, 57 with the small chip components mounted on them when the aggregate board is divided. In these cases, bending stress may act on the decorative boards 56, 57, and torsional stress may act on the decorative boards 56, 57.

Figure 13(a) is a plan view of the first mounting surface 84 of the first decorative board 56, showing an enlarged view of the peripheral area 182 (Figure 8(b)) of the bypass capacitor 85, and Figure 13(b) is an explanatory diagram for explaining the relationship between the pads 171a, 171b in the peripheral area 182 and the solder resist 222. Figure 13(c) is an explanatory diagram for explaining the movement of the bypass capacitor 85 that may occur in this embodiment, and Figure 13(d) is an explanatory diagram for explaining the movement of the bypass capacitor 85 that may occur in the comparative example. Note that in Figure 13(b), the solder resist 222 is shown hatched.

As shown in FIG. 13(a), the first pad 171a and the second pad 171b corresponding to the first electrode 85a and the second electrode 85b of the bypass capacitor 85 are formed into a substantially rectangular shape. As shown in FIG. 13(b), the first pad 171a and the second pad 171b have the same shape and size. The vertical dimension LA1 of the pads 171a and 171b is approximately 0.35 mm, which is larger than the short-side dimension (approximately 0.3 mm) of the bypass capacitor 85. Since the pair of pads 171a and 171b have the same shape and size, the amount of solder paste applied to the pair of pads 171a and 171b can be approximately the same. Note that the vertical dimension LA1 of the pads 171a and 171b may be configured to be the same as the short-side dimension of the bypass capacitor 85, or the vertical dimension LA1 of the pads 171a and 171b may be configured to be smaller than the short-side dimension of the bypass capacitor 85.

The horizontal dimension LA2 of the pads 171a and 171b is approximately 0.32 mm. The first pad 171a and the second pad 171b are spaced apart at a predetermined distance LA3 (specifically, approximately 0.28 mm) in the longitudinal direction (first direction DR1) of the bypass capacitor 85 (FIG. 13(a)). The distance (predetermined distance LA3) between the outer edge of the first pad 171a on the second pad 171b side and the outer edge of the second pad 171b on the first pad 171a side is set in the range of approximately 1/3 (0.2 mm) to approximately 1/2 (approximately 0.3 mm) of the longitudinal dimension of the bypass capacitor 85 (approximately 0.6 mm). This allows the bypass capacitor 85 to be mounted on the first decorative substrate 56 in such a way that the first electrode 85a of the bypass capacitor 85 is located approximately in the center of the first pad 171a and the second electrode 85b is located approximately in the center of the second pad 171b in the longitudinal direction of the bypass capacitor 85.

The solder resist 222 is not applied between the first pad 171a and the second pad 171b. If the solder resist 222 is applied to the narrow area between the first pad 171a and the second pad 171b, the probability of defective products occurring in which part or all of the pads 171a and 171b are covered with the solder resist 222 increases if there is a misalignment in the application area of the solder resist 222. In contrast, by not applying the solder resist 222 between the first pad 171a and the second pad 171b, it is possible to prevent part or all of these pads 171a and 171b from being covered with the solder resist 222 and to apply solder paste to the entire area of these pads 171a and 171b. This ensures the connection area between the first pad 171a and the first electrode 85a, ensuring the mechanical strength of the connection between the first pad 171a and the first electrode 85a, and also ensures the connection area between the second pad 171b and the second electrode 85b, ensuring the mechanical strength of the connection between the second pad 171b and the second electrode 85b.

As shown in FIG. 13(a), the pair of pads 171a, 171b are spaced apart in the first direction DR1, which is the longitudinal direction of the bypass capacitor 85. Therefore, when the first decorative substrate 56 is transported to a reflow furnace in the reflow process, the first decorative substrate 56 is transported in a second direction DR2 perpendicular to the first direction DR1, so that heating of the solder paste applied to the pair of pads 171a, 171b can be started at approximately the same time.

The solder paste applied to the pads 171a and 171b is heated in a reflow furnace to become liquid molten solder. The molten solder floats and attracts the electrodes 85a and 85b of the bypass capacitor 85. The solder paste contains flux components, and the molten solder flows on the pads 171a and 171b. In addition, gas is released from the molten solder. If the solder paste melts in one pad 171a of the pair of pads 171a and 171b before the other pad 171b, only one electrode 85a of the pair of electrodes 85a and 85b of the bypass capacitor 85 is in contact with the molten solder, and the balance of the forces acting on the electrodes 85a and 85b of the bypass capacitor 85 due to the surface tension of the molten solder is lost. This makes it easier for the bypass capacitor 85 to rotate around an axis normal to the first decorative substrate 56, and makes it easier for the bypass capacitor 85 to stand up approximately vertically on one of the pads 171a with one electrode 85a, which is called a chip standing. In this way, if there is a difference in the timing at which the solder paste melts between the pair of pads 171a and 171b, the bypass capacitor 85 is more likely to rotate and the chip standing to occur. In contrast, by transporting the first decorative substrate 56 in the second direction DR2 in the reflow process and starting to heat the solder paste applied to the pair of pads 171a and 171b approximately at the same time, it is possible to align the timing at which the solder paste melts between the pair of pads 171a and 171b, and to prevent the bypass capacitor 85 from rotating and the chip standing from occurring.

As shown in FIG. 8(b), the bypass capacitor 85 is mounted on the first decorative substrate 56 with the longitudinal direction of the bypass capacitor 85 parallel to the first direction DR1. As shown in FIG. 8(c), the small chip resistor 87 is mounted on the first decorative substrate 56 with the longitudinal direction of the small chip resistor 87 parallel to the first direction DR1. Although not shown, the small chip resistors 143-149 are also mounted on the first decorative substrate 56 with the longitudinal direction of the small chip resistors 143-149 parallel to the first direction DR1. In this way, the small chip components (the bypass capacitor 85 and the small chip resistors 87, 143-149) are mounted on the first decorative substrate 56 with the longitudinal direction of the small chip components parallel to the first direction DR1.

8(b) and (c), the spacing direction of the pads 171a, 171b corresponding to the electrodes 85a, 85b of the bypass capacitor 85 and the spacing direction of the pads 176a, 176b corresponding to the electrodes 87a, 87b of the small chip resistor 87 are the first direction DR1. The spacing direction of the pads 171a, 171b, 176a, 176b is the same in multiple small chip components. Therefore, by transporting the first decorative substrate 56 in a direction perpendicular (second direction DR2) or substantially perpendicular to the common separation direction (first direction DR1) during the reflow process, the timing at which heating of the solder paste applied to the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 can be synchronized, and the timing at which heating of the solder paste applied to the pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the small chip resistor 87 can be synchronized. This makes it possible to prevent rotation of multiple small chip components and the occurrence of chip standing.

In the pads 171a and 171b corresponding to the electrodes 85a and 85b of the bypass capacitor 85, the portions where the wiring patterns 172a to 172d are pulled out (the positions where the wiring patterns 172a to 172d are pulled out) tend to lose heat to the wiring patterns 172a to 172d, so the temperature rise is likely to be delayed in the initial heating stage of the reflow process compared to the portions where the wiring patterns 172a to 172d are not pulled out. In addition, the first wiring pattern 172a and the third wiring pattern 172c connected to the GND plane layer 93 or the power plane layer 94, which are larger in area than the pads 171a and 171b, tend to experience a delayed temperature rise in the initial heating stage compared to the second wiring pattern 172b and the fourth wiring pattern 172d not connected to the GND plane layer 93 or the power plane layer 94. Therefore, the temperature rise in the first pad 171a where the first wiring pattern 172a connected to the GND plane layer 93 is drawn out is more likely to be delayed compared to the location where the second wiring pattern 172b is drawn out. Also, the temperature rise in the second pad 171b where the third wiring pattern 172c connected to the power plane layer 94 is drawn out is more likely to be delayed compared to the location where the fourth wiring pattern 172d is drawn out. In the reflow process, the temperature distribution in the pads 171a and 171b in the early heating stage changes depending on the number of wiring patterns 172a to 172d drawn out from the pair of pads 171a and 171b, the drawing positions, and the connection destinations. Also, the drawing direction of the wiring patterns 172a to 172d drawn out from the pair of pads 171a and 171b may affect the temperature distribution in the pads 171a and 171b in the early heating stage. Details will be described later, but in this embodiment, the first decorative substrate 56 has the number, drawing positions, connection destinations, and drawing directions of the wiring patterns 172a-172d drawn out from the pair of pads 171a, 171b set so that there is no difference in temperature distribution within the pair of pads 171a, 171b during the initial heating stage.

13(d), in the bypass capacitor 183 in the comparative example, the first wiring pattern 185a is drawn out from the right end of the first pad 184a (or the first pad) toward the right, and the second wiring pattern 185b is drawn out from the left end of the first pad 184a toward the left. The first wiring pattern 185a in the comparative example is a wiring pattern electrically connected to the GND plane layer 93 (FIG. 9) through the via hole 174, similar to the first wiring pattern 172a in the embodiment already described, and the second wiring pattern 185b in the comparative example is a wiring pattern electrically connected to the GND terminal 154 of the LED driver 126, similar to the second wiring pattern 172b in the embodiment already described. In addition, the third wiring pattern 185c is drawn out downward from the lower end of the second pad 184b (or the second pad), and the fourth wiring pattern 185d is drawn out from the left end of the second pad 184b toward the left. The third wiring pattern 185c in the comparative example is a wiring pattern electrically connected to the power supply plane layer 94 (FIG. 9) through the via hole 175, similar to the third wiring pattern 172c in the embodiment already described, and the fourth wiring pattern 172d in the comparative example is a wiring pattern electrically connected to the power supply terminal 151 of the LED driver 126, similar to the fourth wiring pattern 172d in the embodiment already described. In the first pad 184a, the temperature rise is likely to be delayed in the initial heating stage at the locations where the first wiring pattern 185a and the second wiring pattern 185b are drawn out (the right end and the left end of the first pad 184a). In particular, the temperature rise is likely to be delayed at the location where the first wiring pattern 185a connected to the GND plane layer 93 is drawn out (the left end of the first pad 184a). In addition, in the second pad 184b, the temperature rise is likely to be delayed in the initial heating stage at the locations (lower end and left end of the second pad 184b) where the third wiring pattern 185c and the fourth wiring pattern 185d are drawn out. In particular, the temperature rise is likely to be delayed at the location (lower end of the second pad 184b) where the third wiring pattern 185c connected to the power supply plane layer 94 is drawn out. For this reason, in the initial heating stage of the reflow process, the temperature of the upper right part of the second pad 184b is likely to rise. If a state occurs in which the solder paste is melted only in the upper right part of the second pad 184b, as shown in FIG. 13(d), the upper right part of the second pad 184b becomes the center of rotation, and the normal direction of the first decorative substrate 56 becomes the rotation axis, and the bypass capacitor 183 rotates, and the bypass capacitor 183 may be mounted on the first decorative substrate 56 in an inclined state. In this case, the connection area between the first pad 184a and the first electrode 183a by the solder fillet 186 becomes small, which may cause a connection failure. In addition, the bypass capacitor 183 may be mounted in a state where the first pad 184a and the first electrode 183a are not in electrical contact due to the rotation of the bypass capacitor 183. Furthermore, a chip rise where the bypass capacitor 183 stands on one electrode 183a on the first pad 184a is likely to occur. In this way, in the comparative example in which the lead-out positions of the wiring patterns 185a to 185d drawn from the first pad 184a and the second pad 184b are different, mounting failure of the bypass capacitor 183 is likely to occur.

In contrast, in the first decorative board 56 of this embodiment, as shown in Fig. 13(a), the first wiring pattern 172a is drawn out to the right from the first pad 171a, and the third wiring pattern 172c is drawn out to the right from the second pad 171b. The second wiring pattern 172b is drawn out to the left from the first pad 171a, and the fourth wiring pattern 172d is drawn out to the left from the second pad 171b. In a configuration in which the same number of wiring patterns 172a to 172d (specifically, two) are drawn out from the first pad 171a and the second pad 171b, the direction (rightward) along which the side of the first pad 171a from which the first wiring pattern 172a is drawn out is the same direction (rightward) as the direction (rightward) along which the side of the second pad 171b from which the third wiring pattern 172c is drawn out is, when viewed from the center of the second pad 171b, and the direction (leftward) along which the side of the first pad 171a from which the second wiring pattern 172b is drawn out is the same direction (leftward) as the direction (leftward) along which the side of the second pad 171b from which the fourth wiring pattern 172d is drawn out is, when viewed from the center of the second pad 171b. This prevents differences in temperature distribution within the pair of pads 171a, 171b during the initial heating stage of the reflow process, and also prevents the bypass capacitor 85 from rotating and becoming chip-standing.

The first decorative substrate 56 is mounted with a number of capacitors (not shown) whose longitudinal dimension along a plane perpendicular to the thickness direction is larger than that of small chip components, and in some of these capacitors, the direction in which the side of the first pad (or first pad) from which the first wiring pattern is drawn out exists when viewed from the center of the first pad (or first pad) electrically connected to the first electrode of the capacitor differs from the direction in which the side of the second pad (or second pad) from which the third wiring pattern is drawn out exists when viewed from the center of the second pad (or second pad) electrically connected to the second electrode of the capacitor. In the bypass capacitor 85, which is a small chip component, the direction along which the side of the first pad 171a from which the first wiring pattern 172a is drawn is the same as the direction along which the side of the second pad 171b from which the third wiring pattern 172c is drawn is the same as the direction along which the side of the first pad 171a from which the second wiring pattern 172b is drawn is the same as the direction along which the side of the first pad 171a from which the second wiring pattern 172b is drawn is the same as the direction (leftward) along which the side of the second pad 171b from which the fourth wiring pattern 172d is drawn is the same as the direction (leftward) along which the side of the second pad 171b from which the fourth wiring pattern 172d is drawn is the same as the direction (leftward) along which the bypass capacitor 85 is rotated and the chip standing is prevented.

As shown in FIG. 8(b), in the first pad 171a, the lead-out position of the first wiring pattern 172a electrically connected to the GND plane layer 93 (FIG. 9) through the via hole 174 is approximately the center in the vertical direction at the right end of the first pad 171a, and in the second pad 171b, the lead-out position of the third wiring pattern 172c electrically connected to the power plane layer 94 (FIG. 9) through the via hole 175 is approximately the center in the vertical direction at the right end of the second pad 171b. The GND plane layer 93 has a larger area than the first pad 171a, and the power plane layer 94 has a larger area than the second pad 171b.

In a configuration in which the first pad 171a is electrically connected to the GND plane layer 93 having a larger area than the first pad 171a via the first wiring pattern 172a, and the second pad 171b is electrically connected to the power plane layer 94 having a larger area than the second pad 171b via the third wiring pattern 172c, the direction (rightward) in which the side from which the first wiring pattern 172a is drawn out exists among the four sides of the first pad 171a as viewed from the center of the first pad 171a is the same direction as the direction (rightward) in which the side from which the third wiring pattern 172c is drawn out exists among the four sides of the second pad 171b as viewed from the center of the second pad 171b. This reduces the possibility of a difference in temperature distribution occurring within the pair of pads 171a and 171b during the initial heating stage of the reflow process.

As shown in FIG. 13A, the width of the first wiring pattern 172a drawn rightward from the right end of the first pad 171a is approximately the same as the width of the third wiring pattern 172c drawn rightward from the right end of the second pad 171b. Therefore, compared to a configuration in which the widths of these wiring patterns 172a and 172c are different, the possibility of a difference in temperature distribution in the pair of pads 171a and 171b occurring in the initial heating stage of the reflow process is reduced. In addition, the width of the second wiring pattern 172b drawn leftward from the left end of the first pad 171a is approximately the same as the width of the fourth wiring pattern 172d drawn leftward from the left end of the second pad 171b. Therefore, compared to a configuration in which the widths of these wiring patterns 172b and 172d are different, the possibility of a difference in temperature distribution in the pair of pads 171a and 171b occurring in the initial heating stage of the reflow process is reduced.

As already explained, the first wiring pattern 172a electrically connected to the GND plane layer 93 is pulled out from the right end of the first pad 171a, so the right side of the first pad 171a is more likely to experience a slower temperature rise in the initial heating stage than the left side of the first pad 171a. Also, the third wiring pattern 172c connected to the power plane layer 94 is pulled out from the right end of the second pad 171b, so the right side of the second pad 171b is more likely to experience a slower temperature rise in the initial heating stage than the left side of the second pad 171b. The number of wiring patterns 172a, 172c pulled out from the first pad 171a is the same as the number of wiring patterns 172b, 172d pulled out from the second pad 171b. Furthermore, the direction of the side from which the first wiring pattern 172a is drawn out among the four sides of the first pad 171a when viewed from the center of the first pad 171a is the same as the direction of the side from which the third wiring pattern 172c is drawn out among the four sides of the second pad 171b when viewed from the center of the second pad 171b, and the direction of the side from which the second wiring pattern 172b is drawn out among the four sides of the first pad 171a when viewed from the center of the first pad 171a is the same as the direction of the side from which the fourth wiring pattern 172d is drawn out among the four sides of the second pad 171b when viewed from the center of the second pad 171b. This makes it possible to balance the force acting on the first electrode 85a of the bypass capacitor 85 due to the surface tension of the molten solder on the first pad 171a and the force acting on the second electrode 85b of the bypass capacitor 85 due to the surface tension of the molten solder on the second pad 171b. Therefore, even if only the left side of the solder paste melts first in the pair of pads 171a, 171b, the movement of the bypass capacitor 85 is parallel, as shown in FIG. 13(c), and the rotation of the bypass capacitor 85 can be prevented. This makes it possible to suppress the degree of reduction in the connection area due to the solder fillet 173a between the first pad 171a and the first electrode 85a, and also to suppress the degree of reduction in the connection area due to the solder fillet 173b between the second pad 171b and the second electrode 85b.

Figure 14(a) is a plan view of the first mounting surface 84 of the first decorative substrate 56, showing an enlarged view of the peripheral area 187 (Figure 8(c)) of the small chip resistor 87, and Figure 14(b) is an explanatory diagram for explaining the relationship between the pads 176a, 176b of the peripheral area 187 and the solder resist 222. Also, Figure 14(c) is an explanatory diagram for explaining the movement mode of the small chip resistor 87 that may occur in this embodiment, and Figure 14(d) is an explanatory diagram for explaining the movement mode of the small chip resistor 191 that may occur in the comparative example. Note that in Figure 14(b), the solder resist 222 is shown hatched.

As shown in FIG. 14(a), the first pad 176a and the second pad 176b corresponding to the first electrode 87a and the second electrode 87b of the small chip resistor 87 are formed into an approximately rectangular shape. As shown in FIG. 14(b), the first pad 176a and the second pad 176b have the same shape and size as each other. The vertical dimension LB1 of the pads 176a and 176b is approximately 0.35 mm, which is larger than the short-side dimension (approximately 0.3 mm) of the small chip resistor 87. Since the pair of pads 176a and 176b have the same shape and size as each other, the amount of solder paste applied to the pair of pads 176a and 176b can be approximately the same. The vertical dimension LB1 of the pads 176a, 176b may be the same as the short-side dimension of the small chip resistor 87, or the vertical dimension LB1 of the pads 176a, 176b may be smaller than the short-side dimension of the small chip resistor 87.

The horizontal dimension LB2 of the pads 176a and 176b is approximately 0.32 mm. The first pad 176a and the second pad 176b are spaced apart at a predetermined distance LB3 (specifically, approximately 0.28 mm) in the longitudinal direction (first direction DR1) of the small chip resistor 87 (FIG. 14(a)). The distance (predetermined distance LB3) between the outer edge of the first pad 176a on the second pad 176b side and the outer edge of the second pad 176b on the first pad 176a side is set in the range of approximately 1/3 (0.2 mm) to approximately 1/2 (approximately 0.3 mm) of the longitudinal dimension of the small chip resistor 87 (approximately 0.6 mm). This allows the small chip resistor 87 to be mounted on the first decorative substrate 56 in such a way that the first electrode 87a of the small chip resistor 87 is located approximately in the center of the first pad 176a and the second electrode 87b is located approximately in the center of the second pad 176b in the longitudinal direction of the small chip resistor 87.

The solder resist 222 is not applied between the first pad 176a and the second pad 176b. If the solder resist 222 is applied to the narrow area between the first pad 176a and the second pad 176b, the probability of defective products occurring in which part or all of the pads 176a, 176b are covered with the solder resist 222 increases if there is a misalignment in the application area of the solder resist 222. In contrast, by not applying the solder resist 222 between the first pad 176a and the second pad 176b, it is possible to prevent part or all of these pads 176a, 176b from being covered with the solder resist 222 and to apply solder paste to the entire area of these pads 176a, 176b. This ensures the connection area between the first pad 176a and the first electrode 87a, ensuring the mechanical strength of the connection between the first pad 176a and the first electrode 87a, and also ensures the connection area between the second pad 176b and the second electrode 87b, ensuring the mechanical strength of the connection between the second pad 176b and the second electrode 87b.

As shown in FIG. 14(d), in the small chip resistor 191 in the comparative example, the first wiring pattern 193a is drawn out from the right end of the first pad 192a (or the first pad) toward the right, and the second wiring pattern 193b is drawn out from the left end of the second pad 192b (or the second pad) toward the left. The first wiring pattern 193a in the comparative example is a wiring pattern electrically connected to the second electrode 142b (FIG. 8(c)) of the LED chip 142, similar to the first wiring pattern 181a in the embodiment already described, and the second wiring pattern 193b in the comparative example is a wiring pattern electrically connected to the eighth output terminal 162 of the LED driver 126, similar to the second wiring pattern 181b in the embodiment already described. The right side of the first pad 192a from which the first wiring pattern 193a is drawn out is more likely to be delayed in temperature rise in the initial heating stage of the reflow process compared to the left side from which the wiring pattern is not drawn out. In addition, the left side of the second pad 192b from which the second wiring pattern 193b is drawn out is more likely to have a delayed temperature rise in the initial heating stage compared to the right side from which the wiring pattern is not drawn out. Therefore, in the initial heating stage, only the left side of the solder paste in the first pad 192a and only the right side of the solder paste in the second pad 192b are likely to melt, and as shown in FIG. 14(d), the normal direction of the first decorative substrate 56 becomes the rotation axis and the small chip resistor 191 rotates, and the small chip resistor 191 may be mounted on the first decorative substrate 56 in a tilted state. If the small chip resistor 191 is mounted in a tilted state, the connection area between the first pad 184a and the first electrode 183a by the solder fillet 194 becomes smaller, and the connection area between the second pad 184b and the second electrode 183b by the solder fillet 195 becomes smaller. In addition, due to the rotation of the small chip resistor 191, the small chip resistor 191 may be mounted without electrical contact between the first pad 192a and the first electrode 191a. Furthermore, the small chip resistor 191 is likely to stand up on the first pad 192a with one electrode 191a. Thus, in the comparative example in which the lead-out positions of the wiring patterns 193a, 193b are different for the pair of pads 192a, 192b, mounting defects of the small chip resistor 191 are likely to occur.

In contrast, in the first decorative board 56 of this embodiment, as shown in Fig. 14(a), the first wiring pattern 181a is drawn out to the right from the right end of the first pad 176a, and the second wiring pattern 181b is drawn out to the right from the right end of the second pad 176b. The drawing position of the first wiring pattern 181a is approximately the center in the vertical direction at the right end of the first pad 176a, and the drawing position of the second wiring pattern 181b is approximately the center in the vertical direction at the right end of the second pad 176b. In a configuration in which the same number of wiring patterns 181a, 181b (specifically, one) are drawn out from the first pad 176a and the second pad 176b, the direction (rightward) of the side from which the first wiring pattern 181a is drawn out when viewed from the center of the first pad 176a out of the four sides of the first pad 176a is the same direction as the direction (rightward) of the side from which the second wiring pattern 181b is drawn out when viewed from the center of the second pad 176b out of the four sides of the second pad 176b. This makes it possible to prevent differences in temperature distribution within the pair of pads 176a, 176b during the initial heating stage of the reflow process, and to prevent rotation and chip standing of the small chip resistor 87.

The first decorative board 56 is equipped with a plurality of resistors (not shown) whose longitudinal dimension along a plane perpendicular to the thickness direction is larger than that of the small chip components, and in some of these resistors, the direction in which the first wiring pattern is drawn out of the four sides of the first pad (or first pad) electrically connected to the first electrode of the resistor is different from the direction in which the second wiring pattern is drawn out of the four sides of the second pad (or second pad) electrically connected to the second electrode of the resistor is different from the direction in which the second wiring pattern is drawn out of the four sides of the second pad (or second pad) electrically connected to the second electrode of the resistor is different from the direction in which the second wiring pattern is drawn out of the four sides of the first pad 176a is the same as the direction in which the first wiring pattern 181a is drawn out of the four sides of the first pad 176a is the same as the direction in which the second wiring pattern 181b is drawn out of the four sides of the second pad 176b is the same as the direction in which the second wiring pattern 181b is drawn out of the four sides of the second pad 176b. This prevents the small chip resistor 87 from rotating and the chip from standing up.

The right end of the first pad 176a is the lead-out position of the first wiring pattern 181a, so the temperature rise is more likely to be delayed in the initial heating stage than the left end of the first pad 176a. Also, the right end of the second pad 176b is the lead-out position of the second wiring pattern 181b, so the temperature rise is more likely to be delayed in the initial heating stage than the left end of the second pad 176b. The number of wiring patterns 181a drawn out from the first pad 176a is the same as the number of wiring patterns 181b drawn out from the second pad 176b. The direction (rightward) in which the side from which the first wiring pattern 181a is drawn out exists among the four sides of the first pad 176a as viewed from the center of the first pad 176a is the same direction as the direction in which the side from which the second wiring pattern 181b is drawn out exists among the four sides of the second pad 176b as viewed from the center of the second pad 176b. This makes it possible to balance the force acting on the first electrode 87a of the small chip resistor 87 due to the surface tension of the molten solder on the first pad 176a and the force acting on the second electrode 87b of the small chip resistor 87 due to the surface tension of the molten solder on the second pad 176b. Therefore, even if only the left side of the solder paste of the pair of first pad 176a and second pad 176b melts first, as shown in FIG. 14(c), the movement mode of the small chip resistor 87 is parallel movement, and the rotation of the small chip resistor 87 can be prevented. This makes it possible to suppress the degree of reduction in the connection area due to the solder fillet 177a between the first pad 176a and the first electrode 87a, and to suppress the degree of reduction in the connection area due to the solder fillet 177b between the second pad 176b and the second electrode 87b.

As already explained, the first pad 176a electrically connected to the first electrode 87a of the small chip resistor 87 is electrically connected to the second pad 178b electrically connected to the second electrode 142b of the LED chip 142 via the first wiring pattern 181a (see FIG. 8(c)). Also, as already explained, the second pad 176b electrically connected to the second electrode 87b of the small chip resistor 87 is electrically connected to a pad (or pad, not shown) electrically connected to the eighth output terminal 162 (FIG. 11) of the LED driver 126 (FIG. 8(a)) via the second wiring pattern 181b. As shown in FIGS. 8(a) and 8(c), the second pad 178b connected to the first pad 176a is located in the upward direction, and the pad (or pad, not shown) corresponding to the eighth output terminal 162 connected to the second pad 176b is located in the upper left direction. The location where the second wiring pattern 181b is connected in the pad (not shown) corresponding to the eighth output terminal 162 is located in the opposite direction to the direction in which the second wiring pattern 181b is pulled out from the second pad 176b when viewed in the direction of one axis (second direction DR2 in FIGS. 8A and 8C) including the direction in which the second wiring pattern 181b is pulled out from the second pad 176b (rightward in FIGS. 8A and 8C). The second wiring pattern 181b is pulled out from the second pad 176b in the same direction (rightward) as the direction in which the first wiring pattern 181a is pulled out from the first pad 176a, and then routed in the opposite direction when viewed in the direction of the one axis (second direction DR2) with the second pad 176b as the reference.

Even in a configuration in which the second wiring pattern 181b is connected to the connection destination at a location that is in the opposite direction to the direction in which the second wiring pattern 181b is pulled out from the second pad 176b when viewed in the direction of one axis (second direction DR2), the second wiring pattern 181b is pulled out from the second pad 176b in the same direction as the direction in which the first wiring pattern 181a is pulled out from the first pad 176a. This reduces the possibility of a difference in temperature distribution occurring within the pair of first pad 176a and second pad 176b during the initial heating stage of the reflow process.

As shown in FIG. 14(a), the width of the first wiring pattern 181a drawn rightward from the right end of the first pad 176a is approximately the same as the width of the second wiring pattern 181 drawn rightward from the right end of the second pad 176b. Therefore, compared to a configuration in which the widths of the wiring patterns 181a and 181b drawn from the pads 176a and 176b are different, the possibility of a difference in temperature distribution occurring within the pair of pads 176a and 176b during the initial heating stage of the reflow process is reduced.

As already explained with reference to Figures 8(a) to 8(c), in the first decorative substrate 56, the small chip components are mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip components is parallel to the first direction DR1 (the longitudinal direction of the first decorative substrate 56). Therefore, compared to a case in which the longitudinal direction of the small chip components is mounted on the first decorative substrate 56 in such a manner that it is perpendicular to the first direction DR1 (the longitudinal direction of the first decorative substrate 56), the maximum value of the stress that can act on the connection point between the small chip components and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56 is reduced, and the maximum value of the stress that can act on the small chip components themselves is reduced.

As described above, the first decorative substrate 56 is equipped with a number of capacitors (not shown) whose longitudinal dimensions along a plane perpendicular to the thickness direction are larger than those of the small chip components. Some of these capacitors are mounted on the first decorative substrate 56 in such a way that the longitudinal direction of the capacitors is not parallel to the first direction DR1. The small chip components are protected by being mounted on the first decorative substrate 56 in such a way that the longitudinal direction of the small chip components is perpendicular to the first direction DR1.

10(b), the bypass capacitor 97 is mounted on the second decorative substrate 57 in such a manner that the longitudinal direction of the bypass capacitor 97 is parallel to the longitudinal axis direction LD of the second decorative substrate 57. Also, as shown in FIG. 10(c), the small chip resistor 101 is mounted on the second decorative substrate 57 in such a manner that the longitudinal direction of the small chip resistor 101 is parallel to the longitudinal axis direction LD of the second decorative substrate 57. In this way, the small chip components (bypass capacitor 97 and small chip resistor 101) are mounted on the second decorative substrate 57 with their longitudinal direction parallel to the longitudinal axis direction LD of the second decorative substrate 57. Compared to a case where the small chip components are mounted on the second decorative substrate 57 with their longitudinal direction perpendicular to the longitudinal axis direction LD of the second decorative substrate 57, the maximum value of stress that can act on the connection points between the small chip components and the second decorative substrate 57 when distortion occurs in the second decorative substrate 57 is reduced, and the maximum value of stress that can act on the small chip components themselves is reduced.

8B, in the first decorative board 56, the first wiring pattern 172a drawn from the first pad 171a and the third wiring pattern 172c drawn from the second pad 171b extend in a direction perpendicular to the longitudinal direction of the bypass capacitor 85 (one of the short sides of the bypass capacitor 85). The second wiring pattern 172b drawn from the first pad 171a and the fourth wiring pattern 172d drawn from the second pad 171b extend in a direction perpendicular to the longitudinal direction of the bypass capacitor 85 (the other of the short sides of the bypass capacitor 85). In this way, the wiring patterns 172a to 172d drawn from the pads 171a and 171b of the bypass capacitor 85 extend in a direction perpendicular to the longitudinal direction of the bypass capacitor 85 (the short side). In addition, the wiring patterns 172a to 172d extending from the pads 171a and 171b of the bypass capacitor 85 may be configured to extend in a direction substantially perpendicular to the longitudinal direction of the bypass capacitor 85.

As already explained, the pads 171a, 171b and the wiring patterns 172a to 172d are integrally formed, and the electrodes 85a, 85b of the bypass capacitor 85 are fixed to the pads 171a, 171b by the solder fillets 173a, 173b. If the wiring patterns 172a to 172d drawn out from the pads 171a, 171b are configured to extend in a direction parallel to the longitudinal direction of the bypass capacitor 85, when a force that bends the first decorative substrate 56 from a folding line extending in a direction perpendicular or substantially perpendicular to the longitudinal direction acts on the first decorative substrate 56, the connection between the bypass capacitor 85 and the first decorative substrate 56 is likely to be damaged, and the bypass capacitor 85 itself is likely to be damaged. In addition, in this configuration, the stress acting on the periphery of the bypass capacitor 85 due to the distortion of the first decorative substrate 56 is likely to be transmitted to the bypass capacitor 85 itself, and the bypass capacitor 85 is likely to be damaged. In contrast, by configuring the wiring patterns 172a-172d drawn out from the pads 171a, 171b to extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 85, the maximum value of stress that can act on the connection between the bypass capacitor 85 and the first decorative board 56 when distortion occurs in the first decorative board 56 is reduced, and the maximum value of stress that can act on the bypass capacitor 85 itself when distortion occurs in the first decorative board 56 is reduced. This makes it possible to prevent damage to the connection between the bypass capacitor 85 and the first decorative board 56, and also to prevent damage to the bypass capacitor 85 itself.

As described above, the first decorative substrate 56 is equipped with a number of capacitors (not shown) whose longitudinal dimensions along a plane perpendicular to the thickness direction are larger than those of the small chip components, and in some of these capacitors, the wiring patterns extending from the pads (or pads) electrically connected to the electrodes of the capacitor are extended in a direction different from the direction perpendicular or nearly perpendicular to the longitudinal direction of the capacitor. The bypass capacitor 85, which is a small chip component, is protected by configuring the wiring patterns 172a-172d extending from the pads 171a, 171b to extend in a direction perpendicular or nearly perpendicular to the longitudinal direction of the bypass capacitor 85.

As already explained, the wiring patterns 181a, 181b drawn from the pads 176a, 176b of the small chip resistor 87 extend in the second direction DR2 (short direction of the small chip resistor 87) perpendicular to the longitudinal direction of the small chip resistor 87. Also, as already explained, the small chip resistor 87 is electrically connected to the wiring patterns 181a, 181b by the solder fillets 177a, 177b that electrically contact the electrodes 87a, 87b and the pads 176a, 176b. If the wiring patterns 181a, 181b drawn from the pads 176a, 176b are configured to extend in a direction parallel to the longitudinal direction of the small chip resistor 87, the stress acting around the bypass capacitor 85 due to the distortion of the first decorative substrate 56 is easily transmitted to the bypass capacitor 85 itself, and the bypass capacitor 85 is easily damaged. In response to this, the wiring patterns 181a, 181b extending from the pads 176a, 176b of the small chip resistor 87 extend in a direction perpendicular to the longitudinal direction of the small chip resistor 87 (the short direction of the small chip resistor 87) or in a direction substantially perpendicular thereto, thereby reducing the maximum stress that can act on the small chip resistor 87. This makes it possible to prevent damage to the connection between the small chip resistor 87 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56.

As described above, the first decorative substrate 56 is equipped with a number of resistors (not shown) whose longitudinal dimension along a plane perpendicular to the thickness direction is larger than that of the small chip components, and in some of these resistors, the wiring pattern extending from the pads (or pads) electrically connected to the electrodes of the resistors is extended in a direction different from the direction perpendicular or substantially perpendicular to the longitudinal direction of the resistor. The small chip resistor 87, which is a small chip component, is protected by a configuration in which the wiring patterns 181a, 181b extending from the pads 176a, 176b extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of the small chip resistor 87.

As shown in Figures 8(a) to 8(c), in the first decorative board 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149 (Figure 11)) are mounted only on the first mounting surface 84, and are not mounted on the second mounting surface 95. In the first decorative board 56, in a configuration in which the small chip components are concentrated on the first mounting surface 84, the LED chips 127 to 142 (Figure 11) and the LED driver 126 are also mounted on the first mounting surface 84.

Figure 15(a) is a plan view showing the second mounting surface 95 of the first decorative substrate 56, and Figure 15(b) is a plan view of the second mounting surface 95 of the first decorative substrate 56 showing an enlarged view of the backside area 205 of the first light-emitting circuit section 121. As shown in Figure 15(b), no small chip components are mounted in the LED backside corresponding area 201 of the second mounting surface 95. The LED backside corresponding area 201 is the area of the second mounting surface 95 located on the back side of the area in which the LED chips 127-142 (Figure 9) are mounted on the first mounting surface 84 (Figure 8(a)), and is an area within 1 mm away from the outer edge of the area of the second mounting surface 95. Since the small chip components are not mounted in the area of the second mounting surface 95 located on the back side of the area where the LED chips 127-142 are mounted on the first mounting surface 84, the influence of thermal stress that may act on the first decorative board 56 due to heat generated by the LED chips 127-142 on the small chip components is reduced. The LED back side corresponding area 201 is an area that is repeatedly heated by the heat generated when the LED chips 127-142 are driven, and is an area where distortion due to heat of the first decorative board 56 is likely to occur. If the small chip components are mounted in the LED back side corresponding area 201, there is a risk that the load of thermal stress will accumulate at the connection point between the small chip components and the first decorative board 56 due to the repeated execution of the light emission performance on the first decorative board 56, and there is also a risk that the load of thermal stress will accumulate on the small chip components themselves. In contrast, by mounting the small chip components in a manner that avoids the LED backside corresponding area 201, it is possible to prevent damage to the connection points between the small chip components and the first decorative substrate 56 caused by the repeated execution of light-emitting effects on the first decorative substrate 56, and it is also possible to prevent damage to the small chip components themselves.

As shown in FIG. 15B, no small chip components are mounted in the driver back side corresponding region 202 of the second mounting surface 95. The driver back side corresponding region 202 is the region of the second mounting surface 95 located on the back side of the region where the LED driver 126 (FIG. 8A) is mounted on the first mounting surface 84 (FIG. 8A) and the region where the pads (or pads) corresponding to the terminals of the LED driver 126 are provided, and the region within 1 mm from the outer edge of the region of the second mounting surface 95. Since no small chip components are mounted in the region of the second mounting surface 95 located on the back side of the region where the LED driver 126 is mounted on the first mounting surface 84, the influence of thermal stress that may act on the first decorative substrate 56 due to heat generated by the LED driver 126 on the small chip components is reduced. The driver back side corresponding region 202 is an area that is repeatedly heated by heat generated when the LED driver 126 is driven, and is an area where the first decorative substrate 56 is likely to be distorted by heat. If small chip components are mounted in the driver backside corresponding area 202, repeated light-emitting effects on the first decorative substrate 56 may cause thermal stress loads to accumulate at the connection points between the small chip components and the first decorative substrate 56, and thermal stress loads may accumulate in the small chip components themselves. In contrast, by mounting the small chip components avoiding the driver backside corresponding area 202, damage to the connection points between the small chip components and the first decorative substrate 56 caused by repeated light-emitting effects on the first decorative substrate 56 can be prevented, and damage to the small chip components themselves can be prevented.

As shown in Figures 8(a) to 8(c), in the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistor 87) are arranged at a distance of 1 mm or more from the outer edge of the LED chip 142. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, it is possible to prevent the connection points between the small chip components and the first decorative substrate 56 from being damaged by thermal stress, and it is also possible to prevent the small chip components themselves from being damaged by thermal stress.

As shown in Figures 8(a) to 8(c), in the first decorative substrate 56, the small chip components (bypass capacitors 85 and small chip resistors 87) are arranged at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126, it is possible to prevent the connection points between the small chip components and the first decorative substrate 56 from being damaged by thermal stress, and it is also possible to prevent the small chip components themselves from being damaged by thermal stress.

As shown in Figures 8(a) to 8(c), in the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149 (Figure 11)) are arranged to avoid the through-hole peripheral areas 211a-211d. The through-hole peripheral areas 211a-211d are areas that are less than 5 mm away from the outer edges of the fixing through-holes 56d-56g. When the first decorative substrate 56 is screwed to the front door frame 14, a force that causes distortion in the first decorative substrate 56 may act on the through-hole peripheral areas 211a-211d. By positioning the small chip components at least 5 mm away from the outer edge of the fixing through holes 56d-56g, it is possible to prevent damage to the connection points between the small chip components and the first decorative substrate 56 caused by distortion of the first decorative substrate 56 that may occur near the fixing through holes 56d-56g when the first decorative substrate 56 is screwed to the front door frame 14, and it is also possible to prevent damage to the small chip components themselves.

As shown in FIG. 8(a), the fixing through holes 56d-56g are provided at the corners of the first decorative substrate 56. Therefore, compared to a configuration in which the fixing through holes 56d-56g are provided near the center of the first decorative substrate 56, the area of the first decorative substrate 56 where small chip components cannot be mounted is reduced.

As already explained, the fixing through-hole 56e is provided in the protruding portion 56c of the stepped recess 56a. This makes it possible to stably fix the first decorative substrate 56 to the front door frame 14 while ensuring an area in which small chip components can be mounted.

In a configuration in which small chip components are concentrated on the first mounting surface 84, as shown in FIG. 15(a), the connectors 111 and 112 are concentrated on the second mounting surface 95. As shown in FIG. 8(a), the small chip components are arranged on the first mounting surface 84, avoiding the connector back side corresponding areas 203 and 204. The connector back side corresponding areas 203 and 204 are areas of the first mounting surface 84 located on the back side of the area in which the connectors 111 and 112 are mounted on the second mounting surface 95 (FIG. 15(a)) and areas that are less than 5 mm away from the outer edge of the area of the first mounting surface 84. Since small chip components are not mounted on the area of the first mounting surface 84 located on the back side of the area in which the connectors 111 and 112 are mounted on the second mounting surface 95, the effect of stress acting on the first decorative substrate 56 on the small chip components when the harness is attached to and detached from the connectors 111 and 112 is reduced. The connector back side corresponding areas 203, 204 are areas where tensile stress is likely to act when a harness (not shown) is attached to the connectors 111, 112, and where compressive stress is likely to act when the harness is removed from the connectors 111, 112. If small chip components are mounted in the connector back side corresponding areas 203, 204, stress may act on the connection between the small chip components and the first decorative substrate 56 when the harness is attached to or detached from the connectors 111, 112, and stress may act on the small chip components themselves. In contrast, the small chip components are arranged to avoid the connector back side corresponding areas 203, 204, so that the connection between the small chip components and the first decorative substrate 56 is prevented from being damaged when the harness is attached to or detached from the connectors 111, 112, and the small chip components themselves are prevented from being damaged.

As shown in FIG. 8(a), the LED driver 126 is arranged in an area including an area less than 10 mm from the outer edge of the first decorative substrate 56, while the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149 (FIG. 11)) are arranged 10 mm or more away from the outer edge of the first decorative substrate 56. As already explained, the connection points between the small chip components and the first decorative substrate 56 among the various electronic components mounted on the first decorative substrate 56 have lower mechanical strength than the connection points between the other electronic components and the first decorative substrate 56. By arranging the small chip components 10 mm or more away from the outer edge of the first decorative substrate 56, the possibility of the connection points between the small chip components and the first decorative substrate 56 being damaged by the hand of an operator touching the small chip components when handling the first decorative substrate 56 is reduced, and the possibility of the small chip components themselves being damaged is also reduced.

In a configuration in which the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are arranged to avoid the through-hole peripheral areas 211a-211d and areas less than 10 mm away from the outer edge of the first decorative substrate 56, the fixing through holes 56d-56g are provided in areas less than 10 mm away from the outer edge of the first decorative substrate 56. Therefore, compared to a configuration in which the fixing through holes 56d-56g are provided at positions 10 mm or more away from the outer edge of the first decorative substrate 56, a larger area is ensured in the first decorative substrate 56 in which small chip components can be mounted.

8(b), the LED driver 126 on the first decorative board 56 is surrounded by an outer silk 213 that allows the mounting position of the LED driver 126 to be grasped, and an identification silk 214 (indicated as "IC1") that allows the mounted electronic component to be recognized as the LED driver 126. Also, as shown in FIG. 8(c), the LED chip 142 is surrounded by an outer silk 215 that allows the mounting position of the LED chip 142 to be grasped, and an identification silk 216 (indicated as "LED16") that allows the mounted electronic component to be recognized as the LED chip 142. As shown in FIG. 9, the first wiring layer 91 is covered with a solder resist 222. The outer silk 213 and the identification silk 214 are printed in a manner that convexly extends from the first mounting surface 84. The outer silk 213, 215 and the identification silk 214, 216 are printed before the electronic components are mounted on the first decorative board 56.

After mounting electronic components including small chip components on the first decorative board 56, when visually checking that no electronic components have been omitted, the worker can determine whether the electronic components have been mounted in the correct position by comparing the location where the outline silks 213, 215 are provided with the location where the electronic components (LED driver 126 and LED chip 142) are mounted. In addition, the worker can determine the type of electronic components (LED driver 126 and LED chip 142) that have been mounted based on the display contents of the identification silks 214, 216.

8B, only the identification silk 217 (indicated as "C1") that allows confirmation that the mounted electronic component is the bypass capacitor 85 is provided around the bypass capacitor 85, and no outline silk that allows the mounting position of the bypass capacitor 85 to be grasped is provided. As already explained, the outside dimensions (length, width, and height) of the bypass capacitor 85 are smaller than the outside dimensions of electronic components other than small chip components (such as the LED driver 126 and the LED chips 127 to 142). For this reason, if the outline silk of the bypass capacitor 85 is printed on the first decorative board 56, there is a risk that the worker will mistakenly recognize that the bypass capacitor 85 is mounted by looking only at the outline silk, even though the bypass capacitor 85 is actually missing after the electronic components are mounted. In contrast, by configuring the bypass capacitor 85 so that no outline silk is provided around it, it is easier to grasp the missing mounting of the bypass capacitor 85 after the electronic components are mounted. In addition, by providing an identification silk 217 around the bypass capacitor 85, it is possible to identify that the component mounted around the identification silk 217 is the bypass capacitor 85.

As already explained, the external dimensions of the small chip resistor 87 are smaller than those of electronic components other than the small chip components, similar to the external dimensions of the bypass capacitor 85. As shown in FIG. 8C, only the identification silk 218 (indicated as "R8") that enables confirmation that the mounted electronic component is the small chip resistor 87 is provided around the small chip resistor 87, and no contour silk that enables confirmation of the mounting position of the small chip resistor 87 is provided. This makes it easier to grasp the mounting omission of the small chip resistor 87. In addition, by providing the identification silk 218 around the small chip resistor 87, it is possible to grasp that the electronic component mounted around the identification silk 218 is the small chip resistor 87. In addition, when the electronic component is mounted on the first decorative board 56 using an automatic mounting device, the automatic mounting device mounts the electronic component by coordinate control from the reference position on the first decorative board 56, so even if a configuration is configured in which contour silk is not provided around the small chip component, the mounting position of the small chip component will not shift.

The character size of the identification silk 217, 218 provided around the small chip components (bypass capacitor 85 and small chip resistor 87) is the same as the character size of the identification silk 214, 216 provided around the electronic components (LED driver 126 and LED chip 142) that are larger than the small chip components. This makes it easy to visually check the identification silk 217, 218 provided around the small chip components.

16(a) is a cross-sectional view of the first decorative board 56 in this embodiment, and FIG. 16(b) is a cross-sectional view of the first decorative board 224 in the comparative example. As already described, the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 are formed at an interval of approximately 0.28 mm in the longitudinal direction of the bypass capacitor 85. Also, as already described, the solder resist 222 is not applied between the first pad 171a and the second pad 171b (see FIG. 16(a)). In the process of applying solder paste to the first decorative board 56, the first mounting surface 84 and the second mounting surface 95 (FIG. 9) of the first decorative board 56 are masked by a metal mask 226 in which an opening is formed. The metal mask 226 is, for example, a thin metal plate having a thickness of approximately 150 μm. The metal mask 226 has openings penetrating the metal mask 226 in the thickness direction at positions corresponding to the pads (or pads) of the first decorative board 56. Solder paste is applied onto the pads through openings in metal mask 226. The uniform thickness of metal mask 226 allows the solder paste to be applied evenly to each pad.

As shown in FIG. 16B, the outer silks 225a and 225b are convex with respect to the surface of the solder resist 222. If the outer silks 225a and 225b are provided around the small chip components (bypass capacitor 85 and small chip resistor 87 (FIGS. 8B and 8C)), the outer silks 225a and 225b will be present between the first mounting surface 84 and the metal mask 226, and the distance between the first mounting surface 84 and the metal mask 226 will increase. In this configuration, the solder paste 227 may get into the gap between the first pad 171a and the second pad 171b, and the first pad 171a and the second pad 171b may be electrically connected. In particular, when the solder paste 221 is applied continuously to a large number of first decorative substrates 56, the solder paste 221 that accumulates on the edge of the opening of the metal mask 226 tends to flow around the back side of the opening, and the first pad 171a and the second pad 171b tend to be electrically connected. In contrast, in this embodiment, as shown in FIG. 16(a), no outline silk is provided around the small chip components. This prevents the distance between the first mounting surface 84 and the metal mask 226 from becoming too large, and prevents solder defects caused by the solder paste 221 getting between the pads 171a and 171b. It also prevents parts of the small chip components from being placed on the outline silk, which can cause solder defects.

Next, we will explain how to manufacture the decorative substrates 56 and 57.

As a method for efficiently manufacturing the first decorative board 56, a method is considered in which electronic components are mounted on an aggregate board (printed wiring board before electronic components are mounted) including a plurality of first decorative boards 56, and then the aggregate board is divided to take out a plurality of first decorative boards 56 with electronic components mounted at once. Also, as a method for efficiently manufacturing the second decorative board 57, a method is considered in which electronic components are mounted on an aggregate board (printed wiring board before electronic components are mounted) including a plurality of second decorative boards 57, and then the aggregate board is divided to take out a plurality of second decorative boards 57 with electronic components mounted at once. By manufacturing the decorative boards 56, 57 by these methods, it is possible to reduce the number of times the process of mounting electronic components is performed and to increase the manufacturing efficiency of the decorative boards 56, 57, compared to the case of manufacturing the decorative boards 56, 57 with electronic components mounted one by one. Below, the method for manufacturing the decorative boards 56, 57 will be described using the method for efficiently manufacturing the first decorative board 56 as an example.

Figure 17(a) is a plan view showing the first plate surface 268, which is the plate surface on one side of the collective substrate 231, Figure 17(b) is an explanatory diagram for explaining the valley splitting in which the collective substrate 231 is split so that the first plate surface 268 has a valley shape (concave), and Figure 17(c) is an explanatory diagram for explaining the mountain splitting in which the collective substrate 231 is split so that the first plate surface 268 has a mountain shape (convex). Note that, in reality, multiple electronic components are mounted on each of the first decorative substrates 56 included in the collective substrate 231, and wiring patterns and the like are also formed, but in Figures 17(a) to 17(c) they are illustrated in a simplified manner to avoid complicating the drawings.

The collective board 231 is a four-layer board with a structure in which conductive layers and insulating layers are alternately stacked, similar to the decorative boards 56 and 57 already described. As shown in FIG. 17(a), the collective board 231 is created by cutting out a portion of a printed wiring board formed into an approximately square shape by a router process in which a drill-shaped cutting tool (router) with a blade on the side is rotated while processing, and by forming dividing grooves 232-247 and slits 251-258 in the printed wiring board.

The collective substrate 231 is divided into four first decorative substrates 56 and seven waste substrates 261-267 by the dividing grooves 232-247 and the slits 251-258. The process of forming the dividing grooves 232-247 and the slits 251-258 in the collective substrate 231 is carried out before electronic components are mounted on the collective substrate 231. The collective substrate 231 is divided using the dividing grooves 232-247 and the slits 251-258.

The dividing grooves 232-247 are formed in a straight line by cutting the collective substrate 231 using, for example, a disk-shaped blade rotating at high speed. The dividing grooves 232-247 have a V-shaped cross section that reduces the thickness of the collective substrate 231, and the bottoms of the dividing grooves 232-247 are the parts with the thinnest thickness. The area of the collective substrate 231 where the dividing grooves 232-247 are formed has a lower mechanical strength than the area where the dividing grooves 232-247 are not formed. Therefore, by dividing the collective substrate 231 using the dividing grooves 232-247 as base points, the stress acting on the first decorative substrate 56 when dividing the collective substrate 231 can be reduced. This makes it possible to reduce the stress that may act on the connection points between the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149) and the first decorative substrate 56 when dividing the collective substrate 231, and also to reduce the stress that may act on the small chip components themselves. It is also possible to prevent the base point of division from shifting from the division grooves 232 to 247. The cross-sectional shape of the division grooves 232 to 247 is not limited to a V-shape. The cross-sectional shape of the division grooves 232 to 247 may be rectangular or U-shaped as long as it allows the collective substrate 231 to be easily separated by an external force.

By forming the dividing grooves 232-247 in a straight line, the stress that may act on the first decorative substrate 56 when the assembly substrate 231 is divided is reduced compared to a configuration in which the dividing grooves 232-247 are formed in a curved line.

In this embodiment, the dividing grooves 232-247 are formed only on the first plate surface 268 side of the collective substrate 231 in order to make it easier to distinguish between the first plate surface 268 and the second plate surface 269 (FIG. 17(b)), which is the plate surface opposite the first plate surface 268, and to improve the workability of the substrate dividing process. The slits 251-258 are formed, for example, by the router processing described above. The slits 251-258 are elongated long holes, and are formed wider than the dividing grooves 232-247.

As shown in FIG. 17(a), a vertically elongated, generally rectangular central discarded substrate 261 is provided in the center of the collective substrate 231 in the left-right direction. A pair of first decorative substrates 56 are provided on the left side of the central discarded substrate 261 across the dividing grooves 232, 233, and a pair of first decorative substrates 56 are provided on the right side of the central discarded substrate 261 across the dividing grooves 234, 235. The four first decorative substrates 56 are flush, and the first mounting surfaces 84 of these first decorative substrates 56 are present on the first plate surface 268 side of the collective substrate 231.

As already explained, the first decorative substrate 56 has a stepped recess 56a and a cutout 56b. In the lower left first decorative substrate 56, the stepped recess 56a is provided on the side of the central discarded substrate 261, and the cutout 56b is provided on the side of the left discarded substrate 263, which will be described later. In the upper left first decorative substrate 56, the stepped recess 56a is provided on the side of the left discarded substrate 263, and the cutout 56b is provided on the side of the central discarded substrate 261. The stepped recesses 56a of the pair of first decorative substrates 56 face each other. The space between these stepped recesses 56a is cut out, and the stepped recesses 56a are not connected to each other.

In the first decorative substrate 56 at the bottom right, the stepped recess 56a is provided on the side of the right-side discarded substrate 266 described below, and the cutout 56b is provided on the side of the central discarded substrate 261. In the first decorative substrate 56 at the top right, the stepped recess 56a is provided on the side of the central discarded substrate 261, and the cutout 56b is provided on the side of the right-side discarded substrate 266. The stepped recesses 56a of the pair of first decorative substrates 56 face each other. The space between these stepped recesses 56a is cut out, and the stepped recesses 56a are not connected to each other.

On the left side of the central discarded board 261, the lower left discarded board 262, the vertically elongated, approximately rectangular left discarded board 263, and the upper left discarded board 264 are provided on the lower, left, and upper sides of the pair of first decorative boards 56. The lower left discarded board 262 is connected to the left discarded board 263 and the central discarded board 261 via the dividing grooves 236 and 237, and the upper left discarded board 264 is connected to the left discarded board 263 and the central discarded board 261 via the dividing grooves 238 and 239. A slit 251 is formed between the lower left discarded board 262 and the upper left first decorative board 56, and the lower left discarded board 262 and the upper left first decorative board 56 are not connected. In addition, a slit 252 is formed between the upper left discarded board 264 and the upper right first decorative board 56, and the upper left discarded board 264 and the upper right first decorative board 56 are not connected. The left-side discarded substrate 263 is connected to the lower left first decorative substrate 56 and the upper left first decorative substrate 56 via the dividing grooves 240 and 241.

On the right side of the central discarded board 261, a lower right discarded board 265, a vertically elongated, approximately rectangular right discarded board 266, and an upper right discarded board 267 are provided on the lower, right, and upper sides of the pair of first decorative boards 56. The lower right discarded board 265 is connected to the central discarded board 261 and the right right discarded board 266 via the dividing grooves 242 and 243, and the upper right discarded board 267 is connected to the central discarded board 261 and the right right discarded board 266 via the dividing grooves 244 and 245. A slit 253 is formed between the lower right discarded board 265 and the lower left first decorative board 56, and the lower right discarded board 265 and the lower left first decorative board 56 are not connected. In addition, a slit 254 is formed between the upper right discarded board 267 and the lower right first decorative board 56, and the upper right discarded board 267 and the lower right first decorative board 56 are not connected. The right-side discarded substrate 266 is connected to the lower-left first decorative substrate 56 and the lower-right first decorative substrate 56 via the dividing grooves 246 and 247.

In this way, the discarded boards 262-267 are provided around the entire outer periphery of the collective substrate 231, and the four first decorative substrates 56 are surrounded by the discarded boards 262-267. This makes it possible to handle the collective substrate 231 after mounting the electronic components without touching the electronic components mounted on the first decorative substrate 56. This prevents the electronic components from being damaged by the worker's hands touching the electronic components. The number of first decorative substrates 56 included in the collective substrate 231 is not limited to "4". The number of first decorative substrates 56 included in the collective substrate 231 may be more than "4" (for example, "6"), or the number of first decorative substrates 56 included in the collective substrate 231 may be less than "4" (for example, "2").

A pair of first decorative substrates 56 are provided on the left side of the central discarded substrate 261 with their stepped recesses 56a facing each other, and a pair of first decorative substrates 56 are provided on the right side of the central discarded substrate 261 with their stepped recesses 56a facing each other, thereby reducing the vertical dimension of the aggregate substrate 231 including the four first decorative substrates 56.

Next, the manufacturing process for the decorative substrates 56 and 57 will be explained using the manufacturing process for the first decorative substrate 56 as an example.

In the manufacturing process of the first decorative board 56, first, with the second board surface 269 (second mounting surface 95 side, see FIG. 17(b)) of the collective board 231 facing up, a solder application process is performed to apply solder paste to the pads (or pads) provided on the second board surface 269 of the collective board 231, an adhesive application process is performed to apply an adhesive for fixing the connectors, a component mounting process is performed to mount the connectors 111, 112 (FIG. 8(a)) on the second board surface 269 side of the collective board 231 using an automatic mounting device (not shown), a reflow process is performed to transport the collective board 231 to a reflow furnace and heat it, and a cooling process is performed to cool the collective board 231 to room temperature. As a result, the connectors 111, 112 are mounted on the second board surface 269 side of the collective board 231. The adhesive hardens to prevent the connectors 111, 112 from falling off during the second reflow process.

After that, with the first surface 268 of the collective substrate 231 facing upward, a solder application process is performed in which solder paste is applied onto the lands provided on the first surface 268 side (first mounting surface 84 side) of the collective substrate 231, a component mounting process is performed in which electronic components including small chip components are mounted on the first surface 268 side of the collective substrate 231 using an automatic mounting device (not shown), a reflow process is performed in which the collective substrate 231 is transported to a reflow furnace and heated, a cooling process is performed in which the collective substrate 231 is cooled to room temperature, a substrate division process is performed in which the collective substrate 231 is divided after the electronic components are mounted, and a mounting confirmation process is performed in which the first decorative substrate 56 is visually checked for any missing electronic components. As a result, electronic components including small chip components are mounted on the first surface 268 side of the collective substrate 231.

As shown in FIG. 17(a), the left-side discarded board 263 and the right-side discarded board 266 have a first mounting reference hole 271 and a second mounting reference hole 272 formed through the thickness of the collective board 231. The first mounting reference hole 271 is used to align the collective board 231 in the component mounting process in which electronic components are mounted on the first board surface 268 side, and the second mounting reference hole 272 is used to align the collective board 231 in the component mounting process in which electronic components are mounted on the second board surface 269 side. After aligning the collective board 231, the automatic mounting device uses coordinate control to set the small chip components on the first decorative board 56 so that the electrodes of the small chip components are placed on the solder paste applied to the corresponding pads (or pads).

Known methods for dividing the collective substrate 231 include a method in which an operator manually divides the collective substrate 231, and a method in which the collective substrate 231 is mechanically cut using a press or the like. Of these, by adopting the manual division method, it becomes possible to flexibly handle multiple types of collective substrates while keeping equipment costs down.

Possible methods of dividing the collective substrate 231 include valley division, in which the collective substrate 231 is divided so that the first plate surface 268 on which the small chip components are concentrated has a valley shape (concave) using the dividing grooves 232-247 as base points, and mountain division, in which the collective substrate 231 is divided so that the first plate surface 268 has a mountain shape (convex). In the substrate dividing process, as shown in FIG. 17(b), the collective substrate 231 is divided by valley division, using the dividing grooves 232-247 as base points to make the first plate surface 268 have a valley shape (concave), and multiple first decorative substrates 56 (specifically, four) are taken out.

As already explained, in the first decorative board 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149) are concentrated on the first mounting surface 84 side. In the collective board 231, the small chip components are concentrated on the first board surface 268 side (first mounting surface 84 side) and are not mounted on the second board surface 269 side (second mounting surface 95 side). Also, as already explained, the connection points between the small chip components and the first decorative board 56 have lower mechanical strength than the connection points between other electronic components and the first decorative board 56. When the collective board 231 is split as shown in FIG. 17(c), the force that can act on the first board surface 268 side (first mounting surface 84 side) of the collective board 231 becomes a tensile stress, and the force that can act on the second board surface 269 side (second mounting surface 95 side) becomes a compressive stress. On the other hand, when the collective substrate 231 is split into valleys as shown in FIG. 17(b), the force that can act on the first plate surface 268 side (first mounting surface 84 side) of the collective substrate 231 is a compressive stress, and the force that can act on the second plate surface 269 side (second mounting surface 95 side) is a tensile stress.

The stress when dividing the collective substrate 231 acts more strongly on the plate surface that is mountain-shaped (convex) than on the plate surface that is valley-shaped (concave). By dividing the collective substrate 231 into valleys so that the first plate surface 268 side (first mounting surface 84 side) on which the small chip components are concentrated is valley-shaped (concave), it is possible to reduce the stress that may act on the connection points between the small chip components and the first decorative substrate 56 when dividing the collective substrate 231, and to reduce the stress that may act on the small chip components themselves. This reduces the possibility that the connection points between the small chip components and the first decorative substrate 56 will be damaged, and also reduces the possibility that the small chip components themselves will be damaged. In this way, the manufacturing efficiency of the first decorative substrate 56 can be improved by reducing the possibility of poor contact of the small chip components occurring in the substrate division process.

Among the small chip components, the multilayer ceramic capacitors used as the bypass capacitors 85 are vulnerable to tensile stress, and when tensile stress acts on the bypass capacitors 85, the bypass capacitors 85 themselves are prone to cracking. By dividing the collective substrate 231 into valleys so that the first plate surface 268 side (first mounting surface 84 side) on which the small chip components including the bypass capacitors 85 are concentrated has a valley shape (concave), the force that may act on the bypass capacitors 85 is treated as a compressive stress, and it is possible to prevent tensile stress from acting on the bypass capacitors 85. This reduces the possibility that the bypass capacitors 85 themselves will be damaged when the collective substrate 231 is divided.

As already explained, by dividing the assembly substrate 231 using the dividing grooves 232-247 as base points, it is possible to minimize the stress that may act on the connection points between the small chip components and the first decorative substrate 56, and also to minimize the stress that may act on the small chip components. On the other hand, if the dividing base points deviate from the dividing grooves 232-247, these stresses will increase. A dividing jig is used to prevent the dividing base points from deviating from the dividing grooves 232-247 and to improve the workability of the substrate dividing process.

Figure 18(a) is a perspective view of a dividing jig 281 used to divide the collective substrate 231 in this embodiment, Figure 18(b) is a front view of the dividing jig 281, and Figure 18(c) is an explanatory diagram for explaining how the collective substrate 231 is divided using the dividing jig 281. As shown in Figure 18(a), the dividing jig 281 is equipped with a thin metal blade 282 that abuts against the dividing grooves 232 to 247 and serves as a fulcrum when dividing the collective substrate 231, and a base 283 that supports the thin blade 282. The base 283 is equipped with a resin base portion 283a molded in a horizontally elongated rectangular parallelepiped shape, and a rectangular parallelepiped upright portion 283b that is integrally formed by standing up from the plate surface on one side of the base portion 283a.

The thin blade 282 has a plate-shaped blade portion 282a and a flange portion 282b. The thin blade 282 is fixed to the base portion 283 by screwing the flange portion 282b to the standing portion 283b. The blade portion 282a protrudes upward from the upper flat surface of the standing portion 283b and extends in the longitudinal direction of the standing portion 283b.

A protrusion 283c is integrally formed at approximately the center of the length of the standing portion 283b to assist in aligning the assembly substrate 231 with the blade portion 282a so that the blade portion 282a abuts against the dividing grooves 232 to 247. The protrusion 283c protrudes upward from the upper flat surface of the standing portion 283b with a protrusion dimension greater than that of the blade portion 282a. As shown in FIG. 17(a), recesses 284 and 285 are provided between the pair of first decorative substrates 56 on the right side of the left discarded substrate 263 and the left side of the central discarded substrate 261, allowing the protrusion 283c to be inserted. In addition, recesses 286 and 287 are provided between the pair of first decorative substrates 56 on the right side of the central discarded substrate 261 and the left side of the right discarded substrate 266, allowing the protrusion 283c to be inserted.

As shown in FIG. 18(c), the worker faces the first plate surface 268 (first mounting surface 84) of the collective board 231 downward, and fixes one of the central discarded board 261, the left discarded board 263, and the right discarded board 266 (central discarded board 261 in FIG. 18(c)) on the upright portion 283b. At this time, by inserting the protrusion 283c into the recesses 284-287 (FIG. 17(a)) provided on the discarded boards 261, 263, and 266, it is possible to easily create a state in which the dividing grooves 232-247, which are the base points of division, are in contact with the blade portion 282a. In this state, by applying a downward force to the second plate surface 269 side and pushing the part protruding to the right from the upright portion 283b downward, the collective board 231 can be divided into valleys with the dividing grooves 232-247 as the base points, with the first plate surface 268 becoming valley-shaped (concave).

For example, the worker first divides the collective board 231 (FIG. 17(a)) into a first unit including a pair of first decorative boards 56 on the left side, a lower left discard board 262, a left discard board 263, and an upper left discard board 264, and a second unit including a pair of first decorative boards 56 on the right side, a central discard board 261, a lower right discard board 265, a right discard board 266, and an upper right discard board 267. After that, in the first unit, the pair of first decorative boards 56 and the left discard board 263 can be divided to take out two first decorative boards 56. In addition, in the second unit, the pair of first decorative boards 56 and the central discard board 261 can be divided, and the pair of first decorative boards 56 and the right discard board 266 can be divided to take out two first decorative boards 56. The order in which the collective board 231 is divided to take out the four first decorative boards 56 is arbitrary.

By dividing the aggregate substrate 231 into valleys using the blade portion 282a as a fulcrum while the blade portion 282a is in contact with the dividing grooves 232 to 247 that serve as the base points for division, it is possible to prevent the base points for division from shifting from the dividing grooves 232 to 247. This makes it possible to minimize stress that may act on the connection points between the small chip components and the first decorative substrate 56 when dividing the aggregate substrate 231, and also to minimize stress that may act on the small chip components themselves.

By pushing the second mounting surface 95 downward to split the collective substrate 231 into valleys, it is easier for the worker to apply force to split the collective substrate 231 compared to a configuration in which the collective substrate 231 is split into valleys by pulling the second mounting surface 95 upward. In addition, in the central discarded substrate 261, the left discarded substrate 263, and the right discarded substrate 266, the recesses 284-287 (FIG. 17(a)) are provided between the pair of first decorative substrates 56, making it possible to fix the collective substrate 231 to the splitting jig 281 while preventing an increase in the stress acting on the electronic components mounted on the first decorative substrate 56.

As already explained with reference to FIG. 8(a), the first decorative board 56 is provided with the fixing through holes 56d-56g, and the small chip components are arranged avoiding the through hole peripheral areas 211a-211d. Therefore, as shown in FIG. 18(c), when the first board surface 268 (first mounting surface 84) is facing downward and any of the central waste board 261, the left side waste board 263, and the right side waste board 266 is fixed to the rising portion 283b, a downward force is applied to the second board surface 269 side to push the part protruding from the rising portion 283b downward to divide the collective board 231, the vicinity of the fixing through holes 56d-56g can be selected as the part to be pushed downward. This makes it possible to minimize the stress that may act on the small chip components mounted on the first board surface 268 side (first mounting surface 84 side).

As already explained, the dividing grooves 232-247 are formed only on the first plate surface 268 side of the collective substrate 231, and are not formed on the second plate surface 269 side. Therefore, the worker need only set the collective substrate 231 in the dividing jig 281 with the plate surface on which the dividing grooves 232-247 are formed (first plate surface 268) facing downward, reducing the possibility of the collective substrate 231 being accidentally divided into two.

As shown in FIG. 17(a), the 16 dividing grooves 232-247 in the collective substrate 231 extend in the first direction DR1. The extending directions of these dividing grooves 232-247 are parallel to each other. As already explained with reference to FIG. 8(a) to FIG. 8(c), the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149 (FIG. 11)) are mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip components is parallel to the 16 dividing grooves 232-247 in the collective substrate 231. Therefore, compared to a configuration in which the longitudinal direction of the small chip components is perpendicular to the extending direction of the dividing grooves 232-247, the stress that may act on the connection points between the small chip components and the first decorative substrate 56 when the collective substrate 231 is divided with the dividing grooves 232-247 as the base point is reduced, and the stress that may act on the small chip components themselves is reduced.

As shown in FIG. 17(a), slits 255-258 are provided in the assembly board 231 at locations corresponding to the area where the bypass capacitor 85 is mounted. As already explained, the slits 255-258 are elongated holes, and are formed wider than the dividing grooves 233, 234, 240, and 247. When the assembly board 231 is divided into valleys using the dividing grooves 232-247 as base points, the stress that may act around the slits 255-258 is smaller than the stress that may act around the dividing grooves 232-247. By providing the slits 255-258 at locations corresponding to the mounting area of the bypass capacitor 85, the stress that may act on the connection points between the bypass capacitor 85 and the first decorative board 56 when the assembly board 231 is divided is reduced, and the stress that may act on the bypass capacitor 85 itself is reduced.

8(a) and (b), the bypass capacitor 85 is disposed on the step-like recess 56a side of the LED driver 126. As already explained with reference to FIG. 17(a), the dividing grooves 233, 234, 240, and 247 are not provided on the step-like recess 56a side of the collective substrate 231. By disposing the bypass capacitor 85 on the opposite side of the dividing grooves 233, 234, 240, and 247 across the LED driver 126, it is possible to reduce stress that may act on the connection between the bypass capacitor 85 and the first decorative substrate 56 when the collective substrate 231 is divided using the dividing grooves 233, 234, 240, and 247 as base points, and to reduce stress that may act on the bypass capacitor 85 itself. As a result, when the collective substrate 231 is divided, the possibility of the connection between the bypass capacitor 85 and the first decorative substrate 56 being destroyed is reduced, and the possibility of the bypass capacitor 85 itself being destroyed is reduced.

8(b) and (c), the separation direction of the pads 171a, 171b corresponding to the electrodes 85a, 85b of the bypass capacitor 85 and the separation direction of the pads 176a, 176b corresponding to the electrodes 87a, 87b of the small chip resistor 87 are the first direction DR1. In the reflow process, by transporting the assembly board 231 in a direction perpendicular to the common separation direction (first direction DR1) or in a direction substantially perpendicular to the common separation direction (second direction DR2), the timing at which the heating of the solder paste applied on the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 is started can be synchronized, and the timing at which the heating of the solder paste applied on the pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the small chip resistor 87 is started can be synchronized. This makes it possible to prevent the rotation of multiple small chip components and the occurrence of chip standing. As shown in FIG. 17A, a recognition mark 288 is provided on the first plate surface 268 of the left-side throwaway board 263, allowing the transport direction of the collective board 231 in the reflow process to be confirmed. Although not shown, a recognition mark is also provided on the second plate surface 269 of the left-side throwaway board 263, allowing the transport direction of the collective board 231 in the reflow process to be confirmed. This reduces the possibility that the worker will make a mistake in the transport direction of the collective board 231.

As already explained with reference to FIG. 8(a), in a configuration in which the LED driver 126 is arranged in an area including an area less than 10 mm from the outer edge of the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149 (FIG. 11)) are arranged 10 mm or more away from the outer edge of the first decorative substrate 56. As already explained, the connection points between the small chip components among the various electronic components mounted on the first decorative substrate 56 and the first decorative substrate 56 have lower mechanical strength than the connection points between the other electronic components and the first decorative substrate 56. In addition, the area within 10 mm from the outer edge of the first decorative substrate 56 is an area that may be present in the vicinity of the dividing grooves 232-247 (FIG. 17) in the collective substrate 231 (FIG. 17), and is also an area where force may be applied to split the collective substrate 231 into valleys. By arranging the small chip components at least 10 mm away from the outer edge of the first decorative substrate 56, the maximum value of the stress that can act on the connection points between the small chip components and the first decorative substrate 56 when the collective substrate 231 is divided is reduced, and the maximum value of the stress that can act on the small chip components themselves is also reduced.

<Electrical configuration of the pachinko machine 10>
FIG. 19 is a block diagram showing the electrical configuration of the pachinko machine 10.

The main control device 60 comprises a main control board 61 which is responsible for the main control of the game, and a power failure monitoring board 67 which monitors the power supply. The main control board 61 is equipped with an MPU 62. The MPU 62 contains a main CPU 63, which is an arithmetic processing device including a control unit and an arithmetic unit, as well as a main ROM 64 and a main RAM 65. In addition to the above elements, the MPU 62 also contains an interrupt circuit, a timer circuit, a data input/output circuit, various counter circuits as random number generators, and the like.

The main ROM 64 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain memory, such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

The main RAM 65 is a memory (i.e., a volatile memory means) that requires an external power supply to retain memory, such as SRAM and DRAM, and is used for both reading and writing. The main RAM 65 allows random access, and when compared for the same data capacity, requires less time to read data than the main ROM 64. The main RAM 65 temporarily stores various data for the execution of the control programs stored in the main ROM 64.

The main CPU 63 executes a process for managing the game history. The main CPU 63 grasps the ball entry history of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, and grasps the ball entry frequency of the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 according to the grasped ball entry history. The main CPU 63 also grasps the occurrence frequency of the opening/closing execution mode and the high frequency support mode, which will be described later.

The MPU 62 has an input port and an output port. The input side of the MPU 62 is connected to a power outage monitoring board 67 and a payout control device 77 provided in the main control device 60. The power outage monitoring board 67 is connected to a power supply and launch control device 78 that has the function of supplying operating power, and the MPU 62 is supplied with operating power via the power outage monitoring board 67.

The input side of the MPU 62 is connected to various sensors such as the ball entry detection sensors 42a to 49a. As already explained, the ball entry detection sensors 42a to 49a include the first winning hole detection sensor 42a, the second winning hole detection sensor 43a, the third winning hole detection sensor 44a, the special electric detection sensor 45a, the first operating hole detection sensor 46a, the second operating hole detection sensor 47a, the out hole detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a to 49a, the main CPU 63 determines whether a ball has entered each entry section. In addition, the main CPU 63 executes various lotteries based on the entry into the first operating hole 33, and executes various lotteries based on the entry into the second operating hole 34.

The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, which are provided on the main control board 61. The setting key insertion section 68a is provided with a sensor (not shown), which detects whether the setting key insertion section 68a is located at the ON operation position or the OFF operation position. The main CPU 63 then identifies whether the setting key insertion section 68a is located at the ON operation position or the OFF operation position based on the detection result from the sensor. The update button 68b is provided with a sensor (not shown), which detects whether the update button 68b is pressed. The main CPU 63 then identifies whether the update button 68b is pressed based on the detection result from the sensor. The reset button 68c is provided with a sensor (not shown), which detects whether the reset button 68c is pressed. The main CPU 63 then identifies whether the reset button 68c is pressed based on the detection result from the sensor.

The output side of the MPU 62 is connected to a power outage monitoring board 67, a payout control device 77, and an audio/light emitting control device 81. A prize ball command is output to the payout control device 77, for example, based on the fact that a game ball has entered a prize ball entry section among the above-mentioned entry sections, where the occurrence of the ball entry corresponds to the payout of the game ball. Various commands such as a variation command, a type command, and an opening command are output to the audio/light emitting control device 81.

The output side of the MPU 62 is connected to the special electric drive unit 32b that opens and closes the opening and closing door 32a of the special electric winning device 32, the normal electric drive unit 34b that opens and closes the normal electric device 34a of the second operating port 34, the special chart unit 37, and the normal chart unit 38. Incidentally, the special chart unit 37 is provided with a special chart display unit 37a and a special chart reserved display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal chart unit 38 is provided with a normal chart display unit 38a and a normal chart reserved display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 controls the drive of the various drive units and various display units through the driver circuits.

That is, in the open/close execution mode, the main CPU 63 controls the drive of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Also, when the open state of the regular power role device 34a is selected, the main CPU 63 controls the drive of the regular power drive unit 34b so that the regular power role device 34a is opened and closed. Also, during each game round, the main CPU 63 controls the display of the special chart display unit 37a. Also, when the lottery result of whether or not the regular power role device 34a is to be opened is to be clearly displayed, the main CPU 63 controls the display of the regular chart display unit 38a. In addition, when a winning entry occurs in the first operating port 33 or the second operating port 34, or when a variable display starts in the special chart display unit 37a, the main CPU 63 executes display control of the special chart pending display unit 37b, and when a winning entry occurs in the through gate 35, or when a variable display starts in the regular chart display unit 38a, the main CPU 63 executes display control of the regular chart pending display unit 38b.

The first to third notification display devices 69a to 69c are connected to the output side of the MPU 62. The first to third notification display devices 69a to 69c display the results of game history management. When the settings of the pachinko machine 10 are changed, the third notification display device 69c displays the current settings. The display of the first to third notification display devices 69a to 69c is controlled by the main CPU 63.

The power failure monitoring board 67 relays between the main control board 61 and the power supply and launch control device 78, and monitors the stable DC voltage of 24 volts, which is the maximum voltage output from the power supply and launch control device 78. The payout control device 77 controls the payout of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

The power supply and launch control device 78 is connected to a commercial power supply (external power supply) in, for example, an amusement hall. Based on the external power supplied from the commercial power supply, the power supply and launch control device 78 generates the necessary operating power for the main control board 61, the payout control device 77, etc., and supplies the generated operating power. Incidentally, the power supply and launch control device 78 is provided with a power supply unit for power outage such as a backup capacitor, and even when the power supply to the pachinko machine 10 is in an OFF state, the power supply unit for power outage supplies memory retention power to the main RAM 65 of the main control device 60 and the payout control device 77. The power supply and launch control device 78 is also responsible for the launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when a predetermined launch condition is met. As already explained, the payout mechanism unit 73 is provided with a power switch, and when the power switch is turned ON, the supply of operating power to the pachinko machine 10 is started, and when the power switch is turned OFF, the supply of operating power to the pachinko machine 10 is stopped.

The audio and light emission control device 81 drives and controls the speaker unit 53 provided in the front door frame 14 based on various commands received from the main control device 60. As already explained, the audio and light emission control device 81 also controls the emission of the LED chips 127-142 mounted on the first decorative board 56 and the LED chips mounted on the second decorative board 57. Furthermore, the audio and light emission control device 81 controls the display control device 82. The display control device 82 executes display control of the pattern display device 41 based on commands received from the audio and light emission control device 81.

<Electrical configuration for performing various lotteries by the main CPU 63>
Next, the electrical configuration for performing various lotteries by the main CPU 63 will be described with reference to FIG.

During play, the main CPU 63 uses various counter information to perform a lottery for determining whether a jackpot occurs, settings for the display of the special chart display section 37a, settings for the display of the pattern display device 41, settings for the display of the normal chart display section 38a, etc. Specifically, as shown in FIG. 20, a winning random number counter C1 used for the lottery for determining whether a jackpot occurs, a jackpot type counter C2 used for determining the type of jackpot, a reach random number counter C3 used for the lottery for determining whether a reach occurs when the pattern display device 41 misses and fluctuates, a random number initial value counter CINI used for setting the initial value of the winning random number counter C1, and a fluctuating type counter CS that determines the display duration time in the special chart display section 37a and the pattern display device 41. In addition, a normal power role release counter C4 used for the lottery for determining whether the normal power role 34a of the second operating port 34 is in a normal power open state is used. The counters C1 to C3, CINI, CS, and C4 are located in the various counter areas 65b of the main RAM 65.

Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after it reaches its maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored in the reserved storage area 65a provided as acquired information storage means in the main RAM 65 when a winning occurs in the first actuation port 33 or the second actuation port 34.

The reserved storage area 65a comprises a reserved area RE and an execution area AE. The reserved area RE comprises a first reserved area RE1, a second reserved area RE2, a third reserved area RE3 and a fourth reserved area RE4, and a combination of the numerical information of the winning random number counter C1, the big win type counter C2 and the reach random number counter C3 is stored as reserved information in one of the reserved areas RE1 to RE4 according to the winning history of the first actuation port 33 or the second actuation port 34.

In this case, when multiple winning entries into the first actuation port 33 or the second actuation port 34 occur consecutively, the numerical information is stored in the first holding area RE1 to the fourth holding area RE4 in chronological order from the first holding area RE1 to the second holding area RE2 to the third holding area RE3 to the fourth holding area RE4. By providing four holding areas RE1 to RE4 in this way, up to four winning entries of game balls into the first actuation port 33 or the second actuation port 34 can be reserved and stored.

The number of items that can be stored on hold is not limited to four, but is arbitrary, and may be any other multiple, such as two, three, or five or more, or may be singular.

The execution area AE is an area for moving the various numerical information stored in the first reserve area RE1 of the reserve area RE when the variable display of the special chart display section 37a begins, and when one game round begins, a win/loss determination is made based on the various numerical information stored in the execution area AE.

Each of the above counters will be explained in detail below.

First, the normal power feature opening counter C4 will be described. The normal power feature opening counter C4 is configured to increment by one within the range of 0 to 250, for example, and return to "0" after reaching the maximum value. The normal power feature opening counter C4 is updated periodically, and is stored in the normal power reserve area 65c of the main RAM 65 when the game ball enters the through gate 35. Then, at a specified timing, a lottery is held to determine whether or not to control the normal power feature 34a to an open state based on the value of the stored normal power feature opening counter C4.

In this pachinko machine 10, multiple types of support modes are set so that the manner of support provided by the normal power device 34a differs from one another. In detail, the support modes are set to a high-frequency support mode and a low-frequency support mode so that the frequency with which the normal power device 34a of the second operating port 34 opens per unit time is relatively high and low when compared with a situation in which game balls are continuously released in the same manner into the game area PA.

In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power role opening counter C4 is the same (for example, both are 4/5), but in the high-frequency support mode, the number of times that the normal power role 34a will be in the open state when the normal power opening state is won is set to be more than in the low-frequency support mode, and the opening time for one time is set to be longer. In this case, when the normal power opening state is won in the high-frequency support mode and the open state of the normal power role 34a occurs multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for one time. Furthermore, in the high-frequency support mode, the minimum time to be secured between one normal power opening lottery and the next normal power opening lottery (i.e., the duration of one display on the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

As described above, in the high-frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of a winning entry into the first actuation port 33 is higher than in the second actuation port 34, but in the high-frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the first actuation port 33. When a winning entry into the second actuation port 34 occurs, a predetermined number of game balls are paid out, so in the high-frequency support mode, the player can play without losing too many balls.

The configuration for increasing the frequency of the high-frequency support mode being in the normal power release state per unit time compared to the low-frequency support mode is not limited to the above, and may be, for example, a configuration for increasing the probability of winning the normal power release state in the normal power release lottery. In addition, in a configuration in which multiple types of reserved time (for example, the time of variable display executed in the normal power display unit 38a based on winning the through gate 35) are prepared for the time reserved between one normal power release lottery and the next normal power release lottery, the high-frequency support mode may be set so that a shorter reserved time is more likely to be selected or the average reserved time is shorter than in the low-frequency support mode. Furthermore, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one or any combination of conditions from increasing the number of openings, lengthening the opening time, shortening the reserved time reserved between one normal power release lottery and the next normal power release lottery, shortening the average time of the reserved time, and increasing the winning probability.

As already explained, the pachinko machine 10 has the setting states of "Setting 1" to "Setting 6", but the opening frequency and opening mode of the normal power device 34a in the low-frequency support mode are the same regardless of the setting value, and the opening frequency and opening mode of the normal power device 34a in the high-frequency support mode are also the same regardless of the setting value. However, this is not limited to this, and at least one of the opening frequency and opening mode of the normal power device 34a for at least one of the low-frequency support mode and the high-frequency support mode may be configured to vary depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the opening frequency of the normal power device 34a in the low-frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is in a one-time opening state in the low-frequency support mode. In addition, the higher the set value, the higher the frequency of opening the normal power device 34a in the high-frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is opened once in the high-frequency support mode.

Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to increment by one within the range of, for example, 0 to 7999, and return to "0" after reaching a maximum value. In particular, when the winning random number counter C1 goes around once, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 7999). The winning random number counter C1 is updated periodically, and is stored in the reserved storage area 65a of the main RAM 65 when a game ball enters the first actuation port 33 or the second actuation port 34.

The random number value that will result in a jackpot win is stored as a win/lose table in the main ROM 64. As shown in FIG. 19, the main ROM 64 is provided with a win/lose table storage area 64a. In the win/lose table storage area 64a, a low probability win/lose table for the low probability mode and a high probability win/lose table for the high probability mode are stored as win/lose tables.

The low-probability win/loss tables are provided in one-to-one correspondence with the setting states of "Setting 1" to "Setting 6." In other words, there is a low-probability win/loss table for Setting 1 that is referenced when the setting state of the pachinko machine 10 is "Setting 1," a low-probability win/loss table for Setting 2 that is referenced when the setting state of the pachinko machine 10 is "Setting 2," a low-probability win/loss table for Setting 3 that is referenced when the setting state of the pachinko machine 10 is "Setting 3," a low-probability win/loss table for Setting 4 that is referenced when the setting state of the pachinko machine 10 is "Setting 4," a low-probability win/loss table for Setting 5 that is referenced when the setting state of the pachinko machine 10 is "Setting 5," and a low-probability win/loss table for Setting 6 that is referenced when the setting state of the pachinko machine 10 is "Setting 6."

These low probability tables are set so that the higher the setting value, the higher the probability of winning the jackpot. Specifically, when the low probability table for setting 1 is referenced, the jackpot result occurs at 1/320, when the low probability table for setting 2 is referenced, the jackpot result occurs at about 1/308, when the low probability table for setting 3 is referenced, the jackpot result occurs at about 1/278, when the low probability table for setting 4 is referenced, the jackpot result occurs at about 1/286, when the low probability table for setting 5 is referenced, the jackpot result occurs at about 1/276, and when the low probability table for setting 6 is referenced, the jackpot result occurs at about 1/267. As a result, when the setting state of the pachinko machine 10 is a high setting value, the jackpot result is more likely to occur in the low probability mode, which is advantageous for the player.

On the other hand, only one type of high probability winning/losing table is provided so that it is common to any of the settings of "Setting 1" to "Setting 6". The high probability winning/losing table is set so that the probability of winning the jackpot result is higher than that of the low probability winning/losing table regardless of the setting of any of "Setting 1" to "Setting 6". Specifically, when the high probability winning/losing table is referenced, the jackpot result occurs at about 1/30. This makes it possible to make the high probability mode more advantageous than the low probability mode regardless of the setting of the pachinko machine 10. In addition, even in the lowest setting state "Setting 1", the high probability mode makes it possible to increase the probability of winning the jackpot result compared to the low probability mode of the highest setting state "Setting 6". In addition, it is possible to prevent the high probability mode from causing an advantage or disadvantage depending on the setting state of the pachinko machine 10, and it is also possible to reduce the storage capacity for storing the high probability winning/losing table in advance in the main ROM 64.

The jackpot type counter C2 is configured to be incremented by one within the range of 0 to 29, and to return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically, and is stored in the reserved storage area 65a when a game ball enters the first actuation port 33 or the second actuation port 34.

In this pachinko machine 10, multiple jackpot results are set. These multiple jackpot results are set by providing differences in three conditions: (1) the manner of opening and closing control of the special electric prize winning device 32 in the opening and closing execution mode, (2) the lottery mode in the winning/losing lottery means after the opening and closing execution mode ends, and (3) the support mode in the regular electric device 34a of the second operating port 34 after the opening and closing execution mode ends.

As the manner of opening and closing control of the special electric winning device 32 in the opening and closing execution mode, a high frequency winning mode and a low frequency winning mode are set so that the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is relatively high and low. Specifically, in either the high frequency winning mode or the low frequency winning mode, a predetermined number of rounds are played up to the upper limit.

A round play is a play that continues until one of the following conditions is met: a predetermined upper limit duration has elapsed, or a predetermined upper limit number of game balls have entered the special electric winning device 32. In addition, the number of round plays in the open/close execution mode triggered by a jackpot result is the same fixed number of rounds regardless of the type of jackpot result that triggered the transition. Specifically, the upper limit number of round plays is set to 15 rounds regardless of the jackpot result.

In addition, in this pachinko machine 10, the special electric winning device 32 is set to have multiple opening modes with different opening durations from when the special electric winning device 32 is opened to when it is closed. In detail, a long-time mode in which the opening duration is set to 29 seconds, which is a long time, and a short-time mode in which the opening duration is set to 0.06 seconds, which is a short time shorter than the long time, are set.

In this pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launch mechanism 27 is driven and controlled so that one game ball is launched toward the game area PA every 0.6 seconds. In addition, the upper limit number of balls for the end condition of the round game is set to nine. In this case, in the long-time mode among the above-mentioned opening modes, the opening duration is set to a time longer than the product of the game ball launch cycle and one round game. On the other hand, in the short-time mode, the opening duration is set to a time shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when one opening is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of balls in one round game, and when one opening is performed in the short-time mode, it is expected that no prize will be won in the special electric winning device 32, or that if a prize is won, it will be about one ball.

In the high frequency winning mode, the special electric winning device 32 is opened once in each round of play in a long time mode. On the other hand, in the low frequency winning mode, the special electric winning device 32 is opened once in each round of play in a short time mode.

The number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of times per round of play in the high frequency winning mode and low frequency winning mode are not limited to the above values and are arbitrary, so long as the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high frequency winning mode than in the low frequency winning mode.

As shown in FIG. 19, the main ROM 64 has an allocation table storage area 64b. The allocation table storage area 64b stores an allocation table in which the allocation destination of the jackpot result for the jackpot type counter C2 is set. In the allocation table, a low probability jackpot result, a low prize high probability jackpot result, and a most favorable jackpot result are set as the allocation destination of the jackpot result in the event of a jackpot result.

A low probability jackpot result is one in which the open/close execution mode becomes the high probability winning mode, and after the open/close execution mode ends, the win/lose selection mode becomes the low probability mode, and the support mode becomes the high frequency support mode. However, this high frequency support mode will transition to the low frequency support mode if the number of plays reaches the end reference number (specifically, 100 plays) after the transition.

A low-winning, high-probability jackpot result is one in which the open/close execution mode becomes the low-frequency winning mode, and after the open/close execution mode ends, the win/lose lottery mode becomes the high-probability mode, and the support mode becomes the high-frequency support mode. These high-probability and high-frequency support modes continue until the lottery result in a win/lose lottery win and the jackpot state is entered.

The most favorable jackpot result is one in which the open/close execution mode becomes the high frequency winning mode, and after the open/close execution mode ends, the win/lose lottery mode becomes the high probability mode, and the support mode becomes the high frequency support mode. These high probability and high frequency support modes continue until the lottery result in a win in the jackpot state, which transitions to the jackpot state.

In relation to the above game states, the normal game state refers to a state in which the win/lose selection mode is a low probability mode and the support mode is a low frequency support mode, rather than the open/close execution mode. Also, a configuration may be adopted in which a low prize-winning, high probability jackpot result is not set as a game result. Also, in the open/close execution mode in a low prize-winning, high probability jackpot result, the number of rounds of play may be fewer than in the case of a low probability jackpot result and a most favorable jackpot result.

In the distribution table, of the jackpot type counter C2 values of "0 to 29," "0 to 9" correspond to a low probability jackpot result, "10 to 14" correspond to a low probability jackpot result with a high probability of winning, and "15 to 29" correspond to the most favorable jackpot result.

Only one type of distribution table is provided so that it is common to all settings from "Setting 1" to "Setting 6." This makes it possible to prevent any advantage or disadvantage in the distribution pattern of the jackpot result from being caused by the setting state of the pachinko machine 10, and also makes it possible to reduce the storage capacity required to previously store the distribution table in the main ROM 64.

The allocation of the jackpot result may be different depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result, or the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result or the low prize-winning high probability jackpot result. In this case, the higher the setting value, the higher the probability of entering the high probability mode after the jackpot result. Also, the higher the setting value, the lower the probability of being allocated to the low prize-winning high probability jackpot result, or the higher the setting value, the higher the probability of being allocated to the low prize-winning high probability jackpot result. In this case, the higher the setting value, the higher the probability of the opening and closing execution mode of the high frequency winning mode occurring.

Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by one within a range of, for example, 0 to 238, and to return to "0" after reaching a maximum value. In this pachinko machine 10, an expectation effect is set as a type of display effect in the pattern display device 41. The expectation effect refers to a display state that makes the player think that the change display state is likely to result in the award corresponding result from the start of the change display of the patterns in the pattern display device 41 and before the stop result is derived and displayed in a gaming machine equipped with a pattern display device 41 capable of performing a change display of the patterns, in which the final stop result in a game round that results in a predetermined jackpot result is a grant corresponding result. Specifically, the grant corresponding result is displayed as a combination of patterns with the same number on one of the pay lines.

There are two types of expected effects: a reach display and a warning display that is set to anticipate the occurrence of a reach display or a corresponding result before the reach display occurs.

The reach display includes a display state in which the reach pattern combination is displayed by stopping the display of the patterns for some of the multiple pattern rows displayed on the display surface 41a of the pattern display device 41, and in this state, the remaining pattern rows display a changing pattern. In addition, it includes a state in which the reach pattern combination is displayed as described above, the remaining pattern rows display a changing pattern, and a reach performance is performed by displaying a predetermined character or the like as a video on the background screen, and a reach performance is performed by displaying a reduced or hidden display of the reach pattern combination and displaying a predetermined character or the like as a video on almost the entire display surface 41a.

Pre-notification displays include a mode in which characters are displayed separately from the patterns on the pattern rows in a situation in which patterns are displayed in a variable manner in all pattern rows after the display surface 41a of the pattern display device 41 starts displaying the variable patterns, or in a situation in which patterns are displayed in a variable manner in some pattern rows. Pre-notification displays also include a mode in which the background screen is displayed in a predetermined manner different from the previous manner, and a mode in which the patterns on the pattern rows are displayed in a predetermined manner different from the previous manner. Such pre-notification displays can occur in both game rounds when a reach display is made and when a reach display is not made, but are set to occur with a higher probability when a reach display is made than when a reach display is not made.

The reach display is executed regardless of the value of the reach random number counter C3 in a game round in which the same symbol combination is finally displayed. Also, in a game round corresponding to a jackpot result in which the same symbol combination is not displayed, the reach display is not executed regardless of the value of the reach random number counter C3. Also, in a game round corresponding to a miss result, the reach display is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

On the other hand, the decision as to whether or not to display a preview is not made by the main control device 60, but by the audio and light control device 81. In this case, the audio and light control device 81 executes a lottery process for the preview display so that a game round corresponding to any jackpot result satisfies at least one of the conditions that a preview display is more likely to occur and that a preview display with a low occurrence rate is more likely to occur in a game round corresponding to a miss result. Incidentally, this lottery result is reflected when the performance for the game round is executed by the pattern display device 41.

Here, the probability of a reach display occurring in a game that results in a losing result is the same regardless of the setting state of "Setting 1" to "Setting 6." This makes it possible to ensure that the setting state of the pachinko machine 10 does not result in an advantage or disadvantage in terms of the probability of a reach display occurring in a game that results in a losing result. However, this is not limited to this, and a configuration may be adopted in which the higher the setting value, the higher the probability of a reach display occurring in a game that results in a losing result.

Next, the change type counter CS will be explained. The change type counter CS is configured to increment by one within the range of, for example, 0 to 198, and return to "0" after reaching the maximum value. The change type counter CS is used by the main CPU 63 to determine the display duration in the special chart display unit 37a and the display duration of the pattern in the pattern display device 41. The change type counter CS is updated once each time the timer interrupt process described below is executed, and is repeatedly updated within the remaining time until the next timer interrupt process is executed. The buffer value of the change type counter CS is obtained when determining the change pattern at the start of the change display in the special chart display unit 37a and at the start of the pattern change by the pattern display device 41.

<Regarding the processing configuration of the main CPU 63>
Next, we will explain each process executed to progress the game by the master CPU 63. The processes of the master CPU 63 are roughly divided into main processes that are started when the power is turned on, and timer interrupt processes that are started periodically (every 4 millisecond period in this embodiment).

<Main processing>
First, the main processing will be described with reference to the flowchart of FIG.

In the main process, first, a power-on wait process is executed (step S101). In this power-on wait process, for example, the main process waits until a predetermined wait time (specifically, one second) has elapsed since the main process was started, without proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial settings of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102).

Then, it is determined whether the setting key insertion section 68a is turned on (step S103). If the setting key insertion section 68a is not turned on (step S103: NO), it is determined whether the reset button 68c is pressed (step S104). If the reset button 68c is pressed (step S104: YES), each area of the main RAM 65 is cleared to "0" except for the area in which the setting value information indicating the setting state of the pachinko machine 10 is set in the main RAM 65, and the area cleared to "0" is initialized (step S105). In other words, when the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed without turning on the setting key insertion section 68a, the clearing process of the main RAM 65 is executed while the setting value information is maintained in the state before the supply of operating power to the pachinko machine 10 was stopped, and the initial setting is executed for the memory area in which the clearing process was executed. This makes it possible to initialize other areas of the main RAM 65 without changing the setting value. In step S105, various registers in the main CPU 63 are also cleared to "0" and then initialized.

If the reset button 68c is not pressed (step S104: NO), it is determined whether the power outage flag is set to "1" (step S106). The power outage flag is provided in the main RAM 65, and if the supply of operating power to the main CPU 63 is stopped and a predetermined power outage process is normally executed, the power outage flag is set to "1". If the power outage flag is set to "1", it is determined whether the checksum calculation result matches the checksum saved when the power was cut off, that is, the validity of the stored data (step S107). If the process of step S105 is executed, or if a positive determination is made in step S107, it is determined whether the setting value of the pachinko machine 10 is normal by checking the main RAM 65 (step S108). Specifically, if the setting value is any of "Setting 1" to "Setting 6", it is determined to be normal, and if it is "0" or 7 or more, it is determined to be abnormal.

If a negative judgment is made in any of steps S106 to S108, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S109), and then an infinite loop is entered. The operation prohibition process is released by executing an all-clear process (step S115) described below.

If the determination is positive in all of steps S106 to S108, the power-on setting process is executed (step S110). In the power-on setting process, a predetermined area of the main RAM 65, such as the power outage flag, is set to an initial value, and a command corresponding to the current game state is sent to the sound and light emission control device 81.

The main CPU 63 is configured to periodically execute timer interrupt processing, but timer interrupt processing is prohibited from occurring when main processing is started. This state in which timer interrupt processing is prohibited is released when step S110 processing is completed and before step S111 processing is executed, and timer interrupt processing is permitted to be executed. As a result, when the supply of operating power to the main CPU 63 is started, the power-on setting processing of step S110 is completed, and timer interrupt processing is not executed until the stage before step S111 processing is started. Therefore, processing to progress the game in the main CPU 63 is not started until this situation is reached.

Then, proceed to the remaining processing of steps S111 to S114. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there will be a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time will vary depending on the processing completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining processing of steps S111 to S114. In this respect, the remaining processing of steps S111 to S114 can be said to be non-periodic processing that is executed non-periodically.

In the remaining process, first, in step S111, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing. In the following step S112, random number initial value update processing is executed to update the random number initial value counter CINI, and in step S113, fluctuation counter update processing is executed to update the fluctuation type counter CS. In these update processing, the current numerical information is read from the corresponding counter in the main RAM 65, and the read numerical information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value exceeds the maximum value, each is cleared to "0". After that, in step S114, interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing is prohibited to a state in which it is permitted. If the processing of step S114 is executed, the process returns to step S111, and the processing of steps S111 to S114 is repeated.

On the other hand, if the setting key insertion section 68a is turned ON (step S103: YES), an all-clear process is executed (step S115). In the all-clear process, all areas of the main RAM 65, including the areas in which setting value information indicating the setting state of the pachinko machine 10 is set in the main RAM 65, are cleared to "0", and the areas cleared to "0" are initialized. In other words, if an operation to change the setting state of the pachinko machine 10 is performed, all areas of the main RAM 65 are cleared to "0" even if the reset button 68c is not pressed, and the memory areas in which the clear process was executed are initialized. In step S115, various registers of the main CPU 63 are also cleared to "0", and then initialized. However, without being limited to this, the configuration may be such that, even if an operation to change the setting state of the pachinko machine 10 is being performed, if the reset button 68c is not pressed, the all-clear process of the main RAM 65 is not executed, and the all-clear process is executed when an operation to change the setting state of the pachinko machine 10 is being performed and the reset button 68c is pressed.

After that, in step S116, the setting value update process is executed, and then the process proceeds to step S110. In the setting value update process (step S116), first, "1" is set to the setting value counter provided in the main RAM 65. The setting value counter is a counter for the main CPU 63 to specify which setting value the setting state of the pachinko machine 10 is. By setting "1" to the setting value counter, when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the previous setting value. Then, the display of the third notification display device 69c is controlled so that the number "1" corresponding to "Setting 1" is displayed. When changing the setting value, the manager of the game hall can grasp the current setting state of the pachinko machine 10 by checking the third notification display device 69c. Then, the update execution process is executed.

In the update execution process, on the condition that the setting key insertion section 68a is not turned OFF, it is determined whether the update button 68b has been pressed once, and if the update button 68b has been pressed once, the value of the setting value counter in the main RAM 65 is incremented by 1. If the value of the setting value counter after the increment exceeds "6", the setting value counter is set to "1". As a result, the setting value is updated to the next higher setting value each time the update button 68b is pressed once, and if the update button 68b is pressed once in the "setting 6" state, the setting value returns to "setting 1". In the update execution process, when the value of the setting value counter is updated, the display of the third notification display device 69c is controlled so that a number corresponding to the value of the setting value counter in the main RAM 65 is displayed. The manager of the game hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b by checking the third notification display device 69c. In the setting value update process (step S116), the update execution process is repeatedly executed until the setting key insertion section 68a is turned OFF. When the setting key insertion section 68a is turned OFF, the display of the setting value on the third notification display device 69c is terminated, and the setting value update process is terminated.

<Timer interrupt processing>
Next, the timer interrupt process will be described with reference to the flowchart of Fig. 22. The timer interrupt process is executed periodically (for example, every 4 milliseconds).

In the timer interrupt process, first, the power outage information storage process is executed (step S201). In the power outage information storage process, it is monitored whether a power outage signal corresponding to the occurrence of a power cut is received from the power outage monitoring board 67, and if the occurrence of a power outage is identified, the power outage process is executed and then an infinite loop is entered. In the power outage process, the power outage flag in the main RAM 65 is set to "1", and the checksum is calculated and the calculated checksum is saved.

Then, a random number update process for lottery is executed (step S202). In the random number update process for lottery, the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the normal power feature opening counter C4 are updated. Specifically, the current numerical information is read out sequentially from the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the normal power feature opening counter C4, and the read numerical information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value exceeds the maximum value, each is cleared to "0". After that, in step S203, a random number initial value update process is executed as in step S112, and in step S204, a variable counter update process is executed as in step S113.

Then, a fraud detection process is executed to monitor whether or not a specific event set as a target for fraudulent activity has occurred (step S205). In this fraud detection process, the occurrence of multiple types of events is monitored, and if a specific event has occurred, a game stop flag provided in the main RAM 65 is set to "1". In the following step S206, it is determined whether or not the game progress has been stopped by determining whether or not the game stop flag has been set to "1". If a negative determination is made in step S206, the process from step S207 onwards is executed.

In step S207, port output processing is executed. In the port output processing, when output information has been set in the previous timer interrupt processing, processing is executed to output corresponding to that output information to the various drive units 32b, 34b. For example, when information is set to switch the special power winning device 32 to an open state, the output of a drive signal to the special power drive unit 32b is started, and when information is set to switch to a closed state, the output of the drive signal is stopped. Also, when information is set to switch the normal power device 34a of the second operating port 34 to an open state, the output of a drive signal to the normal power drive unit 34b is started, and when information is set to switch to a closed state, the output of the drive signal is stopped.

Then, a read process is executed (step S208). In the read process, signals other than the power outage signal and the winning signal are read, and the read information is stored for use in future processes.

Then, the ball entry detection process is executed (step S209). In the ball entry detection process, the signals received from each ball entry detection sensor 42a to 49a are read, and based on the read results, it is determined whether or not a ball has entered the out gate 24a, the general winning gate 31, the special electric winning device 32, the first operating gate 33, the second operating gate 34, and the through gate 35.

Then, a timer update process is executed to collectively update the numerical information of multiple types of timer counters provided in the main RAM 65 (step S210). In this case, the timer counters whose stored numerical information is updated by subtraction are handled in a consolidated manner, but it is also possible to configure the system to collectively update both subtractive timer counters and additive timer counters.

Then, a launch control process is executed to control the launch of the gaming balls (step S211). When the launch operation to the launch operation device 28 is continued, one gaming ball is launched every 0.6 seconds, which is the predetermined launch cycle. In the following step S212, as an input status monitoring process, based on the information read in the reading process of step S208, a disconnection check is performed for each ball entry detection sensor 42a to 49a, and the opening of the gaming machine main body 12 and the front door frame 14 is confirmed.

Then, a special chart special electricity control process is executed to control the execution of the game round and the open/close execution mode (step S213). The special chart special electricity control process will be described in detail later.

Then, execute the normal map normal power control process (step S214). In the normal map normal power control process, if a winning entry has occurred in the through gate 35, execute a process to obtain the reserved information on the normal map side, and if reserved information on the normal map side is stored, execute an opening judgment for the reserved information, and execute a process to perform a normal map performance triggered by the opening judgment. Also, execute a process to open and close the normal power role 34a of the second operating port 34 based on the result of the opening judgment. In this case, if the support mode is the low frequency support mode, execute the corresponding process, and if the support mode is the high frequency support mode, execute the corresponding process. Also, if the opening and closing execution mode is selected, the support mode will be the low frequency support mode even if the previous support mode was the high frequency support mode.

In the next step S215, based on the processing results of the immediately preceding steps S213 and S214, output information is set to reflect the increase or decrease in the number of reserved information related to the special drawing display unit 37a in the special drawing reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved information related to the ordinary drawing display unit 38a in the ordinary drawing reserved display unit 38b. Also, in step S215, based on the processing results of the immediately preceding steps S213 and S214, output information is set to update the display contents of the special drawing display unit 37a, and output information is set to update the display contents of the ordinary drawing display unit 38a.

Then, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout status receiving process is executed to perform processing corresponding to the confirmation result (step S216). A payout output process is also executed to set the prize ball command as the output target (step S217). An external information setting process is also executed to control the start and end of the output of an external signal according to the processing results of the various processes executed in this timer interrupt process (step S218). Then, a management process is executed to display information corresponding to the ball entry results in the game area PA on the first to third notification display devices 69a to 69c (step S219), and this timer interrupt process is terminated.

<Special chart special signal control processing>
Next, the special picture special electricity control process in step S213 will be described with reference to the flowchart of FIG.

First, the process for acquiring reserved information is executed (step S301). In the process for acquiring reserved information, it is determined whether or not a winning has occurred in the first actuation port 33 or the second actuation port 34, and if a winning has occurred, it is determined whether or not the number of reserved balls in the reserved storage area 65a is less than the upper limit ("4" in this embodiment). If the number of reserved balls is less than the upper limit, the number of reserved balls is incremented by 1, and the numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 updated in the previous step S202 is stored in the first reserved area among the empty reserved areas RE1 to RE4 in the reserved area RE. If winning balls have been simultaneously won in the first actuation port 33 and the second actuation port 34, the process for acquiring the reserved information is executed multiple times within the range in which the process for acquiring reserved information is executed once. In addition, when new reserved information is acquired, a corresponding acquisition command is sent to the sound and light emission control device 81. When the audio and light emission control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to display content that corresponds to the increase in pending information items.

Then, the information of the special drawing special power counter provided in the main RAM 65 is read (step S302), and the special drawing special power address table provided in the main ROM 64 is read (step S303). Then, a start address corresponding to the information of the special drawing special power counter is obtained from the special drawing special power address table (step S304), and a jump is made to the process indicated by the obtained start address among the processes of steps S306 to S312 (step S305). The special drawing special power counter is a counter that allows the main CPU 63 to grasp which of the various processes of steps S306 to S312 should be executed, and the special drawing special power address table is set with the start address of the program for executing the processes of steps S306 to S312 corresponding to the numerical information of the special drawing special power counter.

In step S306, the special chart change start process is executed. Figure 24 is a flowchart showing the special chart change start process.

In the special chart change start process, the number of reserved information stored in the reserved area RE is 1 or more (step S401: YES), and the data setting process is executed (step S402). In the data setting process, the reserved number is first subtracted by 1, and the data stored in the first reserved area RE1 of the reserved area RE is moved to the execution area AE. Then, a process is executed to shift the data stored in each reserved area RE1 to RE4 of the reserved area RE. This data shift process is a process to shift the data stored in the first reserved area RE1 to the fourth reserved area RE4 to the lower area side in order, and in detail, the data in each area is shifted from the second reserved area RE2 to the first reserved area RE1, the third reserved area RE3 to the second reserved area RE2, the fourth reserved area RE4 to the third reserved area RE3, and so on, and then the fourth reserved area RE4 is cleared to "0". At this time, a shift command to recognize that the data in the reserved area has been shifted is sent to the voice light emission control device 81. When the audio and light emission control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to a display content that corresponds to a decrease in the number of pending information items.

After the data setting process is executed, the win/loss table is read from the win/loss table storage area 64a of the main ROM 64 (step S403). As already explained, the win/loss table storage area 64a stores the low-probability win/loss table for setting 1 through the low-probability win/loss table for setting 6 and the high-probability win/loss table as win/loss tables. In step S403, first, the current win/loss lottery mode is identified by reading information indicating the win/loss lottery mode from the main RAM 65. If it is the high probability mode, the high probability win/loss table is read from the win/loss table storage area 64a. On the other hand, if it is the low probability mode, the setting state of the pachinko machine 10 is identified by reading the value of the setting value counter in the main RAM 65. Then, the low probability win/loss table corresponding to the identified setting value is read from the win/loss table storage area 64a.

Then, the hit/miss table read in step S403 is referenced to execute a hit/miss determination process (step S404). In the hit/miss determination process, it is determined whether the hit/miss determination information stored in the execution area AE, i.e., the numerical information related to the hit random number counter C1, matches the jackpot numerical information set in the hit/miss table read in step S403.

If the result of the win/loss determination process is a jackpot winning result (step S405: YES), an allocation determination process is executed (step S406). In the allocation determination process, the information for allocation determination from the information stored in the execution area AE, i.e., the numerical information related to the jackpot type counter C2, is read out. Then, by referring to the allocation table provided in the allocation table storage area 64b of the main ROM 64, it is determined which jackpot result the numerical information related to the jackpot type counter C2 read out above corresponds to. Specifically, it is determined which jackpot result it corresponds to among a low probability jackpot result, a low prize high probability jackpot result, and a most favorable jackpot result.

Then, a stop result setting process for the jackpot result is executed (step S407). Specifically, information on the form of the pattern to be finally stopped and displayed on the special chart display unit 37a in the game round related to the start of the current fluctuation is identified from a stop result table for the jackpot result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. In this stop result table for the jackpot result, information on the form of the pattern to be stopped and displayed on the special chart display unit 37a is set differently for each type of jackpot result.

Then, a flag set process corresponding to the distribution determination result is executed (step S408). Specifically, flags corresponding to the types of each jackpot result are provided in the main RAM 65, and in step S408, the flag corresponding to the result of the distribution determination process in step S406 is set to "1".

On the other hand, if it is determined in step S405 that the result is not a jackpot win, a stop result setting process for a miss result is executed (step S409). Specifically, information on the pattern form to be finally stopped and displayed on the special chart display unit 37a in the game round related to the start of the current fluctuation is identified from a stop result table for miss results pre-stored in the main ROM 64, and the identified information is written to the main RAM 65. The information on the pattern form selected in this case is different from the information on the pattern form selected in the case of a jackpot win result.

After executing either step S408 or step S409, a process for grasping the duration of the game round is executed (step S410). In this process, the numerical information of the fluctuation type counter CS is acquired. Also, it is determined whether or not a reach display will occur on the pattern display device 41 in the current game round. Specifically, if the game round related to the start of the current fluctuation has a low probability jackpot result or a most favorable jackpot result, it is determined that a reach display will occur. Also, if there is no jackpot result and furthermore the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display will occur.

If it is determined that a reach display will occur, the reach occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game corresponding to the current numerical information of the variable type counter CS. On the other hand, if it is determined that a reach display will not occur, the reach non-occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game corresponding to the current numerical information of the variable type counter CS. Incidentally, the duration of the game that can be obtained by reference to the reach non-occurrence duration table is different from the duration of the game that can be obtained by reference to the reach occurrence duration table.

The duration of the game when a reach does not occur is set so that the more reserved information stored in the reserved area RE, the shorter the duration of the game. In addition, the non-reach duration table is set so that a shorter duration of the game is selected when the support mode is a high-frequency support mode than when the support mode is a low-frequency support mode, when the number of reserved information is the same. However, this is not limited to this, and the duration of the game may not change depending on the number of reserved information or the support mode, and the above relationship may be reversed. Furthermore, the above configuration may be applied to the duration of the game when a reach occurs. In addition, a duration table may be set separately for each of various jackpot results, a miss reach, and a miss result without a reach. In this case, the duration of the game is allocated according to each game result.

Then, the information on the duration of the game acquired in step S410 is set in the special chart special electricity timer counter provided in the main RAM 65 (step S411). The update of the numerical information set in the special chart special electricity timer counter is executed in the timer update process (step S210). Incidentally, as a performance for a game round, the display of changing patterns in the special chart display section 37a and the display of changing patterns in the pattern display device 41 are performed, and when each of these display of changes is ended, the final stop display is performed for the final stop period (e.g., 0.5 seconds) in a state in which the stop result of that game round is displayed (in the pattern display device 41, a predetermined combination of patterns is waiting on the active line). In this case, the duration of the game round acquired in step S410 is the total time for one game round.

Then, the variation command and the type command are sent to the sound and light emission control device 81 (step S412). The variation command includes information on the duration of the game round. Here, as described above, the duration of the game round obtained by referring to the non-reach duration table is different from the duration of the game round obtained by referring to the reach duration table. Therefore, even if the variation command does not include information on whether or not a reach has occurred, the sound and light emission control device 81 can determine whether or not a reach has occurred from the information on the duration of the game round. In this respect, it can be said that the variation command includes information indicating whether or not a reach has occurred. Note that the variation command may also include information directly indicating whether or not a reach has occurred. Furthermore, the type command includes information on the game result.

When the sound and light emission control device 81 receives a variation command and a type command from the main CPU 63, it causes the decorative boards 56, 57, the speaker unit 53, and the pattern display device 41 to execute the presentation for the game round. In this case, the presentation for that game round is executed in a manner corresponding to the contents of the variation command and the type command. In addition, the pattern display device 41 displays a variation of the patterns as the presentation for the game round, and when the presentation for that game round ends, a combination of patterns corresponding to the results of the win/lose determination process and the allocation determination process is displayed in a stopped state.

Then, the display of the changing pattern on the special chart display unit 37a is started (step S413). Then, the special chart special electricity counter is incremented by 1 (step S414), and the special chart change start process is terminated. When the special chart change start process is executed, the numerical information of the special chart special electricity counter is "0". By incrementing "1" in step S414, the numerical information of the special chart special electricity counter becomes "1".

Returning to the explanation of the special chart special electricity control process (FIG. 23), in step S307, special chart change processing is executed. In the special chart change processing, it is determined whether or not it is during the duration of a game round and before the final stop display, and if it is before the final stop display, processing is executed to regularly change the display mode of the image in the special chart display section 37a. When it is time to display the final stop, the numerical information of the special chart special electricity counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special chart change processing to that corresponding to the special chart determination processing. Note that in this embodiment, a final stop command is not transmitted from the main CPU 63 to the sound and light emission control device 81.

In step S308, a special chart determination process is executed. In the special chart determination process, the display mode of the image on the special chart display unit 37a is changed to a display mode corresponding to the lottery result of the current game round. In addition, in the special chart determination process, it is determined whether the final stop period has elapsed, and if the period has elapsed, it is determined whether a transition to the opening and closing execution mode will occur. If a transition to the opening and closing execution mode does not occur, the numerical information of the special chart special electricity counter is cleared to "0". If a transition to the opening and closing execution mode occurs, the numerical information of the special chart special electricity counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special chart determination process to that corresponding to the special electricity start process.

In step S309, the special power start process is executed. In the special power start process, if the process for starting the opening period in the current opening/closing execution mode has not yet been executed, the process for setting the opening period is executed. In addition, an opening command is sent to the sound and light emission control device 81. By receiving the opening command, the sound and light emission control device 81 causes the opening performance to be executed on the decorative boards 56, 57, the speaker unit 53, and the pattern display device 41. If the opening period has elapsed, a start process is executed to start the first round of play. In the start process, the special power winning device 32 is opened and the end condition of the round of play is set. When setting this end condition, the upper limit continuation period for which the special power winning device 32 is to be kept open in the current first round of play is set, and the upper limit number of game balls that can be won in the special power winning device 32 in the current first round of play is set in the winning number counter provided in the main RAM 65.

In step S310, the special line open process is executed. In the special line open process, it is determined whether the end condition of the round game is met. If the end condition is met, the special line winning device 32 is closed. If the currently ended round game is not the last round game executed, the numerical information of the special chart special line counter is incremented by 1 to update the numerical information of the counter from that corresponding to the special line open process to that corresponding to the special line closed process, and if the currently ended round game is the last round game executed, the numerical information of the special chart special line counter is incremented by 2 to update the numerical information of the counter from that corresponding to the special line open process to that corresponding to the special line end process.

In step S311, special line closed processing is executed. In the special line closed processing, it is determined whether or not the interval period between rounds of play has elapsed. The interval period is set when the previous round of play ends. When the interval period has elapsed, the special line winning device 32 is opened and the end condition for the round of play is set. Then, the numerical information of the special chart special line counter is subtracted by 1, thereby updating the numerical information of the counter from that corresponding to the special line closed processing to that corresponding to the special line open processing.

In step S312, the special call termination process is executed. In the special call termination process, if the process for starting the ending period in the current opening/closing execution mode has not yet been executed, the ending period (e.g., 5 seconds) is set and an ending command is sent to the sound and light emission control device 81. By receiving the ending command, the sound and light emission control device 81 causes the decorative boards 56, 57, the speaker unit 53, and the pattern display device 41 to execute an ending performance. When the ending period has elapsed, the win/lose lottery mode and the support mode after the end of the opening/closing execution mode are each set to a mode corresponding to the jackpot result that triggered the start of the current opening/closing execution mode.

The present embodiment described above provides the following excellent advantages:

In the first decorative board 56, the same number (specifically, two) of wiring patterns 172a to 172d are drawn out from a pair of pads 171a, 171b corresponding to a pair of electrodes 85a, 85b of the bypass capacitor 85. The direction (right direction) in which the first wiring pattern 172a is drawn out of the four sides of the first pad 171a when viewed from the center of the first pad 171a is the same direction as the direction (right direction) in which the third wiring pattern 172c is drawn out of the four sides of the second pad 171b when viewed from the center of the second pad 171b. In addition, the direction (left direction) in which the second wiring pattern 172b is drawn out of the four sides of the first pad 171a when viewed from the center of the first pad 171a is the same direction as the direction (left direction) in which the fourth wiring pattern 172d is drawn out of the four sides of the second pad 171b when viewed from the center of the second pad 171b. This prevents differences in temperature distribution within the pair of pads 171a, 171b during the initial heating stage of the reflow process, and also prevents the bypass capacitor 85 from rotating and becoming chip-standing.

The bypass capacitor 85 is a small chip component with a longitudinal dimension of approximately 0.6 mm, and a transverse dimension and a thickness dimension of approximately 0.3 mm. Since the longitudinal dimension of the bypass capacitor 85 along a plane perpendicular to the thickness direction is 0.7 mm or less, the area occupied by the bypass capacitor 85 on the first decorative board 56 can be reduced. Since the longitudinal dimension of the bypass capacitor 85 is 0.4 mm or more, the mechanical strength of the connection point between the bypass capacitor 85 and the first decorative board 56 and the mechanical strength of the bypass capacitor 85 itself can be increased, and the possibility of the connection point being damaged and the possibility of the bypass capacitor 85 itself being damaged can be reduced. In addition, since the longitudinal dimension of the bypass capacitor 85 is 0.4 mm or more, the accuracy of confirmation when visually checking whether or not the bypass capacitor 85 is missing from installation can be improved.

In a configuration in which the same number (specifically, one) of wiring patterns 181a, 181b are drawn out from a pair of pads 176a, 176b corresponding to a pair of electrodes 87a, 87b of a small chip resistor 87, the direction (rightward) of the side from which the first wiring pattern 181a is drawn out when viewed from the center of the first pad 176a among the four sides of the first pad 176a is the same direction as the direction (rightward) of the side from which the second wiring pattern 181b is drawn out when viewed from the center of the second pad 176b among the four sides of the second pad 176b. This makes it possible to prevent differences in temperature distribution within the pair of pads 176a, 176b during the initial heating stage of the reflow process, and to prevent rotation and chip standing of the small chip resistor 87.

Like the bypass capacitor 85, the small chip resistor 87 is a small chip component whose longitudinal dimension (longitudinal dimension of the small chip resistor 87) along a plane perpendicular to the thickness direction of the component is 0.1 mm or more and 0.9 mm or less. The small chip resistor 87 is a small chip component whose longitudinal dimension is approximately 0.6 mm and whose short-side dimension and thickness dimension are approximately 0.3 mm. Since the longitudinal dimension of the small chip resistor 87 is 0.7 mm or less, the area occupied by the small chip resistor 87 on the first decorative substrate 56 can be reduced. Since the longitudinal dimension of the small chip resistor 87 is 0.4 mm or more, the mechanical strength of the connection point between the small chip resistor 87 and the first decorative substrate 56 and the mechanical strength of the small chip resistor 87 itself can be increased, and the possibility of the connection point being damaged can be reduced, and the possibility of the small chip resistor 87 itself being damaged can be reduced. In addition, by having the longitudinal dimension of the small chip resistor 87 be 0.4 mm or more, the accuracy of visually checking whether or not the small chip resistor 87 is missing from the mounting can be improved.

The first pad 171a corresponding to the first electrode 85a of the bypass capacitor 85 is electrically connected to the GND plane layer 93 having a larger area than the first pad 171a through the first wiring pattern 172a, and the second pad 171b corresponding to the second electrode 85b of the bypass capacitor 85 is electrically connected to the power plane layer 94 having a larger area than the second pad 171b through the third wiring pattern 172c. The direction (rightward) in which the side from which the first wiring pattern 172a is drawn out exists among the four sides of the first pad 171a as viewed from the center of the first pad 171a is the same direction as the direction (rightward) in which the side from which the third wiring pattern 172c is drawn out exists among the four sides of the second pad 171b as viewed from the center of the second pad 171b. This reduces the possibility of a difference in temperature distribution occurring within the pair of pads 171a and 171b during the initial heating stage of the reflow process.

The width dimension of the first wiring pattern 172a drawn from the first pad 171a corresponding to the first electrode 85a of the bypass capacitor 85 is approximately the same as the width dimension of the third wiring pattern 172c drawn from the second pad 171b corresponding to the second electrode 85b. Therefore, compared to a configuration in which the width dimensions of these wiring patterns 172a, 172c are different, the possibility of a difference in temperature distribution in the pair of pads 171a, 171b occurring in the initial heating stage of the reflow process is reduced. In addition, the width dimension of the second wiring pattern 172b drawn from the first pad 171a is approximately the same as the width dimension of the fourth wiring pattern 172d drawn from the second pad 171b. Therefore, compared to a configuration in which the width dimensions of these wiring patterns 172b, 172d are different, the possibility of a difference in temperature distribution in the pair of pads 171a, 171b occurring in the initial heating stage of the reflow process is reduced.

The width dimension of the first wiring pattern 181a drawn from the first pad 176a corresponding to the first electrode 87a of the small chip resistor 87 is approximately the same as the width dimension of the second wiring pattern 181 drawn from the second pad 176b corresponding to the second electrode 87b. Therefore, compared to a configuration in which the width dimensions of the wiring patterns 181a, 181b drawn from the pads 176a, 176b are different, the possibility of a difference in temperature distribution occurring within the pair of pads 176a, 176b during the initial heating stage of the reflow process is reduced.

The number and positions of the wiring patterns 172a to 172d drawn out from the pair of pads 171a and 171b corresponding to the pair of electrodes 85a and 85b of the bypass capacitor 85 are common, so that the force acting on the first electrode 85a of the bypass capacitor 85 due to the surface tension of the molten solder on the first pad 171a and the force acting on the second electrode 85b of the bypass capacitor 85 due to the surface tension of the molten solder on the second pad 171b can be balanced. Therefore, even if only the left side of the solder paste melts first in the pair of pads 171a and 171b, the movement mode of the bypass capacitor 85 can be made parallel, and the rotation of the bypass capacitor 85 can be prevented. This makes it possible to suppress the degree of reduction in the connection area due to the solder fillet 173a between the first pad 171a and the first electrode 85a, and to suppress the degree of reduction in the connection area due to the solder fillet 173b between the second pad 171b and the second electrode 85b.

Since the number and drawing positions of the wiring patterns 181a, 181b drawn from the pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the small chip resistor 87 are common, the force acting on the first electrode 87a of the small chip resistor 87 due to the surface tension of the molten solder on the first pad 176a and the force acting on the second electrode 87b of the small chip resistor 87 due to the surface tension of the molten solder on the second pad 176b can be balanced. Therefore, even if only the left side of the solder paste of the pair of first pads 176a and second pads 176b melts first, the movement mode of the small chip resistor 87 is parallel movement, and the rotation of the small chip resistor 87 can be prevented. This makes it possible to suppress the degree of reduction in the connection area due to the solder fillet 177a between the first pad 176a and the first electrode 87a, and also to suppress the degree of reduction in the connection area due to the solder fillet 177b between the second pad 176b and the second electrode 87b.

The small chip components (bypass capacitors 85 and small chip resistors 87) are mounted on the first decorative substrate 56 so that the longitudinal direction of the small chip components is parallel to the first direction DR1. The dimension of the first decorative substrate 56 in the first direction DR1 is greater than the dimension of the first decorative substrate 56 in the second direction DR2 perpendicular to the first direction DR1. If the small chip components are mounted on the first decorative substrate 56 so that the longitudinal direction of the small chip components is perpendicular to the first direction DR1, when a force acts on the first decorative substrate 56 to bend the first decorative substrate 56 from the boundary line extending in the first direction DR1, there is a risk that stress that damages the connection between the small chip components and the first decorative substrate 56 may act on the connection, and there is a risk that stress that damages the small chip components may act on the small chip components themselves. In contrast, the small chip components are mounted on the first decorative substrate 56 so that the longitudinal direction of the small chip components is perpendicular to the first direction DR1, thereby reducing the maximum stress that can act on the connection points between the small chip components and the first decorative substrate 56, and reducing the maximum stress that can act on the small chip components. This prevents damage to the connection points between the small chip components and the first decorative substrate 56, and prevents damage to the small chip components themselves.

The small chip components (bypass capacitor 97 and small chip resistor 101) are mounted on the second decorative substrate 57 so that the longitudinal direction of the small chip components is parallel to the longitudinal direction LD. The dimension of the second decorative substrate 57 in the longitudinal direction LD is larger than the dimension of the second decorative substrate 57 in the short axis direction SD perpendicular to the longitudinal direction LD. If the small chip components are mounted on the second decorative substrate 57 so that the longitudinal direction of the small chip components is perpendicular to the longitudinal direction LD, when a force acts on the second decorative substrate 57 to bend the second decorative substrate 57 from the boundary line extending in the longitudinal direction LD as a base point, there is a risk that stress that will damage the connection between the small chip components and the second decorative substrate 57 will act on the small chip components themselves. In contrast, the small chip components are mounted on the second decorative substrate 57 so that their longitudinal direction is perpendicular to the long axis direction LD, reducing the maximum stress that can act on the connection points between the small chip components and the second decorative substrate 57, and reducing the maximum stress that can act on the small chip components. This prevents damage to the connection points between the small chip components and the second decorative substrate 57, and prevents damage to the small chip components themselves.

The electrodes 85a, 85b of the bypass capacitor 85 are fixed to the pads 171a, 171b by solder fillets 173a, 173b. The pads 171a, 171b and the wiring patterns 172a to 172d are integrally formed by etching a copper foil plate. The wiring patterns 172a to 172d drawn out from the pads 171a, 171b extend in a direction perpendicular to the longitudinal direction of the bypass capacitor 85 (short side direction) or in a direction approximately perpendicular to the longitudinal direction of the bypass capacitor 85. If the wiring patterns 172a to 172d drawn from the pads 171a and 171b are configured to extend in a direction parallel to the longitudinal direction of the bypass capacitor 85, when the first decorative substrate 56 is distorted in a direction in which the first decorative substrate 56 is bent from a boundary line perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 85 as a base point, there is a risk that stress that may damage the connection point between the bypass capacitor 85 and the first decorative substrate 56 may act on the bypass capacitor 85 itself, and there is a risk that stress that may damage the bypass capacitor 85 may act on the bypass capacitor 85 itself. In contrast, by configuring the wiring patterns 172a to 172d drawn from the pads 171a and 171b to extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 85, it is possible to reduce the maximum value of stress that may act on the connection point between the bypass capacitor 85 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56, and to reduce the maximum value of stress that may act on the bypass capacitor 85 itself.

The electrodes 87a, 87b of the small chip resistor 87 are fixed to the pads 176a, 176b by solder fillets 177a, 177b. The pads 176a, 176b and the wiring patterns 181a, 181b are integrally formed by etching a copper foil plate. The wiring patterns 181a, 181b drawn from the pads 176a, 176b extend in a direction perpendicular to the longitudinal direction of the small chip resistor 87 (short side direction) or in a direction approximately perpendicular to the longitudinal direction of the small chip resistor 87. If the wiring patterns 181a, 181b drawn out from the pads 176a, 176b are configured to extend in a direction parallel to the longitudinal direction of the small chip resistor 87, when a bending stress acts on the first decorative substrate 56 so as to bend the first decorative substrate 56 at a line perpendicular or approximately perpendicular to the long side direction of the small chip resistor 87, there is a risk that stress will act on the connection point between the small chip resistor 87 and the first decorative substrate 56 causing the connection point to be damaged, and there is also a risk that stress will act on the small chip resistor 87 itself causing the small chip resistor 87 to be damaged. In contrast, by configuring the wiring patterns 181a, 181b drawn out from the pads 176a, 176b to extend in a direction perpendicular or nearly perpendicular to the longitudinal direction of the small chip resistor 87, it is possible to reduce the maximum stress that can act on the connection point between the small chip resistor 87 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56, and also to reduce the maximum stress that can act on the small chip resistor 87 itself.

The first pad 176a electrically connected to the first electrode 87a of the small chip resistor 87 is electrically connected to the second pad 178b electrically connected to the second electrode 142b of the LED chip 142 via the first wiring pattern 181a (see FIG. 8(c)). The second pad 176b electrically connected to the second electrode 87b of the small chip resistor 87 is electrically connected to a pad (not shown) electrically connected to the eighth output terminal 162 (FIG. 11) of the LED driver 126 (FIG. 8(a)) via the second wiring pattern 181b. The location where the second wiring pattern 181b is connected in the pad (not shown) corresponding to the eighth output terminal 162 is located in the opposite direction to the direction in which the second wiring pattern 181b is pulled out from the second pad 176b when viewed in the direction of one axis (second direction DR2 in FIGS. 8A and 8C) including the direction in which the second wiring pattern 181b is pulled out from the second pad 176b (rightward in FIGS. 8A and 8C). The second wiring pattern 181b is pulled out from the second pad 176b in the same direction (rightward) as the direction in which the first wiring pattern 181a is pulled out from the first pad 176a, and then routed in the opposite direction when viewed in the direction of the one axis (second direction DR2). Even in a configuration in which the second wiring pattern 181b is connected to the connection destination at a location that is in the opposite direction to the direction in which the second wiring pattern 181b is pulled out from the second pad 176b when viewed in the direction of one axis (second direction DR2), the second wiring pattern 181b is pulled out from the second pad 176b in the same direction as the direction in which the first wiring pattern 181a is pulled out from the first pad 176a. This reduces the possibility of a difference in temperature distribution occurring within the pair of first pad 176a and second pad 176b during the initial heating stage of the reflow process.

The pair of pads corresponding to the pair of electrodes of the small chip component have the same shape and size. This allows the amount of solder paste applied to the pair of pads in the solder application process to be uniform, and the amount of molten solder generated on the pair of pads to be uniform. This allows for a balance between the force acting on the first electrode of the small chip component due to the surface tension of the molten solder on the first pad and the force acting on the second electrode of the small chip component due to the surface tension of the molten solder on the second pad. This prevents the small chip component from rotating and the chips from standing up.

The bypass capacitor 85 is mounted on the first decorative substrate 56 so that the longitudinal direction of the bypass capacitor 85 is parallel to the first direction DR1. A pair of pads 171a, 171b corresponding to a pair of electrodes 85a, 85b of the bypass capacitor 85 are spaced apart in the longitudinal direction of the bypass capacitor 85. The small chip resistor 87 is mounted on the first decorative substrate 56 so that the longitudinal direction of the small chip resistor 87 is parallel to the first direction DR1. A pair of pads 176a, 176b corresponding to a pair of electrodes 87a, 87b of the small chip resistor 87 are spaced apart in the longitudinal direction of the small chip resistor 87. In this way, the spacing direction of the pair of pads 176a, 176b is common in multiple small chip components (bypass capacitors 85 and small chip resistors 87). Therefore, by transporting the first decorative substrate 56 in a direction perpendicular or substantially perpendicular to the common separation direction in the reflow process, the timing at which heating of the solder paste applied to the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 can be synchronized, and the timing at which heating of the solder paste applied to the pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the small chip resistor 87 can be synchronized. This makes it possible to prevent rotation of multiple small chip components and the occurrence of chip standing.

In a configuration in which the small chip components (bypass capacitors 85 and small chip resistors 87) are concentrated on the first mounting surface 84 of the first decorative substrate 56, the connectors 111, 112 are mounted only on the second mounting surface 95 of the first decorative substrate 56. On the first mounting surface 84, the small chip components are arranged avoiding the connector back side corresponding areas 203, 204 (the area on the first mounting surface 84 corresponding to the area on which the connectors 111, 112 are mounted on the second mounting surface 95 and the area around it). This makes it possible to reduce the maximum value of the tensile stress that can act on the connection between the small chip components and the first decorative substrate 56 when attaching the harness to the connectors 111, 112, and to reduce the maximum value of the tensile stress that can act on the small chip components themselves. In addition, it is possible to reduce the maximum value of the compressive stress that can act on the connection between the small chip components and the first decorative substrate 56 when pulling out the harness from the connectors 111, 112, and to reduce the maximum value of the compressive stress that can act on the small chip components themselves.

In the first decorative board 56, the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are positioned at a distance of 5 mm or more from the outer edge of the fixing through holes 56d-56g. No small chip components are mounted in the through hole peripheral areas 211a-211d. By positioning the small chip components at a distance of 5 mm or more from the outer edge of the fixing through holes 56d-56g, it is possible to prevent damage to the connection points between the small chip components and the first decorative board 56 due to distortion of the first decorative board 56 that may occur near the fixing through holes 56d-56g when the first decorative board 56 is screwed to the front door frame 14, and it is also possible to prevent damage to the small chip components themselves.

No small chip components are mounted in the LED backside corresponding area 201 on the second mounting surface 95 of the first decorative substrate 56. The LED backside corresponding area 201 is an area of the second mounting surface 95 located on the back side of the area where the LED chips 127-142 are mounted on the first mounting surface 84, and an area within a distance of 1 mm from the outer edge of the area of the second mounting surface 95. Since no small chip components are mounted in the area of the second mounting surface 95 located on the back side of the area where the LED chips 127-142 are mounted on the first mounting surface 84, the influence of thermal stress that may act on the first decorative substrate 56 due to heat generation from the LED chips 127-142 on the small chip components is reduced. Since the small chip components are mounted avoiding the LED backside corresponding area 201, it is possible to prevent the connection between the small chip components and the first decorative substrate 56 from being damaged due to repeated light-emitting effects on the first decorative substrate 56, and it is also possible to prevent the small chip components themselves from being damaged.

No small chip components are mounted in the driver back side corresponding area 202 of the second mounting surface 95. The driver back side corresponding area 202 is an area of the second mounting surface 95 located behind the area where the LED driver 126 is mounted on the first mounting surface 84 and the area where the pads corresponding to the terminals of the LED driver 126 are provided, and an area within 1 mm from the outer edge of the area of the second mounting surface 95. Since no small chip components are mounted in the area of the second mounting surface 95 located behind the area where the LED driver 126 is mounted on the first mounting surface 84 and the area where the pads corresponding to the terminals of the LED driver 126 are provided, the influence of thermal stress that may act on the first decorative board 56 due to heat generation by the LED driver 126 on the small chip components is reduced. Since the small chip components are mounted avoiding the driver back side corresponding area 202, it is possible to prevent the connection between the small chip components and the first decorative board 56 from being damaged due to repeated execution of the light-emitting performance on the first decorative board 56, and it is also possible to prevent the small chip components themselves from being damaged.

In the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistor 87) are arranged at a distance of 1 mm or more from the outer edge of the LED chip 142. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, the effect of thermal stress on the connection points between the small chip components and the first decorative substrate 56 can be minimized, and the effect of thermal stress on the small chip components themselves can be minimized. In addition, by arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, the connection points between the small chip components and the first decorative substrate 56 can be prevented from being damaged by thermal stress, and the small chip components themselves can be prevented from being damaged by thermal stress.

In the first decorative substrate 56, the small chip components (bypass capacitors 85 and small chip resistors 87) are arranged at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126, it is possible to prevent the connection points between the small chip components and the first decorative substrate 56 from being damaged by thermal stress, and it is also possible to prevent the small chip components themselves from being damaged by thermal stress.

In the first decorative board 56, the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are arranged to avoid the through-hole peripheral areas 211a-211d. The through-hole peripheral areas 211a-211d are areas that are less than 5 mm away from the outer edges of the fixing through holes 56d-56g. By arranging the small chip components 5 mm or more away from the outer edges of the fixing through holes 56d-56g, it is possible to prevent damage to the connection points between the small chip components and the first decorative board 56 due to distortion of the first decorative board 56 that may occur near the fixing through holes 56d-56g when the first decorative board 56 is screwed to the front door frame 14, and it is also possible to prevent damage to the small chip components themselves.

On the first mounting surface 84, the small chip components are arranged to avoid the connector back side corresponding regions 203, 204. The connector back side corresponding regions 203, 204 are the region of the first mounting surface 84 located on the back side of the region where the connectors 111, 112 are mounted on the second mounting surface 95, and the region that is less than 5 mm away from the outer edge of the region of the first mounting surface 84. Since the small chip components are not mounted in the region of the first mounting surface 84 located on the back side of the region where the connectors 111, 112 are mounted on the second mounting surface 95, the effect of stress that may act on the first decorative substrate 56 when the harness is attached to and detached from the connectors 111, 112 on the small chip components is reduced. Since the small chip components are arranged to avoid the connector back side corresponding regions 203, 204, the connection points between the small chip components and the first decorative substrate 56 are prevented from being damaged when the harness is attached to and detached from the connectors 111, 112, and the small chip components themselves are prevented from being damaged.

The LED driver 126 is arranged in an area including an area less than 10 mm from the outer edge of the first decorative substrate 56, while the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149 (Figure 11)) are arranged 10 mm or more away from the outer edge of the first decorative substrate 56. The connection points between the small chip components and the first decorative substrate 56, among the various electronic components mounted on the first decorative substrate 56, have lower mechanical strength than the connection points between the other electronic components and the first decorative substrate 56. By arranging the small chip components 10 mm or more away from the outer edge of the first decorative substrate 56, the possibility of the connection points between the small chip components and the first decorative substrate 56 being damaged by the hand of an operator touching the small chip components when handling the first decorative substrate 56 is reduced, and the possibility of the small chip components themselves being damaged is reduced. In addition, the maximum value of the stress that can act on the connection points between the small chip components and the first decorative substrate 56 when the collective substrate 231 is divided is reduced, and the maximum value of the stress that can act on the small chip components themselves is reduced.

In a configuration in which the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are arranged to avoid the through-hole peripheral areas 211a-211d and areas less than 10 mm away from the outer edge of the first decorative substrate 56, the fixing through holes 56d-56g are provided in areas less than 10 mm away from the outer edge of the first decorative substrate 56. Therefore, compared to a configuration in which the fixing through holes 56d-56g are provided at positions 10 mm or more away from the outer edge of the first decorative substrate 56, a larger area is ensured in the first decorative substrate 56 in which small chip components can be mounted.

A bypass capacitor 85 is disposed between the power supply terminal 151 of the LED driver 126 and the power supply plane layer 94. This reduces the effect of noise components contained in the driving power supplied from the sound emission control device 81 to the LED driver 126 on the LED driver 126. The bypass capacitor 85 is disposed close to the power supply terminal 151 so that there are no other electronic components such as ICs between the bypass capacitor 85 and the power supply terminal 151. This increases the possibility that the noise components contained in the driving power supplied to the power supply terminal 151 of the LED driver 126 are absorbed by the bypass capacitor 85, and reduces the possibility that the LED driver 126 will malfunction due to the influence of the noise components. Since there are no other ICs between the bypass capacitor 85 and the power supply terminal 151, the noise components generated by the LED driver 126 can be absorbed by the bypass capacitor 85, preventing the noise components from causing other ICs to malfunction. In addition, since there are no other electronic components between the bypass capacitor 85 and the power supply terminal 151, the noise components generated by the LED driver 126 are absorbed by the bypass capacitor 85, preventing the noise components from causing malfunctions in other electronic components.

Around the bypass capacitor 85, only the identification silk 217 (indicated as "C1") is provided to confirm that the mounted electronic component is the bypass capacitor 85, and no outline silk is provided to allow the mounting position of the bypass capacitor 85 to be grasped. The outside dimensions (length, width, and height) of the bypass capacitor 85 are smaller than the outside dimensions of electronic components other than small chip components (such as the LED driver 126 and the LED chips 127 to 142). For this reason, if the outline silk of the bypass capacitor 85 is printed on the first decorative board 56, there is a risk that the worker may mistakenly recognize that the bypass capacitor 85 is mounted by looking only at the outline silk, even though the bypass capacitor 85 is actually missing after mounting the electronic components. In contrast, by configuring the bypass capacitor 85 so that no outline silk is provided around it, it is easier to grasp the missing mounting of the bypass capacitor 85 after mounting the electronic components. In addition, by providing the identification silk 217 around the bypass capacitor 85, it is possible to grasp that the component mounted around the identification silk 217 is the bypass capacitor 85.

The external dimensions of the small chip resistor 87, like those of the bypass capacitor 85, are smaller than those of electronic components other than small chip components. Around the small chip resistor 87, only an identification silk 218 (marked "R8") is provided to confirm that the mounted electronic component is a small chip resistor 87, and no contour silk is provided to confirm the mounting position of the small chip resistor 87. This makes it easier to identify any missing mounting of the small chip resistor 87. Also, by providing the identification silk 218 around the small chip resistor 87, it is possible to identify that the electronic component mounted around the identification silk 218 is a small chip resistor 87.

Since the outer silk 225a, 225b are convex with respect to the surface of the solder resist 222, if the outer silk 225a, 225b are provided around the small chip components (bypass capacitor 85 and small chip resistor 87), the outer silk 225a, 225b will be between the first mounting surface 84 and the metal mask 226, and the distance between the first mounting surface 84 and the metal mask 226 will increase. In this configuration, the solder paste 227 may get into the gap between the first pad 171a and the second pad 171b, and the first pad 171a and the second pad 171b may be electrically connected. In particular, when the solder paste 221 is applied continuously to a large number of first decorative substrates 56, the solder paste 221 that accumulates on the edge of the opening of the metal mask 226 tends to flow around to the back side of the opening, and the first pad 171a and the second pad 171b tend to be electrically connected. In contrast, in this embodiment, the outline silk is not provided around the small chip components. This prevents the distance between the first mounting surface 84 and the metal mask 226 from becoming too large, and prevents solder defects caused by the solder paste 221 getting between the pads 171a and 171b. It also prevents parts of the small chip components from being placed on the outline silk, which can cause solder defects.

In addition, the LED backside corresponding area 201 on the second mounting surface 95 of the first decorative substrate 56 where small chip components are not mounted is not limited to the area of the second mounting surface 95 located on the back side of the area on the first mounting surface 84 (FIG. 8(a)) where the LED chips 127-142 (FIG. 9) are mounted, and the area within 1 mm from the outer edge of the area of the second mounting surface 95. The LED backside corresponding area 201 may be the area of the second mounting surface 95 located on the back side of the area on the first mounting surface 84 where the LED chips 127-142 are mounted, and the area within 2 mm from the outer edge of the area of the second mounting surface 95. This further reduces the effect of thermal stress on the small chip components that may act on the first decorative substrate 56 due to heat generated by the LED chips 127-142. This reduces the possibility that the connection between the small chip component and the first decorative substrate 56 will be damaged due to the repeated execution of the light-emitting effects on the first decorative substrate 56, and also reduces the possibility that the small chip component itself will be damaged.

The driver back side corresponding area 202 on the second mounting surface 95 of the first decorative substrate 56 where small chip components are not mounted is not limited to the area of the second mounting surface 95 located on the back side of the area where the LED driver 126 (FIG. 8(a)) is mounted and the area where the pads corresponding to the terminals of the LED driver 126 are provided on the first mounting surface 84 (FIG. 8(a)), and the area within 1 mm from the outer edge of the area of the second mounting surface 95. The driver back side corresponding area 202 may be the area of the second mounting surface 95 located on the back side of the area where the LED driver 126 is mounted and the area where the pads corresponding to the terminals of the LED driver 126 are provided on the first mounting surface 84, and the area within 2 mm from the outer edge of the area of the second mounting surface 95. This further reduces the effect of thermal stress on the small chip components that may act on the first decorative substrate 56 due to heat generated by the LED driver 126. This reduces the possibility that the connection between the small chip component and the first decorative substrate 56 will be damaged due to the repeated execution of the light-emitting effects on the first decorative substrate 56, and also reduces the possibility that the small chip component itself will be damaged.

- In the first decorative board 56, the through hole peripheral areas 211a-211d in which the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (FIG. 11)) are not mounted are not limited to areas less than 5 mm away from the outer edge of the fixed through holes 56d-56g. The through hole peripheral areas 211a-211d may be areas less than 7 mm away from the outer edge of the fixed through holes 56d-56g. This reduces the possibility that the connection points between the small chip components and the first decorative board 56 will be damaged due to distortion of the first decorative board 56 that may occur near the fixed through holes 56d-56g when the first decorative board 56 is screwed to the front door frame 14, and also reduces the possibility that the small chip components themselves will be damaged. The through hole peripheral areas 211a-211d may be areas less than 4 mm away from the outer edge of the fixed through holes 56d-56g. This reduces the stress acting on the connection points between the small chip components and the first decorative substrate 56 when the first decorative substrate 56 is screwed to the front door frame 14, as well as the stress acting on the small chip components themselves, while ensuring a large area on the first decorative substrate 56 where small chip components can be mounted.

- On the first mounting surface 84 of the first decorative board 56, the connector back side corresponding areas 203, 204 where small chip components are not mounted are not limited to the area of the first mounting surface 84 located on the back side of the area where the connectors 111, 112 are mounted on the second mounting surface 95 (FIG. 15(a)) and the area that is less than 5 mm away from the outer edge of the area of the first mounting surface 84. The connector back side corresponding areas 203, 204 may be the area of the first mounting surface 84 located on the back side of the area where the connectors 111, 112 are mounted on the second mounting surface 95 and the area that is less than 7 mm away from the outer edge of the area of the first mounting surface 84. This reduces the possibility that the connection points between the small chip components and the first decorative board 56 will be damaged when the harness is attached to or detached from the connectors 111, 112, and reduces the possibility that the small chip components themselves will be damaged. The connector backside corresponding areas 203, 204 may be areas of the first mounting surface 84 located on the back side of the area where the connectors 111, 112 are mounted on the second mounting surface 95, and areas that are less than 4 mm away from the outer edge of the area of the first mounting surface 84. This makes it possible to reduce the stress acting on the connection points between the small chip components and the first decorative substrate 56 and on the small chip components themselves when attaching and detaching the harness to the connectors 111, 112, while ensuring a large area on the first decorative substrate 56 where small chip components can be mounted.

- The area near the outer edge of the first decorative substrate 56 where small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are not mounted is not limited to an area less than 10 mm away from the outer edge of the first decorative substrate 56. The area near the outer edge of the substrate where small chip components are not mounted may be an area less than 12 mm away from the outer edge of the first decorative substrate 56. This reduces the possibility of the connection between the small chip components and the first decorative substrate 56 being damaged due to the worker's hands touching the small chip components when handling the first decorative substrate 56, and also reduces the possibility of the small chip components themselves being damaged. In addition, when a collective substrate 231 including a plurality of first decorative substrates 56 is divided to remove the first decorative substrates 56, the stress that may act on the connection between the small chip components and the first decorative substrate 56 when the collective substrate 231 is divided can be reduced, and the stress acting on the small chip components themselves can be reduced. In addition, the area near the outer edge of the board where small chip components are not mounted may be an area that is less than 8 mm away from the outer edge of the first decorative board 56. This reduces the possibility of damage to the connection between the small chip components and the first decorative board 56 and to the small chip components themselves, while ensuring a large area on the first decorative board 56 where small chip components can be mounted.

Second Embodiment
This embodiment differs from the first embodiment in that the longitudinal direction of some of the small chip components mounted on the first decorative substrate 56 is perpendicular to the first direction DR1. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment is basically omitted.

Figure 25(a) is a plan view showing the first mounting surface 84 of the first decorative substrate 56 in this embodiment, and Figure 25(b) is a plan view of the first mounting surface 84 of the first decorative substrate 56 showing an enlarged peripheral area 292 of a bypass capacitor 291 mounted on the first decorative substrate 56. As in the first embodiment described above, the dimension of the first decorative substrate 56 in the first direction DR1 is larger than the dimension of the first decorative substrate 56 in a direction perpendicular to the first direction DR1, as shown in Figure 25(a).

25(b), the bypass capacitor 291 is a small chip component having a dimension of 0.1 mm or more and 0.9 mm or less in the longitudinal direction along a plane perpendicular to the thickness direction of the bypass capacitor 291 (hereinafter also referred to as the "longitudinal direction of the bypass capacitor 291"), similar to the bypass capacitor 85 in the first embodiment. The bypass capacitor 291 is a small chip component having a dimension of approximately 0.6 mm in the longitudinal direction along a plane perpendicular to the thickness direction, and a dimension of approximately 0.3 mm in the transverse direction along a plane perpendicular to the thickness direction (hereinafter also referred to as the "transverse direction") and in the thickness direction. Since the dimension of the bypass capacitor 291 in the longitudinal direction along a plane perpendicular to the thickness direction is 0.7 mm or less, the area occupied by the bypass capacitor 291 in the light emitting substrate 301 can be reduced. By having the longitudinal dimension of the bypass capacitor 291 along the plane perpendicular to the thickness direction be 0.4 mm or more, the mechanical strength of the connection between the bypass capacitor 291 and the light emitting substrate 301 and the mechanical strength of the bypass capacitor 291 itself can be increased, and the possibility of the connection being damaged can be reduced, and the possibility of the bypass capacitor 291 itself being damaged can be reduced. In addition, by having the longitudinal dimension of the bypass capacitor 291 be 0.4 mm or more, the accuracy of checking whether or not the bypass capacitor 291 is missing from mounting can be improved when checking visually. Note that the longitudinal dimension of the bypass capacitor 291 may be smaller than 0.6 mm (e.g., 0.4 mm), the lateral dimension of the bypass capacitor 291 may be smaller than 0.3 mm (e.g., 0.2 mm), or the thickness dimension may be smaller than 0.3 mm (e.g., 0.2 mm).

The first wiring pattern 294a drawn from the first pad 293a (or first pad) corresponding to the first electrode 291a of the bypass capacitor 291 is electrically connected to the GND plane layer 93 (FIG. 9) through a via hole 295 provided in the first decorative substrate 56, and the second wiring pattern 294b drawn from the first pad 293a is electrically connected to the GND terminal 297 (ground terminal or ground terminal) of the LED driver 296. The third wiring pattern 294c drawn from the second pad 293b (or second pad) corresponding to the second electrode 291b of the bypass capacitor 291 is electrically connected to the power plane layer 94 (FIG. 9) through a via hole 298 provided in the first decorative substrate 56, and the fourth wiring pattern 294d drawn from the second pad 293b is electrically connected to the power terminal 299 of the LED driver 296. In this way, the first pad 293a is arranged between the GND terminal 297 of the LED driver 296 and the GND plane layer 93, and the second pad 293b is arranged between the power terminal 299 of the LED driver 296 and the power plane layer 94.

The bypass capacitor 291 is mounted on the first decorative substrate 56 so that the longitudinal direction of the bypass capacitor 291 is perpendicular or nearly perpendicular to the first direction DR1. The first wiring pattern 294a is drawn upward from the upper end of the first pad 293a, and the second wiring pattern 294b is drawn downward from the lower end of the first pad 293a. The third wiring pattern 294c is drawn upward from the upper end of the second pad 293b, and the fourth wiring pattern 294d is drawn downward from the lower end of the second pad 293b.

In this way, the wiring patterns 294a to 294d drawn from a pair of pads 293a, 293b corresponding to a pair of electrodes 291a, 291b of the bypass capacitor 291 extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 291. Therefore, compared to a configuration in which the wiring patterns 294a to 294d drawn from a pair of pads 293a, 293b extend in a direction parallel to the longitudinal direction of the bypass capacitor 291, it is possible to reduce stress that may act on the connection between the bypass capacitor 291 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56, and to reduce stress that may act on the bypass capacitor 291 itself. For example, when the collective substrate 231 is divided, it is possible to reduce stress that may act on the connection between the bypass capacitor 291 and the first decorative substrate 56, and to reduce stress that may act on the bypass capacitor 291 itself.

The present embodiment described above provides the following excellent advantages:

The dimension of the first decorative substrate 56 in the first direction DR1 is larger than the dimension of the first decorative substrate 56 in a direction perpendicular to the first direction DR1. In a configuration in which the longitudinal direction of the bypass capacitor 291 is perpendicular to the first direction DR1, the wiring patterns 294a to 294d drawn from a pair of pads 293a, 293b corresponding to a pair of electrodes 291a, 291b of the bypass capacitor 291 extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 291. Therefore, compared to a configuration in which the wiring patterns 294a to 294d drawn from a pair of pads 293a, 293b extend in a direction parallel to the longitudinal direction of the bypass capacitor 291, when the first decorative substrate 56 is distorted, it is possible to reduce stress that may act on the connection point between the bypass capacitor 291 and the first decorative substrate 56, and also to reduce stress that may act on the bypass capacitor 291 itself.

Third Embodiment
This embodiment differs from the first embodiment in that it includes a light emitting substrate having LED chips mounted on both plate surfaces. The following describes the configuration different from the first embodiment. Note that the description of the same configuration as the first embodiment is basically omitted.

A movable object (not shown) is provided to the right of the pattern display device 41 on the front side of the game board 24 (Figure 4). The movable object is placed in an area where game balls do not flow down. The movable object includes a light-emitting board 301 (Figure 26) with LED chips mounted on both board surfaces, and a board case (not shown) that houses the light-emitting board 301.

26 is a plan view of the first light-emitting surface 302 of the light-emitting substrate 301 in this embodiment, and FIG. 27 is a plan view of the second light-emitting surface 303 of the light-emitting substrate 301. In FIG. 26, the wiring pattern formed on the first light-emitting surface 302 is omitted, and in FIG. 27, the wiring pattern formed on the second light-emitting surface 303 is omitted. As shown in FIG. 26, the light-emitting substrate 301 is formed in a vertically elongated, approximately elliptical shape. The light-emitting substrate 301 is a four-layer substrate having a structure in which conductive layers and insulating layers are alternately laminated, similar to the first decorative substrate 56 in the first embodiment. Although not shown, the light-emitting substrate 301 has a first wiring layer arranged on the first light-emitting surface 302 side and a second wiring layer arranged on the second light-emitting surface 303 side, similar to the first decorative substrate 56 in the first embodiment. In addition, like the first decorative substrate 56 in the first embodiment, the light-emitting substrate 301 includes a GND plane layer (ground plane layer or ground plane layer) and a power plane layer as conductive layers disposed between the first wiring layer and the second wiring layer.

As shown in FIG. 26, LED chips 304-313 and a first LED driver 314 that controls the light emission of these LED chips 304-313 are mounted on the first light-emitting surface 302 of the light-emitting substrate 301. Also, as shown in FIG. 27, LED chips 315-325 and a second LED driver 326 that controls the light emission of these LED chips 315-325 are mounted on the second light-emitting surface 303 of the light-emitting substrate 301. As shown in FIG. 26, the LED chips 304-313 are arranged in an area near the center of the first light-emitting surface 302, and as shown in FIG. 27, the LED chips 315-325 are arranged in an area near the outer edge of the second light-emitting surface 303.

As shown in FIG. 27, a connector 327 for receiving lighting control data from the audio light-emitting control device 81 (FIG. 19) is mounted on the second light-emitting surface 303 of the light-emitting substrate 301. A harness (not shown) that electrically connects the light-emitting substrate 301 and the audio light-emitting control device 81 is attached to the connector 327. The first LED driver 314 controls the lighting of the LED chips 304 to 313 mounted on the first light-emitting surface 302 based on the lighting control data received from the audio light-emitting control device 81, and the second LED driver 326 controls the lighting of the LED chips 315 to 325 mounted on the second light-emitting surface 303 based on the lighting control data received from the audio light-emitting control device 81.

The board case (not shown) is made of a transparent or translucent resin that transmits the light emitted from the LED chips 304-313, 315-325. The board case is supported on the front side of the game board 24 and can rotate around an axis extending in the vertical direction. In a game state other than the opening and closing execution mode, the first light-emitting surface 302 of the light-emitting board 301 faces the front of the pachinko machine 10. In this game state, the light emission of the LED chips 304-313 mounted on the first light-emitting surface 302 is controlled, and an area near the center of the first light-emitting surface 302 emits light. When the game state transitions to the opening and closing execution mode, the movable object (not shown) rotates 180 degrees around the axis so that the second light-emitting surface 303 of the light-emitting board 301 faces the front of the pachinko machine 10. In the opening and closing execution mode, the light emission of the LED chips 315-325 mounted on the second light-emitting surface 303 is controlled, causing the area near the outer edge of the second light-emitting surface 303 to emit light. When the opening and closing execution mode ends, the movable object rotates 180 degrees around the axis in the opposite direction to when the opening and closing execution mode began, so that the first light-emitting surface 302 faces the front of the pachinko machine 10. In the opening and closing execution mode, the movable object is configured to emit light differently from game states other than the opening and closing execution mode, which increases the interest of the presentation during the opening and closing execution mode.

26, the first light-emitting surface 302 of the light-emitting substrate 301 is mounted with a bypass capacitor 328 and small chip resistors 331 to 335. Like the bypass capacitor 85 in the first embodiment, the bypass capacitor 328 is a substantially rectangular parallelepiped. Like the bypass capacitor 85 in the first embodiment, the bypass capacitor 328 is a small chip component having a dimension of 0.1 mm or more and 0.9 mm or less in the longitudinal direction (hereinafter also referred to as the "longitudinal direction of the bypass capacitor 328") along a plane perpendicular to the thickness direction of the bypass capacitor 328. The bypass capacitor 328 is a small chip component having a dimension of approximately 0.6 mm in the longitudinal direction along a plane perpendicular to the thickness direction, and a dimension of approximately 0.3 mm in the transverse direction (hereinafter also referred to as the "transverse direction") along a plane perpendicular to the thickness direction. By making the longitudinal dimension of the bypass capacitor 328 0.7 mm or less, the area occupied by the bypass capacitor 328 on the light emitting substrate 301 can be further reduced. By making the longitudinal dimension of the bypass capacitor 328 0.4 mm or more, the mechanical strength of the connection point between the bypass capacitor 328 and the light emitting substrate 301 and the mechanical strength of the bypass capacitor 328 itself can be increased, and the possibility of the connection point being damaged can be reduced, and the possibility of the bypass capacitor 328 itself being damaged can be reduced. In addition, by making the longitudinal dimension of the bypass capacitor 328 0.4 mm or more, the accuracy of confirmation when visually checking whether or not the bypass capacitor 328 is missing from mounting can be improved. Note that the longitudinal dimension of the bypass capacitor 328 may be smaller than 0.6 mm (for example, 0.4 mm), the lateral dimension of the bypass capacitor 328 may be smaller than 0.3 mm (for example, 0.2 mm), or the thickness dimension may be smaller than 0.3 mm (for example, 0.2 mm).

Like the small chip resistor 87 in the first embodiment, the small chip resistors 331 to 335 are approximately rectangular parallelepipeds. Like the small chip resistor 87 in the first embodiment, the small chip resistors 331 to 335 are small chip components with a dimension of 0.1 mm or more and 0.9 mm or less in the longitudinal direction (hereinafter also referred to as the "longitudinal direction of the small chip resistors 331 to 335") along a plane perpendicular to the thickness direction of the small chip resistors 331 to 335. The small chip resistors 331 to 335 are small chip components with a dimension of approximately 0.6 mm in the longitudinal direction along a plane perpendicular to the thickness direction, and a dimension of approximately 0.3 mm in the short direction (hereinafter also referred to as the "short direction") and the thickness direction of the small chip resistors 331 to 335. By making the longitudinal dimension of the small chip resistors 331-335 0.7 mm or less, the area occupied by the small chip resistors 331-335 on the light emitting substrate 301 can be further reduced. By making the longitudinal dimension of the small chip resistors 331-335 0.4 mm or more, the mechanical strength of the connection points between the small chip resistors 331-335 and the light emitting substrate 301 and the mechanical strength of the small chip resistors 331-335 themselves can be increased, and the possibility of the connection points being damaged can be reduced, and the possibility of the small chip resistors 331-335 themselves being damaged can be reduced. In addition, by making the longitudinal dimension of the small chip resistors 331-335 0.4 mm or more, the accuracy of confirmation can be improved when visually checking whether or not the small chip resistors 331-335 are missing from mounting. The longitudinal dimension of the small chip resistors 331 to 335 may be smaller than 0.6 mm (for example, 0.4 mm), the lateral dimension of the small chip resistors 331 to 335 may be smaller than 0.3 mm (for example, 0.2 mm), or the thickness dimension may be smaller than 0.3 mm (for example, 0.2 mm).

In the light emitting substrate 301, the small chip components (bypass capacitor 328 and small chip resistors 331 to 335) are concentrated on the first light emitting surface 302 side and are not mounted on the second light emitting surface 303 side. Therefore, by handling the light emitting substrate 301 so that the stress acting on the first light emitting surface 302 side of the light emitting substrate 301 is smaller than the stress acting on the second light emitting surface 303 side, the possibility of damage to the connection points between the small chip components and the light emitting substrate 301 can be reduced, and the possibility of damage to the small chip components themselves can be reduced. For example, when dividing an assembly substrate (not shown) including a plurality of light emitting substrates 301 to extract the light emitting substrates 301, the assembly substrate can be divided in such a manner that the first light emitting surface 302 side has a valley shape (concave), thereby preventing tensile stress from acting on the connection points between the small chip components and the light emitting substrate 301. This prevents damage to the connection points between the small chip components and the light emitting substrate 301, and prevents damage to the small chip components themselves.

As shown in FIG. 27, chip resistors 336-346 that limit the current flowing through the LED chips 315-325 are mounted on the second light-emitting surface 303 of the light-emitting substrate 301. The provision of the chip resistors 336-346 allows the LED chips 315-325 to be driven at a current equal to or less than the allowable current. The chip resistors 336-346 are substantially rectangular parallelepipeds, and each has a pair of first and second metal electrodes (not shown) at both ends in the longitudinal direction. The chip resistors 336-346 are surface-mount resistors with a longitudinal dimension of 1 mm and a transverse dimension and thickness dimension of 0.5 mm. The longitudinal dimension of the chip resistors 336-346 along a plane perpendicular to the thickness direction (the longitudinal dimension of the chip resistors 336-346, which is 1 mm) is greater than 0.9 mm, and the chip resistors 336-346 are not small chip components. The longitudinal dimension of the chip resistors 336 to 346 may be greater than 1 mm (e.g., 1.6 mm), the transverse dimension may be greater than 0.5 mm (e.g., 0.8 mm), and the thickness dimension may be greater than 0.5 mm (e.g., 0.8 mm).

The driving power of the second LED driver 326 is supplied from the sound light emission control device 81 to the power terminal 348 of the second LED driver 326 via the connector 327. A bypass capacitor 352 for absorbing noise components contained in the driving power of the second LED driver 326 is mounted on the second light emitting surface 303 of the light emitting substrate 301. The bypass capacitor 352 is an approximately rectangular parallelepiped, and has a pair of metallic first electrodes 352a and second electrodes 352b at both ends in the longitudinal direction. The bypass capacitor 352 is a surface mount type capacitor with a longitudinal dimension of 1 mm, and a lateral dimension and a thickness dimension of 0.5 mm. The longitudinal dimension of the bypass capacitor 352 along a plane perpendicular to the thickness direction (1 mm, which is the longitudinal dimension of the bypass capacitor 352) is greater than 0.9 mm, and the bypass capacitor 352 is not a small chip component. The longitudinal dimension of the bypass capacitor 352 may be greater than 1 mm (e.g., 1.6 mm), the transverse dimension may be greater than 0.5 mm (e.g., 0.8 mm), and the thickness dimension may be greater than 0.5 mm (e.g., 0.8 mm).

The first electrode 352a of the bypass capacitor 352 is electrically connected to the GND terminal 349 and the GND plane layer (not shown) of the second LED driver 326, and the second electrode 352b is electrically connected to the power terminal 348 and the power plane layer (not shown) of the second LED driver 326. By disposing the bypass capacitor 352 between the power terminal 348 and the power plane layer, the effect of noise components contained in the driving power supplied from the audio light emission control device 81 to the second LED driver 326 on the second LED driver 326 is reduced.

The chip resistor 340 on the second light-emitting surface 303 of the light-emitting substrate 301 is disposed in an area including the driver back side corresponding area 353 on the first light-emitting surface 302. The driver back side corresponding area 353 is an area of the second light-emitting surface 303 located on the back side of the area where the first LED driver 314 (FIG. 26) is mounted on the first light-emitting surface 302 (FIG. 26) and the area where the pad (or pad) corresponding to the terminal of the first LED driver 314 is provided, and an area within 1 mm from the area of the second light-emitting surface 303. As already explained, the chip resistor 340 is not a small chip component. The connection point between the chip resistor 340 and the light-emitting substrate 301 has a higher mechanical strength than the connection point between the small chip component and the light-emitting substrate 301. In addition, the chip resistor 340 itself has a higher mechanical strength than the small chip component itself. In the second light-emitting surface 303, by arranging the chip resistor 340 in an area including the driver back-side corresponding area 353, the LED chip 319 can be arranged near the driver back-side corresponding area 353. Meanwhile, as shown in FIG. 26, the small chip components (bypass capacitor 328 and small chip resistors 331 to 335) in the first light-emitting surface 302 of the light-emitting substrate 301 are arranged to avoid the driver back-side corresponding area 354. The driver back-side corresponding area 354 is an area of the first light-emitting surface 302 located on the back side of the area in which the second LED driver 326 (FIG. 27) is mounted on the second light-emitting surface 303 (FIG. 27) and an area located within 1 mm away from the area of the first light-emitting surface 302. Since no small chip components are mounted in the area of the first light-emitting surface 302 located behind the area where the second LED driver 326 is mounted on the second light-emitting surface 303 and the area where the pads corresponding to the terminals of the second LED driver 326 are provided, the effect of thermal stress on the small chip components that may act on the light-emitting substrate 301 due to heat generated by the second LED driver 326 is reduced. Since the small chip components are arranged to avoid the driver back-side corresponding area 354, it is possible to prevent damage to the connection points between the small chip components and the light-emitting substrate 301 due to the influence of thermal stress caused by heat generated by the second LED driver 326, and also to prevent damage to the small chip components themselves.

27, the chip resistor 343 on the second light-emitting surface 303 of the light-emitting substrate 301 is disposed in an area including the LED back-side corresponding area 355 on the first light-emitting surface 302. The LED back-side corresponding area 355 is an area of the second light-emitting surface 303 located on the back side of the area where the LED chips 310, 311 (FIG. 26) are mounted on the first light-emitting surface 302 (FIG. 26) and an area within a distance of 1 mm from the outer edge of the area of the second light-emitting surface 303. By disposing the chip resistor 343 in an area including the LED back-side corresponding area 355 on the second light-emitting surface 303, the LED chip 322 can be disposed near the LED back-side corresponding area 355. On the other hand, as shown in FIG. 26, the small chip components (bypass capacitor 328 and small chip resistors 331-335) on the first light-emitting surface 302 of the light-emitting substrate 301 are disposed to avoid the LED back-side corresponding areas 361-371. The LED backside corresponding regions 361-371 are the region of the first light-emitting surface 302 located on the back side of the region where the LED chips 315-325 (FIG. 27) are mounted on the second light-emitting surface 303 (FIG. 27) and the region that is within 1 mm from the outer edge of the region of the first light-emitting surface 302. Since no small chip components are mounted in the region of the first light-emitting surface 302 located on the back side of the region where the LED chips 315-325 are mounted on the second light-emitting surface 303, the influence of thermal stress that may act on the light-emitting substrate 301 due to heat generated by the LED chips 315-325 on the small chip components is reduced. Since the small chip components are arranged to avoid the LED backside corresponding regions 361-371, it is possible to prevent the connection between the small chip components and the light-emitting substrate 301 from being damaged due to the influence of thermal stress caused by heat generated by the LED chips 315-325, and it is also possible to prevent the small chip components themselves from being damaged.

As shown in FIG. 26, an LED chip 310 is mounted near the center of the first light-emitting surface 302 of the light-emitting substrate 301. The longitudinal dimension of the LED chip 310 along a plane perpendicular to the thickness direction is greater than 0.9 mm, and the LED chip 310 is not a small chip component. As shown in FIG. 26, the LED chip 310 is mounted in an area including the LED backside corresponding area 368 on the first light-emitting surface 302. The LED chip 310 is mounted in an area of the LED backside corresponding area 368 including an area of the first light-emitting surface 302 located on the back side of the area on the second light-emitting surface 303 (FIG. 27) where the LED chip 322 (FIG. 27) is mounted. On the first light-emitting surface 302 of the light-emitting substrate 301, some of the electronic components that are not small chip components (LED chip 310) are mounted in an area that includes the area of the first light-emitting surface 302 located on the back side of the area on the second light-emitting surface 303 (Figure 27) where the LED chip 322 (Figure 27) is mounted, thereby ensuring a large area on the first light-emitting surface 302 where electronic components other than small chip components can be mounted.

In a light emitting substrate 301 in which a part of an electronic component that is not a small chip component (LED chip 310) is mounted in an area including an area of the first light emitting surface 302 located on the back side of the area on the second light emitting surface 303 (Fig. 27) where the LED chip 322 (Fig. 27) is mounted, the small chip component is arranged to avoid the LED back side corresponding areas 361-371. This reduces the possibility that the connection points between the small chip component and the light emitting substrate 301 and the small chip component itself will be damaged due to the influence of thermal stress.

27, the chip resistors 341 on the second light-emitting surface 303 of the light-emitting substrate 301 are arranged in an area including the connector peripheral region 372. The connector peripheral region 372 is an area less than 5 mm from the outer edge of the connector 327. By arranging the chip resistors 341 in an area including the connector peripheral region 372 on the second light-emitting surface 303, the LED chips 315 to 325 can be widely distributed on the light-emitting substrate 301 and the light-emitting area of the second light-emitting surface 303 can be expanded, compared to the case where the chip resistors 341 are arranged avoiding the connector peripheral region 372. On the other hand, as shown in FIG. 26, the small chip components (bypass capacitors 328 and small chip resistors 331 to 335) on the first light-emitting surface 302 of the light-emitting substrate 301 are arranged avoiding the connector back side corresponding region 373. The connector back side corresponding region 373 is a region of the first light emitting surface 302 located on the back side of the region where the connector 327 is mounted on the second light emitting surface 303 (FIG. 27) and a region that is less than 5 mm away from the outer edge of the region of the first light emitting surface 302. Since no small chip components are mounted in the region of the first light emitting surface 302 located on the back side of the region where the connector 327 is mounted on the second light emitting surface 303, the effect of stress that may act on the light emitting substrate 301 when attaching and detaching the harness to the connector 327 on the small chip components is reduced. Since the small chip components are arranged to avoid the connector back side corresponding region 373, it is possible to reduce stress that may act on the connection between the small chip components and the light emitting substrate 301 when attaching and detaching the harness (not shown) to the connector 327, and it is also possible to reduce stress acting on the small chip components themselves. Therefore, it is possible to prevent damage to the connection between the small chip components and the light emitting substrate 301 when attaching and detaching the harness to the connector 327, and it is also possible to prevent damage to the small chip components themselves.

As shown in FIG. 27, the chip resistors 336 on the second light-emitting surface 303 of the light-emitting substrate 301 are arranged in an area including the substrate outer edge region 374 on the second light-emitting surface 303 side. The substrate outer edge region 374 on the second light-emitting surface 303 side is an area less than 10 mm from the outer edge of the light-emitting substrate 301 on the second light-emitting surface 303. By arranging the chip resistors 336 in an area including the substrate outer edge region 374 on the second light-emitting surface 303, the LED chips 315 to 325 can be widely distributed on the light-emitting substrate 301 compared to the case where the chip resistors 336 are arranged to avoid the substrate outer edge region 374. On the other hand, as shown in FIG. 26, the small chip components (bypass capacitors 328 and small chip resistors 331 to 335) on the first light-emitting surface 302 of the light-emitting substrate 301 are arranged to avoid the substrate outer edge region 375 on the first light-emitting surface 302 side. The substrate outer edge region 375 on the first light-emitting surface 302 side is a region less than 10 mm from the outer edge of the light-emitting substrate 301 on the first light-emitting surface 302. By arranging the small chip components on the first light-emitting surface 302 while avoiding the substrate outer edge region 375, it is possible to prevent the connection points between the small chip components and the light-emitting substrate 301 from being damaged due to the operator's hands touching the small chip components when handling the light-emitting substrate 301, and also to prevent the small chip components themselves from being damaged. In addition, when an assembly substrate including a plurality of light-emitting substrates 301 is divided to remove the light-emitting substrates 301, it is possible to reduce the stress that may act on the connection points between the small chip components and the light-emitting substrate 301 when the assembly substrate is divided, and also to reduce the stress that acts on the small chip components themselves. Therefore, it is possible to prevent the connection points between the small chip components and the light-emitting substrate 301 from being damaged when the assembly substrate is divided, and it is possible to prevent the small chip components themselves from being damaged.

26 and 27, the light emitting substrate 301 has fixing through holes 301a and 301b that penetrate the light emitting substrate 301 in the thickness direction and allow the light emitting substrate 301 to be fixed to a substrate case body (not shown) with screws. As shown in FIG. 27, the chip resistors 346 on the second light emitting surface 303 of the light emitting substrate 301 are arranged in an area including the fixing through hole peripheral area 376. The fixing through hole peripheral area 376 is an area less than 5 mm from the outer edge of the fixing through hole 301b. By arranging the chip resistors 346 in an area including the fixing through hole peripheral area 376 on the second light emitting surface 303, the LED chips 315 to 325 can be widely distributed on the light emitting substrate 301 compared to the case where the chip resistors 346 are arranged while avoiding the fixing through hole peripheral area 376. On the other hand, as shown in FIG. 26, the small chip components (bypass capacitor 328 and small chip resistors 331 to 335) on the first light-emitting surface 302 of the light-emitting substrate 301 are arranged to avoid the fixed through-hole peripheral regions 377 and 378. The fixed through-hole peripheral regions 377 and 378 are regions on the first light-emitting surface 302 that are less than 5 mm from the outer edges of the fixed through-holes 301a and 301b. By arranging the small chip components on the first light-emitting surface 302 to avoid the fixed through-hole peripheral regions 377 and 378, when the light-emitting substrate 301 is fixed to the substrate case body (not shown), it is possible to reduce the stress that may act on the connection points between the small chip components and the light-emitting substrate 301, and to reduce the stress that acts on the small chip components themselves. Therefore, when the light-emitting substrate 301 is fixed to the substrate case body, it is possible to prevent the connection points between the small chip components and the light-emitting substrate 301 from being damaged, and it is possible to prevent the small chip components themselves from being damaged.

27, the longitudinal dimension of the LED chips 317, 324 along a plane perpendicular to the thickness direction is greater than 0.9 mm, and the LED chips 317, 324 are not small chip components. The longitudinal dimension of the chip resistors 338, 345 along a plane perpendicular to the thickness direction is greater than 0.9 mm, and the chip resistors 338, 345 are not small chip components. In the light-emitting substrate 301, the LED chips 317, 324 are mounted on the light-emitting substrate 301 in such a manner that the longitudinal direction along a plane perpendicular to the thickness direction of the LED chips 317, 324 is parallel to the short axis direction SDA perpendicular to the long axis direction LDA of the light-emitting substrate 301. The chip resistors 338, 345 are mounted on the light-emitting substrate 301 in such a manner that the longitudinal direction along a plane perpendicular to the thickness direction of the chip resistors 338, 345 is parallel to the short axis direction SDA perpendicular to the long axis direction LDA of the light-emitting substrate 301. On the other hand, as shown in FIG. 26, in the light emitting substrate 301, the small chip components (bypass capacitor 328 and small chip resistors 331-335) are mounted on the light emitting substrate 301 in such a manner that the longitudinal direction along a plane perpendicular to the thickness direction of the small chip components is parallel to the long axis direction LDA of the light emitting substrate 301. As a result, compared to when the longitudinal direction of the small chip components is parallel to the short axis direction SDA perpendicular to the long axis direction LDA, the maximum value of the stress that can act on the connection points between the small chip components and the light emitting substrate 301 when the light emitting substrate 301 is distorted is reduced, and the maximum value of the stress that can act on the small chip components themselves is reduced.

The mechanical strength of the connection between the small chip component and the light emitting substrate 301 is lower than the mechanical strength of the connection between the electronic component larger than the small chip component and the light emitting substrate 301. Also, the mechanical strength of the small chip component itself is lower than the mechanical strength of the electronic component itself that is larger than the small chip component. In a configuration in which some of the electronic components larger than the small chip components are mounted on the light emitting substrate 301 in a manner in which the longitudinal direction of the electronic component is not parallel to the longitudinal axis direction LDA of the light emitting substrate 301, the small chip components are mounted on the light emitting substrate 301 in a manner in which the longitudinal direction of the small chip components is parallel to the longitudinal axis direction LDA of the light emitting substrate 301. This protects the connection between the small chip components and the light emitting substrate 301 and the small chip components themselves.

The present embodiment described above provides the following excellent advantages:

In a configuration in which the chip resistor 340 is arranged in an area including the driver back side corresponding area 353 on the second light-emitting surface 303 of the light-emitting substrate 301, the small chip components (bypass capacitor 328 and small chip resistors 331 to 335) on the first light-emitting surface 302 are arranged to avoid the driver back side corresponding area 354. The driver back side corresponding area 354 is an area of the first light-emitting surface 302 located on the back side of the area in which the second LED driver 326 is mounted on the second light-emitting surface 303 and the area in which the pads corresponding to the terminals of the second LED driver 326 are provided, and an area within 1 mm from the area of the first light-emitting surface 302. Since the small chip components are not mounted on the area of the first light-emitting surface 302 located on the back side of the area in which the second LED driver 326 is mounted on the second light-emitting surface 303 and the area in which the pads corresponding to the terminals of the second LED driver 326 are provided, the effect of thermal stress that may act on the light-emitting substrate 301 due to heat generation by the second LED driver 326 on the small chip components is reduced. By arranging the small chip components to avoid the driver backside corresponding area 354, it is possible to prevent damage to the connection points between the small chip components and the light emitting substrate 301 due to the influence of thermal stress caused by heat generated by the second LED driver 326, and also to prevent damage to the small chip components themselves.

In a configuration in which the chip resistor 343 on the second light-emitting surface 303 of the light-emitting substrate 301 is disposed in an area including the LED backside corresponding area 355, the small chip components on the first light-emitting surface 302 of the light-emitting substrate 301 are disposed to avoid the LED backside corresponding areas 361-371. The LED backside corresponding areas 361-371 are an area of the first light-emitting surface 302 located on the back side of the area in which the LED chips 315-325 are mounted on the second light-emitting surface 303 and an area within a distance of 1 mm from the outer edge of the area of the first light-emitting surface 302. Since the small chip components are not mounted in the area of the first light-emitting surface 302 located on the back side of the area in which the LED chips 315-325 are mounted on the second light-emitting surface 303, the effect of thermal stress on the small chip components that may act on the light-emitting substrate 301 due to heat generation from the LED chips 315-325 is reduced. By arranging the small chip components to avoid the LED backside corresponding areas 361-371, it is possible to prevent damage to the connection points between the small chip components and the light emitting substrate 301 due to the influence of thermal stress caused by heat generation from the LED chips 315-325, and also to prevent damage to the small chip components themselves.

In a light emitting substrate 301 in which a part of an electronic component that is not a small chip component (LED chip 310) is mounted in an area including an area of the first light emitting surface 302 located on the back side of the area on the second light emitting surface 303 (Fig. 27) where the LED chip 322 (Fig. 27) is mounted, the small chip component is arranged to avoid the LED back side corresponding areas 361-371. This reduces the possibility that the connection points between the small chip component and the light emitting substrate 301 and the small chip component itself will be damaged due to the influence of thermal stress.

In a configuration in which the chip resistor 341 on the second light-emitting surface 303 of the light-emitting substrate 301 is arranged in a region including the connector peripheral region 372, the small chip components on the first light-emitting surface 302 of the light-emitting substrate 301 are arranged to avoid the connector back side corresponding region 373. The connector back side corresponding region 373 is a region of the first light-emitting surface 302 located on the back side of the region in which the connector 327 is mounted on the second light-emitting surface 303 and a region that is less than 5 mm away from the outer edge of the region of the first light-emitting surface 302. Since the small chip components are not mounted in the region of the first light-emitting surface 302 located on the back side of the region in which the connector 327 is mounted on the second light-emitting surface 303, the effect of stress that may act on the light-emitting substrate 301 on the small chip components when the harness is attached to or detached from the connector 327 is reduced. By arranging the small chip components to avoid the connector back side corresponding area 373, it is possible to reduce the stress that may act on the connection between the small chip components and the light emitting substrate 301 when attaching or detaching the harness (not shown) to the connector 327, and also to reduce the stress that acts on the small chip components themselves. Therefore, it is possible to prevent damage to the connection between the small chip components and the light emitting substrate 301 when attaching or detaching the harness to the connector 327, and it is also possible to prevent damage to the small chip components themselves.

In a configuration in which the chip resistor 336 on the second light-emitting surface 303 of the light-emitting substrate 301 is disposed in an area including the substrate outer edge region 374, the small chip components on the first light-emitting surface 302 of the light-emitting substrate 301 are disposed to avoid the substrate outer edge region 375 on the first light-emitting surface 302 side. This prevents the connection points between the small chip components and the light-emitting substrate 301 from being damaged due to the operator's hand touching the small chip components when handling the light-emitting substrate 301, and prevents the small chip components themselves from being damaged. In addition, when a collective substrate including a plurality of light-emitting substrates 301 is divided to remove the light-emitting substrates 301, the stress that may act on the connection points between the small chip components and the light-emitting substrate 301 when the collective substrate is divided can be reduced, and the stress acting on the small chip components themselves can be reduced. Therefore, when the collective substrate is divided, the connection points between the small chip components and the light-emitting substrate 301 can be prevented from being damaged, and the small chip components themselves can be prevented from being damaged.

In a configuration in which the chip resistor 346 on the second light-emitting surface 303 of the light-emitting substrate 301 is disposed in an area including the peripheral area 376 of the fixed through hole, the small chip components on the first light-emitting surface 302 of the light-emitting substrate 301 are disposed to avoid the peripheral areas 377, 378 of the fixed through hole. This makes it possible to reduce stress that may act on the connection points between the small chip components and the light-emitting substrate 301 when the light-emitting substrate 301 is fixed to the substrate case body, and also to reduce stress acting on the small chip components themselves. Therefore, when the light-emitting substrate 301 is fixed to the substrate case body, it is possible to prevent damage to the connection points between the small chip components and the light-emitting substrate 301, and also to prevent damage to the small chip components themselves.

In a configuration in which some of the electronic components larger than the small chip components are mounted on the light emitting substrate 301 in a manner in which the longitudinal direction of the electronic components is not parallel to the long axis direction LDA of the light emitting substrate 301, the small chip components (bypass capacitor 328 and small chip resistors 331-335) are mounted on the light emitting substrate 301 in a manner in which the longitudinal direction along a plane perpendicular to the thickness direction of the small chip components is parallel to the long axis direction LDA of the light emitting substrate 301. As a result, compared to a case in which the longitudinal direction of the small chip components is parallel to the short axis direction SDA perpendicular to the long axis direction LDA, the maximum value of the stress that can act on the connection point between the small chip components and the light emitting substrate 301 when distortion occurs in the light emitting substrate 301 is reduced, and the maximum value of the stress that can act on the small chip components themselves is reduced.

In addition, the driver back side corresponding region 354 in which the small chip components (bypass capacitor 328 and small chip resistors 331 to 335) are not mounted on the first light-emitting surface 302 of the light-emitting substrate 301 is not limited to the region of the first light-emitting surface 302 located on the back side of the region in which the second LED driver 326 (FIG. 27) is mounted and the region in which the pads corresponding to the terminals of the second LED driver 326 are provided on the second light-emitting surface 303 (FIG. 27) and the region within 1 mm from the region of the first light-emitting surface 302. The driver back side corresponding region 354 may be the region of the first light-emitting surface 302 located on the back side of the region in which the second LED driver 326 is mounted and the region in which the pads corresponding to the terminals of the second LED driver 326 are provided on the second light-emitting surface 303 and the region within 2 mm from the region of the first light-emitting surface 302. This further reduces the effect of thermal stress on the small chip components that may act on the light-emitting substrate 301 due to heat generated by the second LED driver 326. Therefore, it is possible to reduce the possibility that the connection between the small chip component and the light emitting substrate 301 will be damaged due to the influence of thermal stress caused by the heat generated by the second LED driver 326, and the possibility that the small chip component itself will be damaged. In addition, the driver back side corresponding area 354 may be an area of the first light emitting surface 302 located on the back side of the area where the second LED driver 326 is mounted on the second light emitting surface 303 and the area where the pads corresponding to the terminals of the second LED driver 326 are provided, and an area within 0.5 mm away from the area of the first light emitting surface 302. This makes it possible to secure a large area on the first light emitting surface 302 of the light emitting substrate 301 where small chip components can be mounted, while reducing the influence of thermal stress that may act on the light emitting substrate 301 due to the heat generated by the second LED driver 326 on the small chip components.

- The LED backside corresponding regions 361-371 in the first light-emitting surface 302 of the light-emitting substrate 301 where small chip components (bypass capacitor 328 and small chip resistors 331-335) are not mounted are not limited to the region of the first light-emitting surface 302 located on the back side of the region in which the LED chips 315-325 (FIG. 27) are mounted in the second light-emitting surface 303 (FIG. 27) and the region within 1 mm from the outer edge of the region of the first light-emitting surface 302. The LED backside corresponding regions 361-371 may be the region of the first light-emitting surface 302 located on the back side of the region in which the LED chips 315-325 are mounted in the second light-emitting surface 303 and the region within 2 mm from the outer edge of the region of the first light-emitting surface 302. This further reduces the effect of thermal stress on the small chip components that may act on the light-emitting substrate 301 due to heat generated by the LED chips 315-325. Therefore, it is possible to reduce the possibility that the connection between the small chip parts and the light emitting substrate 301 will be damaged due to the influence of thermal stress caused by the heat generated by the LED chips 315-325, and also to reduce the possibility that the small chip parts themselves will be damaged. In addition, the LED back side corresponding areas 361-371 may be an area of the first light emitting surface 302 located on the back side of the area in which the LED chips 315-325 are mounted on the second light emitting surface 303, and an area within a distance of 0.5 mm from the outer edge of the area of the first light emitting surface 302. This makes it possible to ensure a large area on the first light emitting surface 302 of the light emitting substrate 301 where small chip parts can be mounted, while reducing the influence of thermal stress that may act on the light emitting substrate 301 due to the heat generated by the LED chips 315-325 on the small chip parts.

The connector back side corresponding region 373 on the first light-emitting surface 302 of the light-emitting substrate 301 where small chip components (bypass capacitor 328 and small chip resistors 331-335) are not mounted is not limited to the region of the first light-emitting surface 302 located on the back side of the region where the connector 327 is mounted on the second light-emitting surface 303 (FIG. 27) and the region that is less than 5 mm away from the outer edge of the region of the first light-emitting surface 302. The connector back side corresponding region 373 may be the region of the first light-emitting surface 302 located on the back side of the region where the connector 327 is mounted on the second light-emitting surface 303 and the region that is less than 7 mm away from the outer edge of the region of the first light-emitting surface 302. This can reduce stress that may act on the connection between the small chip components and the light-emitting substrate 301 when attaching and detaching the harness to the connector 327, and can also reduce stress acting on the small chip components themselves. Therefore, the possibility of damage to the connection between the small chip component and the light emitting substrate 301 when attaching or detaching the harness to the connector 327 can be reduced, and the possibility of damage to the small chip component itself can be reduced. In addition, the connector back side corresponding area 373 may be an area of the first light emitting surface 302 located on the back side of the area where the connector 327 is mounted on the second light emitting surface 303, and an area that is less than 4 mm away from the outer edge of the area of the first light emitting surface 302. This reduces the stress acting on the connection between the small chip component and the light emitting substrate 301 and the small chip component itself when attaching or detaching the harness to the connector 327, while ensuring a large area on the first light emitting surface 302 of the light emitting substrate 301 where the small chip component can be mounted.

・The fixed through hole peripheral areas 377, 378 on the first light-emitting surface 302 of the light-emitting substrate 301 where the small chip components (bypass capacitor 328 and small chip resistors 331-335) are not mounted are not limited to areas less than 5 mm from the outer edge of the fixed through holes 301a, 301b on the first light-emitting surface 302. The fixed through hole peripheral areas 377, 378 may be areas less than 7 mm from the outer edge of the fixed through holes 301a, 301b on the first light-emitting surface 302. This reduces the stress that may act on the connection points between the small chip components and the light-emitting substrate 301 when the light-emitting substrate 301 is fixed to the substrate case body (not shown), and reduces the stress acting on the small chip components themselves. Therefore, when the light-emitting substrate 301 is fixed to the substrate case body, the possibility of damage to the connection points between the small chip components and the light-emitting substrate 301 can be reduced, and the possibility of damage to the small chip components themselves can be reduced. The peripheral areas 377, 378 of the fixing through holes may be areas less than 4 mm from the outer edges of the fixing through holes 301a, 301b on the first light-emitting surface 302. This reduces the stress acting on the connection points between the small chip components and the light-emitting substrate 301 and on the small chip components themselves when the light-emitting substrate 301 is fixed to the substrate case body (not shown), while ensuring a large area on the first light-emitting surface 302 of the light-emitting substrate 301 where small chip components can be mounted.

・The substrate outer edge region 375 on the first light-emitting surface 302 side where the small chip components (bypass capacitor 328 and small chip resistors 331 to 335) are not mounted on the first light-emitting surface 302 of the light-emitting substrate 301 is not limited to an area less than 10 mm from the outer edge of the light-emitting substrate 301 on the first light-emitting surface 302. The substrate outer edge region 375 on the first light-emitting surface 302 side may be an area less than 12 mm from the outer edge of the light-emitting substrate 301 on the first light-emitting surface 302. This reduces the possibility that the connection between the small chip components and the light-emitting substrate 301 will be damaged due to the operator's hands touching the small chip components when handling the light-emitting substrate 301, and also reduces the possibility that the small chip components themselves will be damaged. In addition, when a collective substrate including a plurality of light-emitting substrates 301 is divided to remove the light-emitting substrates 301, the stress that may act on the connection between the small chip components and the light-emitting substrate 301 when the collective substrate is divided can be reduced, and the stress acting on the small chip components themselves can be reduced. In addition, the substrate outer edge region 375 on the first light-emitting surface 302 side may be an area less than 8 mm from the outer edge of the light-emitting substrate 301 on the first light-emitting surface 302. This reduces the possibility of damage to the connection between the small chip component and the light-emitting substrate 301 and the possibility of damage to the small chip component itself, while ensuring a large area on the first light-emitting surface 302 of the light-emitting substrate 301 where the small chip component can be mounted.

Fourth Embodiment
This embodiment differs from the third embodiment in that a bypass capacitor for absorbing noise components contained in the driving power supply of the second LED driver 326 mounted on the second light-emitting surface 303 side of the light-emitting substrate 301 is mounted on the first light-emitting surface 302 side. The following describes the configuration different from the third embodiment. Note that the description of the same configuration as the third embodiment will basically be omitted.

Figure 28(a) is a plan view of the first light-emitting surface 302 of the light-emitting substrate 301 in this embodiment. As shown in Figure 28(a), a bypass capacitor 381 is mounted on the first light-emitting surface 302 side of the light-emitting substrate 301 to absorb noise components contained in the driving power supply of the second LED driver 326 (Figure 29(a)) mounted on the second light-emitting surface 303 side (Figure 29(a)). Figure 28(b) is a plan view of the first light-emitting surface 302 of the light-emitting substrate 301, showing an enlarged peripheral area 388 of the bypass capacitor 381.

As shown in FIG. 28B, the bypass capacitor 381 is a substantially rectangular parallelepiped, and has a pair of metallic first and second electrodes 381a and 381b at both ends in the longitudinal direction. As with the bypass capacitor 85 in the first embodiment, the bypass capacitor 381 is a small chip component having a longitudinal dimension (hereinafter also referred to as the "longitudinal direction of the bypass capacitor 381") of 0.1 mm or more and 0.9 mm or less along a plane perpendicular to the thickness direction of the bypass capacitor 381. The bypass capacitor 381 is a small chip component having a longitudinal dimension of approximately 0.6 mm along a plane perpendicular to the thickness direction, and a transverse dimension (hereinafter also referred to as the "transverse direction") along a plane perpendicular to the thickness direction and a thickness direction dimension of approximately 0.3 mm. By having the longitudinal dimension of the bypass capacitor 381 be 0.7 mm or less, the area occupied by the bypass capacitor 381 on the light emitting substrate 301 can be further reduced. By making the longitudinal dimension of the bypass capacitor 381 0.4 mm or more, the mechanical strength of the connection point between the bypass capacitor 381 and the light emitting substrate 301 and the mechanical strength of the bypass capacitor 381 itself can be increased, and the possibility of the connection point being damaged can be reduced, and the possibility of the bypass capacitor 381 itself being damaged can be reduced. In addition, the accuracy of checking whether or not the bypass capacitor 381 is missing from mounting can be improved when checking visually. Note that the longitudinal dimension of the bypass capacitor 381 may be smaller than 0.6 mm (e.g., 0.4 mm), the transverse dimension of the bypass capacitor 381 may be smaller than 0.3 mm (e.g., 0.2 mm), or the thickness dimension may be smaller than 0.3 mm (e.g., 0.2 mm).

On the first light-emitting surface 302 of the light-emitting substrate 301, a first pad 382a (or a first pad) made of metal (specifically, copper) corresponding to the first electrode 381a in the bypass capacitor 381 and a second pad 382b (or a second pad) made of metal (specifically, copper) corresponding to the second electrode 381b are provided. The first pad 382a and the second pad 382b form a pair. The first electrode 381a is electrically connected to the first pad 382a, and the second electrode 381b is electrically connected to the second pad 382b.

Figure 29 (a) is a plan view of the second light-emitting surface 303 of the light-emitting substrate 301. As already described in the third embodiment, the second LED driver 326 has a power terminal 348 and a GND terminal 349. Figure 29 (b) is a plan view of the second light-emitting surface 303 of the light-emitting substrate 301, showing an enlarged peripheral area 389 of the power terminal 348 and the GND terminal 349. As shown in FIG. 28(b) and FIG. 29(b), the light emitting substrate 301 is provided with a first through hole 383 that electrically connects the first pad 382a (FIG. 28(b)) corresponding to the first electrode 381a of the bypass capacitor 381 to the GND terminal 349 (FIG. 29(b)) of the second LED driver 326, and a second through hole 384 that electrically connects the second pad 382b (FIG. 28(b)) corresponding to the second electrode 381b of the bypass capacitor 381 to the power terminal 348 (FIG. 29(b)) of the second LED driver 326. These through holes 383, 384 are formed by penetrating the light emitting substrate 301 in the thickness direction, and the inner circumference of these through holes 383, 384 is plated with a metal such as copper.

As shown in FIG. 28(b), the first light-emitting surface 302 of the light-emitting substrate 301 is provided with a first wiring pattern 386a that electrically connects the first pad 382a to the GND via hole 385 (ground via hole or ground via hole) provided in the light-emitting substrate 301, and a second wiring pattern 386b that electrically connects the first pad 382a to the first through hole 383. The first pad 382a corresponding to the first electrode 381a of the bypass capacitor 381 is electrically connected to the GND plane layer (not shown) via the first wiring pattern 386a and the GND via hole 385, and is electrically connected to the GND terminal 349 (FIG. 29(b)) of the second LED driver 326 via the second wiring pattern 386b and the first through hole 383.

The first light-emitting surface 302 of the light-emitting substrate 301 is provided with a third wiring pattern 386c that electrically connects the second pad 382b to the power supply via hole 387 provided in the light-emitting substrate 301, and a fourth wiring pattern 386d that electrically connects the second pad 382b to the second through hole 384. The second pad 382b corresponding to the second electrode 381b of the bypass capacitor 381 is electrically connected to the power supply plane layer (not shown) via the third wiring pattern 386c and the power supply via hole 387, and is electrically connected to the power supply terminal 348 (FIG. 29(b)) of the second LED driver 326 via the fourth wiring pattern 386d and the second through hole 384.

By arranging the bypass capacitor 381 between the power supply terminal 348 of the second LED driver 326 and the power supply plane layer (not shown), the influence of the noise components contained in the driving power supplied from the audio light emission control device 81 to the second LED driver 326 on the second LED driver 326 can be reduced. The bypass capacitor 381 (FIG. 28(b)) is arranged close to the power supply terminal 348 so that there are no other electronic components such as ICs between the bypass capacitor 381 and the power supply terminal 348 of the second LED driver 326 (FIG. 29(b)). This increases the possibility that the noise components contained in the driving power supplied to the power supply terminal 348 of the second LED driver 326 are absorbed by the bypass capacitor 381, and reduces the possibility that the second LED driver 326 will malfunction due to the influence of the noise components. In addition, by having the bypass capacitor 381 absorb the noise components generated by the second LED driver 326, it is possible to prevent the noise components from causing other electronic components such as ICs to malfunction.

In the light emitting substrate 301, the small chip components including the bypass capacitor 381 are concentrated on the first light emitting surface 302 side (FIG. 28(a)) and are not mounted on the second light emitting surface 303 side (FIG. 29(a)). Therefore, by handling the light emitting substrate 301 so that the stress acting on the first light emitting surface 302 side of the light emitting substrate 301 is smaller than the stress acting on the second light emitting surface 303 side, the possibility of damage to the connection points between the small chip components and the light emitting substrate 301 can be reduced, and the possibility of damage to the small chip components themselves can be reduced. For example, when a collective substrate (not shown) including a plurality of light emitting substrates 301 is divided to extract the light emitting substrates 301, the collective substrate can be divided in such a manner that the first light emitting surface 302 side has a valley shape (concave), thereby preventing tensile stress from acting on the connection points between the small chip components and the light emitting substrate 301. This prevents damage to the connection points between the small chip components and the light emitting substrate 301, and prevents damage to the small chip components themselves.

As shown in Figures 29(a) and (b), on the second light-emitting surface 303 of the light-emitting substrate 301, the first through-hole 383 and the second through-hole 384 are provided at a position approximately 0.8 mm away from the outer edge of the second LED driver 326. Also, as shown in Figures 28(a) and (b), the bypass capacitor 381 is mounted at a position approximately 0.8 mm away from the first through-hole 383 and the second through-hole 384 in a direction away from the second LED driver 326 (Figures 28(a) and (b)).

As shown in FIG. 28A, the bypass capacitor 381 is arranged to avoid the driver back side corresponding region 391. The driver back side corresponding region 391 is a region of the first light-emitting surface 302 located on the back side of the region where the second LED driver 326 (FIG. 29) is mounted on the second light-emitting surface 303 (FIG. 29) and the region where the pads (or pads) corresponding to the terminals of the second LED driver 326 are provided, and a region within 1 mm from the region of the first light-emitting surface 302. Since the bypass capacitor 381 is not mounted in the region of the first light-emitting surface 302 located on the back side of the region where the second LED driver 326 is mounted on the second light-emitting surface 303 and the region where the pads corresponding to the terminals of the second LED driver 326 are provided, the influence of the thermal stress that may act on the light-emitting substrate 301 due to the heat generated by the second LED driver 326 on the bypass capacitor 381 is reduced. By arranging the bypass capacitor 381 to avoid the driver back side corresponding area 391, it is possible to prevent damage to the connection between the bypass capacitor 381 and the light emitting substrate 301 due to the influence of thermal stress caused by heat generated by the second LED driver 326, and also to prevent damage to the bypass capacitor 381 itself.

As shown in FIG. 28(b), on the first light-emitting surface 302 of the light-emitting substrate 301, the first wiring pattern 386a electrically connecting the first pad 382a corresponding to the first electrode 381a of the bypass capacitor 381 and the GND via hole 385 is a linear wiring pattern drawn leftward from the left end of the first pad 382a. Also, the third wiring pattern 386c electrically connecting the second pad 382b corresponding to the second electrode 381b of the bypass capacitor 381 and the power supply via hole 387 is a linear wiring pattern drawn leftward from the left end of the second pad 382b.

The direction (left direction) of the four sides of the first pad 382a in which the first wiring pattern 386a is drawn out when viewed from the center of the first pad 382a is the same as the direction (left direction) of the four sides of the second pad 382b in which the third wiring pattern 386c is drawn out when viewed from the center of the second pad 382b. Therefore, it is possible to prevent a difference in temperature distribution in the pair of the first pad 382a and the second pad 382b from occurring in the initial heating stage of the reflow process. The direction in which the first wiring pattern 386a is drawn out from the first pad 382a is the same direction (left direction) as the direction in which the third wiring pattern 386c is drawn out from the second pad 382b. Therefore, it is possible to reduce the difference in temperature distribution that may occur in the pair of the first pad 382a and the second pad 382b in the initial heating stage.

The first wiring pattern 386a and the third wiring pattern 386c are drawn out in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 381. Therefore, when the light emitting substrate 301 is distorted, the maximum value of the stress that may act on the connection between the bypass capacitor 381 and the light emitting substrate 301 can be reduced, and the maximum value of the stress that may act on the bypass capacitor 381 itself can be reduced. In addition, the first wiring pattern 386a and the third wiring pattern 386c extend linearly in the longitudinal direction of the bypass capacitor 381. Therefore, the possibility that the connection between the bypass capacitor 381 and the light emitting substrate 301 will be damaged due to the influence of distortion that may occur in the light emitting substrate 301 can be reduced, and the possibility that the bypass capacitor 381 itself will be damaged can be reduced.

On the first light-emitting surface 302 of the light-emitting substrate 301, the second wiring pattern 386b electrically connecting the first pad 382a corresponding to the first electrode 381a of the bypass capacitor 381 and the first through-hole 383 is a linear wiring pattern drawn rightward from the right end of the first pad 382a. Also, the fourth wiring pattern 386d electrically connecting the second pad 382b corresponding to the second electrode 381b of the bypass capacitor 381 and the second through-hole 384 is a linear wiring pattern drawn rightward from the right end of the second pad 382b.

The direction (right direction) of the side from which the second wiring pattern 386b is drawn out when viewed from the center of the first pad 382a among the four sides of the first pad 382a is the same as the direction (right direction) of the side from which the fourth wiring pattern 386d is drawn out when viewed from the center of the second pad 382b among the four sides of the second pad 382b. Therefore, it is possible to prevent a difference in temperature distribution in the pair of the first pad 382a and the second pad 382b from occurring in the initial heating stage of the reflow process. The direction (right direction) of the drawing of the second wiring pattern 386b from the first pad 382a is the same as the direction (right direction) of the drawing of the fourth wiring pattern 386d from the second pad 382b. Therefore, it is possible to reduce the difference in temperature distribution that may occur in the pair of the first pad 382a and the second pad 382b in the initial heating stage.

The second wiring pattern 386b and the fourth wiring pattern 386d are drawn out in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 381. Therefore, when the light emitting substrate 301 is distorted, the maximum value of the stress that may act on the connection between the bypass capacitor 381 and the light emitting substrate 301 can be reduced, and the maximum value of the stress that may act on the bypass capacitor 381 itself can be reduced. In addition, the second wiring pattern 386b and the fourth wiring pattern 386d extend linearly in the longitudinal direction of the bypass capacitor 381. Therefore, the possibility that the connection between the bypass capacitor 381 and the light emitting substrate 301 will be damaged due to the influence of distortion that may occur in the light emitting substrate 301 can be reduced, and the possibility that the bypass capacitor 381 itself will be damaged can be reduced.

The present embodiment described above provides the following excellent advantages:

The bypass capacitor 381 for absorbing noise components contained in the driving power supply of the second LED driver 326 mounted on the second light-emitting surface 303 side of the light-emitting substrate 301 is mounted on the first light-emitting surface 302 side, which is the plate surface opposite to the second light-emitting surface 303. The bypass capacitor 381 is a small chip component. The second pad 382b corresponding to the second electrode 381b of the bypass capacitor 381 is electrically connected to the power supply plane layer via the third wiring pattern 386c and the power supply via hole 387, and is electrically connected to the power supply terminal 348 of the second LED driver 326 via the fourth wiring pattern 386d and the second through hole 384. By arranging the bypass capacitor 381 between the power supply terminal 348 of the second LED driver 326 and the power supply plane layer, the influence of noise components contained in the driving power supply supplied from the sound light-emitting control device 81 to the second LED driver 326 on the second LED driver 326 can be reduced.

The bypass capacitor 381 is placed close to the power supply terminal 348 so that there are no other electronic components such as ICs between the bypass capacitor 381 and the power supply terminal 348 of the second LED driver 326. This increases the likelihood that noise components contained in the driving power supplied to the power supply terminal 348 of the second LED driver 326 will be absorbed by the bypass capacitor 381, and reduces the likelihood that the second LED driver 326 will malfunction due to the influence of the noise components. In addition, by having the bypass capacitor 381 absorb the noise components generated by the second LED driver 326, it is possible to prevent the noise components from causing other electronic components such as ICs to malfunction.

The first pad 382a corresponding to the first electrode 381a of the bypass capacitor 381 is electrically connected to the GND terminal 349 of the second LED driver 326 via the first through hole 383, and the second pad 382b corresponding to the second electrode 381b of the bypass capacitor 381 is electrically connected to the power terminal 348 of the second LED driver 326 via the second through hole 384. Therefore, the bypass capacitor 381 for absorbing noise components contained in the driving power supply of the second LED driver 326 mounted on the second light-emitting surface 303 side can be arranged on the first light-emitting surface 302 side, which is the plate surface opposite to the second light-emitting surface 303. In a configuration in which the bypass capacitor 381 is a small chip component, by arranging the bypass capacitor 381 on the first light-emitting surface 302 side, the small chip components can be concentrated on the first light-emitting surface 302 side in the light-emitting substrate 301. Therefore, by handling the light emitting substrate 301 so that the stress acting on the first light emitting surface 302 side of the light emitting substrate 301 is smaller than the stress acting on the second light emitting surface 303 side, the possibility of damage to the connection points between the small chip components and the light emitting substrate 301 can be reduced, and the possibility of damage to the small chip components themselves can be reduced. For example, when dividing an assembly substrate (not shown) including a plurality of light emitting substrates 301 to extract the light emitting substrates 301, the assembly substrate can be divided in such a manner that the first light emitting surface 302 side has a valley shape (concave), thereby preventing tensile stress from acting on the connection points between the small chip components and the light emitting substrate 301. This prevents damage to the connection points between the small chip components and the light emitting substrate 301, and prevents damage to the small chip components themselves.

The bypass capacitor 381 is arranged to avoid the driver back side corresponding area 391. The driver back side corresponding area 391 is an area of the first light emitting surface 302 located behind the area where the second LED driver 326 is mounted on the second light emitting surface 303 and the area where the pads corresponding to the terminals of the second LED driver 326 are provided, and an area within 1 mm from the area of the first light emitting surface 302. Since the bypass capacitor 381 is not mounted in the area of the first light emitting surface 302 located behind the area where the second LED driver 326 is mounted on the second light emitting surface 303 and the area where the pads corresponding to the terminals of the second LED driver 326 are provided, the effect of the thermal stress that may act on the light emitting substrate 301 due to heat generation by the second LED driver 326 on the bypass capacitor 381 is reduced. By arranging the bypass capacitor 381 to avoid the driver back side corresponding area 391, it is possible to prevent damage to the connection between the bypass capacitor 381 and the light emitting substrate 301 due to the influence of thermal stress caused by heat generated by the second LED driver 326, and also to prevent damage to the bypass capacitor 381 itself.

The direction in which the side in which the first wiring pattern 386a is drawn out exists among the four sides of the first pad 382a corresponding to the first electrode 381a of the bypass capacitor 381 as viewed from the center of the first pad 382a is the same as the direction in which the side in which the third wiring pattern 386c is drawn out exists among the four sides of the second pad 382b corresponding to the second electrode 381b of the bypass capacitor 381 as viewed from the center of the second pad 382b. Therefore, it is possible to prevent a difference in the temperature distribution in the pair of the first pad 382a and the second pad 382b from occurring in the initial heating stage of the reflow process. The direction in which the first wiring pattern 386a is drawn out from the first pad 382a is the same as the direction in which the third wiring pattern 386c is drawn out from the second pad 382b. Therefore, it is possible to reduce the difference in the temperature distribution in the pair of the first pad 382a and the second pad 382b in the initial heating stage.

The first wiring pattern 386a and the third wiring pattern 386c are drawn out in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 381. Therefore, when the light emitting substrate 301 is distorted, the maximum value of the stress that may act on the connection between the bypass capacitor 381 and the light emitting substrate 301 can be reduced, and the maximum value of the stress that may act on the bypass capacitor 381 itself can be reduced. In addition, the first wiring pattern 386a and the third wiring pattern 386c extend linearly in the longitudinal direction of the bypass capacitor 381. Therefore, the possibility that the connection between the bypass capacitor 381 and the light emitting substrate 301 will be damaged due to the influence of distortion that may occur in the light emitting substrate 301 can be reduced, and the possibility that the bypass capacitor 381 itself will be damaged can be reduced.

The direction in which the side in which the second wiring pattern 386b is drawn out exists among the four sides of the first pad 382a corresponding to the first electrode 381a of the bypass capacitor 381 as viewed from the center of the first pad 382a is the same as the direction in which the side in which the fourth wiring pattern 386d is drawn out exists among the four sides of the second pad 382b corresponding to the second electrode 381b of the bypass capacitor 381 as viewed from the center of the second pad 382b. Therefore, it is possible to prevent a difference in the temperature distribution in the pair of the first pad 382a and the second pad 382b from occurring in the initial heating stage of the reflow process. The direction in which the second wiring pattern 386b is drawn out from the first pad 382a is the same as the direction in which the fourth wiring pattern 386d is drawn out from the second pad 382b. Therefore, it is possible to reduce the difference in the temperature distribution in the pair of the first pad 382a and the second pad 382b in the initial heating stage.

The second wiring pattern 386b and the fourth wiring pattern 386d are drawn out in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 381. Therefore, when the light emitting substrate 301 is distorted, the maximum value of the stress that may act on the connection between the bypass capacitor 381 and the light emitting substrate 301 can be reduced, and the maximum value of the stress that may act on the bypass capacitor 381 itself can be reduced. In addition, the second wiring pattern 386b and the fourth wiring pattern 386d extend linearly in the longitudinal direction of the bypass capacitor 381. Therefore, the possibility that the connection between the bypass capacitor 381 and the light emitting substrate 301 will be damaged due to the influence of distortion that may occur in the light emitting substrate 301 can be reduced, and the possibility that the bypass capacitor 381 itself will be damaged can be reduced.

In addition, in the first light-emitting surface 302 of the light-emitting substrate 301, the driver back side corresponding region 391 where the bypass capacitor 381 is not mounted is not limited to the region of the first light-emitting surface 302 located on the back side of the region where the second LED driver 326 (FIG. 29) is mounted on the second light-emitting surface 303 (FIG. 29) and the region where the pads corresponding to the terminals of the second LED driver 326 are provided, and the region within 1 mm from the region of the first light-emitting surface 302. The driver back side corresponding region 391 may be the region of the first light-emitting surface 302 located on the back side of the region where the second LED driver 326 is mounted on the second light-emitting surface 303 and the region where the pads corresponding to the terminals of the second LED driver 326 are provided, and the region within 2 mm from the region of the first light-emitting surface 302. This can further reduce the influence of thermal stress that may act on the light-emitting substrate 301 due to heat generation by the second LED driver 326 on the small chip components. Therefore, it is possible to reduce the possibility that the connection between the bypass capacitor 381 and the light emitting substrate 301 will be damaged due to the influence of thermal stress caused by the heat generated by the second LED driver 326, and the possibility that the bypass capacitor 381 itself will be damaged. In addition, the driver back side corresponding area 391 may be an area of the first light emitting surface 302 located on the back side of the area where the second LED driver 326 is mounted on the second light emitting surface 303 and the area where the pads corresponding to the terminals of the second LED driver 326 are provided, and an area within 0.5 mm away from the area of the first light emitting surface 302. This makes it possible to secure a large area on the first light emitting surface 302 of the light emitting substrate 301 where small chip components can be mounted, while reducing the influence of thermal stress that may act on the light emitting substrate 301 due to the heat generated by the second LED driver 326 on the small chip components.

<Other embodiments>
The present invention is not limited to the above-described embodiment, and various modifications and improvements are possible without departing from the spirit of the present invention. For example, the following modifications may be made. The following configurations of the other embodiments may be applied individually or in combination to the configurations of the above-described embodiment.

(1) In the first embodiment, all electronic components including the connectors 111, 112 and small chip components may be concentrated on the mounting surface, which is the plate surface on one side of the first decorative board 56, and the small chip components may be arranged on the mounting surface to avoid the peripheral area of the connectors 111, 112. Specifically, all electronic components including the first connector 111, the second connector 112 and small chip components (bypass capacitors 85, 97 and small chip resistors 87, 101, 143-149) are concentrated on the mounting surface, which is the plate surface on one side of the first decorative board 56. No electronic components are mounted on the back plate surface, which is the plate surface on the opposite side of the mounting surface, in the first decorative board 56. In the first decorative board 56, no small chip components are mounted in the first connector peripheral area, which is less than a predetermined distance (specifically, less than 5 mm) from the outer edge of the first connector 111. The first connector peripheral region is an area where tensile stress is likely to act when the harness is attached to the first connector 111, and is also an area where compressive stress is likely to act when the harness is removed from the first connector. In addition, no small chip components are mounted in the second connector peripheral region, which is less than a predetermined distance (specifically, less than 5 mm) from the second connector 112. The second connector peripheral region is an area where tensile stress is likely to act when the harness is attached to the second connector 112, and is also an area where compressive stress is likely to act when the harness is removed from the second connector 112. If small chip components are mounted in the connector peripheral region, there is a risk that the connection between the small chip components and the first decorative substrate 56 will be damaged when the harness is attached to or detached from the connectors 111 and 112, and there is also a risk that the small chip components themselves will be damaged. In contrast, the small chip components are arranged to avoid the area surrounding the connector, which prevents damage to the connection between the small chip components and the first decorative substrate 56 when attaching or detaching the harness to the connectors 111 and 112, and also prevents damage to the small chip components themselves.

In this manner, all electronic components are concentrated on the mounting surface of the first decorative substrate 56, and the small chip components are arranged on the mounting surface to avoid the areas surrounding the connectors 111, 112. This prevents damage to the connection points between the small chip components and the first decorative substrate 56 when attaching or detaching the harness to the connectors 111, 112, and also prevents damage to the small chip components themselves.

(2) In the first embodiment, the wiring patterns 172a to 172d extending from the pair of pads 171a and 171b may be configured to extend in different directions. Specifically, the first wiring pattern extends from approximately the center in the vertical direction at the right end of the first pad 171a corresponding to the first electrode 85a of the bypass capacitor 85 in an upward and upward direction to the right, and the third wiring pattern extends from approximately the center in the vertical direction at the right end of the second pad 171b corresponding to the second electrode in a downward and upward direction to the right. Even if the directions in which the first wiring pattern and the third wiring pattern are drawn out from the pads 171a and 171b are different, by configuring the direction in which the side of the four sides of the first pad 171a in which the first wiring pattern is drawn out exists as viewed from the center of the first pad 171a to be the same as the direction in which the side of the four sides of the second pad 171b in which the third wiring pattern is drawn out exists as viewed from the center of the second pad 171b, the possibility of differences in temperature distribution within the pads 171a and 171b occurring during the initial heating stage of the reflow process can be reduced.

(3) In the first embodiment, a part of the wiring patterns 172a to 172d drawn out from the pads 171a and 171b may extend in a direction not perpendicular to the longitudinal direction of the bypass capacitor 85. Specifically, as in the first embodiment, the first wiring pattern 172a is drawn out to the right from the right end of the first pad 171a corresponding to the first electrode 85a of the bypass capacitor 85, and the second wiring pattern 172b is drawn out to the left from the left end of the first pad 171a. Also, as in the first embodiment, the fourth wiring pattern 172d is drawn out to the left from the left end of the second pad 171b corresponding to the second electrode 85b of the bypass capacitor 85. The third wiring pattern in this configuration is drawn out diagonally downward to the right from the right end of the second pad 171b. In this way, even if some of the wiring patterns 172a to 172d drawn from the pads 171a and 171b extend in a direction that is not perpendicular to the longitudinal direction of the bypass capacitor 85, compared to a configuration in which the wiring patterns drawn from the pads 171a and 171b extend in the longitudinal direction of the bypass capacitor 85, the maximum value of the stress that can act on the connection point between the bypass capacitor 85 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56 can be reduced, and the maximum value of the stress that can act on the bypass capacitor 85 itself can be reduced.

(4) In the first embodiment, the first decorative board 56 may be configured to have a GND solid pattern (ground solid pattern or ground solid pattern) instead of the GND plane layer 93, and a power solid pattern instead of the power plane layer 94. Specifically, the first decorative board is a two-layer board having a first mounting surface and a second mounting surface. A GND solid pattern and a power solid pattern having a larger area than the wiring patterns 172a to 172d are formed on the second mounting surface of the first decorative board. The first wiring pattern 172a drawn from the first pad 171a of the bypass capacitor 85 is electrically connected to the GND solid pattern via a through hole provided in the first decorative board, and the second wiring pattern 172b drawn from the first pad 171a is electrically connected to the GND terminal 154 of the LED driver 126. The third wiring pattern 172c drawn from the second pad 171b of the bypass capacitor 85 is electrically connected to the power supply solid pattern through a through hole provided in the first decorative board, and the fourth wiring pattern 172d drawn from the second pad 171b is electrically connected to the power supply terminal 151 of the LED driver 126. The first wiring pattern 172a connected to the GND solid pattern, which is larger than the first pad 171a, is slower in temperature rise in the initial heating stage than the second wiring pattern 172b not connected to the GND solid pattern. The third wiring pattern 172c connected to the power supply solid pattern, which is larger than the second pad 171b, is slower in temperature rise in the initial heating stage than the fourth wiring pattern 172d not connected to the power supply solid pattern. In this configuration, in which the same number of wiring patterns 172a to 172d (specifically, two) are drawn out from the first pad 171a and the second pad 171b, the direction in which the side from which the first wiring pattern 172a is drawn out exists among the four sides of the first pad 171a as viewed from the center of the first pad 171a is the same direction as the direction in which the side from which the third wiring pattern 172c is drawn out exists among the four sides of the second pad 171b as viewed from the center of the second pad 171b. Also, the direction in which the side from which the second wiring pattern 172b is drawn out exists among the four sides of the first pad 171a as viewed from the center of the first pad 171a is the same direction as the direction in which the side from which the fourth wiring pattern 172d is drawn out exists among the four sides of the second pad 171b as viewed from the center of the second pad 171b. This reduces the difference in temperature distribution within the pair of pads 171a, 171b during the initial heating stage of the reflow process, and prevents the bypass capacitor 85 from rotating and becoming chip-standing.

(5) In the third embodiment, the second LED driver 326 for controlling the light emission of the LED chips 315 to 325 on the second light-emitting surface 303 and a noise absorbing capacitor for absorbing noise components contained in the driving power supply of the second LED driver 326 may be mounted on the first light-emitting surface 302. The noise absorbing capacitor in this configuration is a small chip component, similar to the bypass capacitor 85 in the first embodiment. By mounting the noise absorbing capacitor on the first light-emitting surface 302, all the small chip components mounted on the light-emitting substrate 301 can be concentrated on the first light-emitting surface 302 side while the noise absorbing capacitor is a small chip component. For this reason, by handling the light-emitting substrate 301 so that the stress acting on the first light-emitting surface 302 side of the light-emitting substrate 301 is smaller than the stress acting on the second light-emitting surface 303 side, the possibility of damage to the connection points between the small chip components and the light-emitting substrate 301 can be reduced, and the possibility of damage to the small chip components themselves can be reduced. For example, when dividing an assembly substrate (not shown) including a plurality of light emitting substrates 301 to extract the light emitting substrates 301, dividing the assembly substrate in such a manner that the first light emitting surface 302 side has a valley shape (concave) can prevent tensile stress from acting on the connection points between the small chip components and the light emitting substrate 301. This can prevent damage to the connection points between the small chip components and the light emitting substrate 301, and can also prevent damage to the small chip components themselves.

(6) In the third and fourth embodiments, instead of the configuration in which the light emitting substrate 301 is fixed to the substrate case by screws, the light emitting substrate 301 may be sandwiched between the substrate case from the front side and the rear side. The substrate case includes a front side case body and a rear side case body. The front side case body has a front side fixing protrusion standing on the rear side, and the rear side case body has a rear side fixing protrusion standing on the front side. The light emitting substrate 301 is fixed to the substrate case by being sandwiched between the front side fixing protrusion and the rear side fixing protrusion. In the light emitting substrate 301, the small chip components are arranged 5 mm or more away from the clamping portion between the front side fixing protrusion and the rear side fixing protrusion. This can prevent the connection between the small chip components and the light emitting substrate 301 from being damaged due to the influence of distortion of the light emitting substrate 301 that may occur near the clamping portion, and can also prevent the small chip components themselves from being damaged.

(7) In each of the above embodiments, as long as the direction in which the side in which the wiring pattern is drawn out exists among the four sides of the first pad (or first pad) as viewed from the center of the first pad exists and the direction in which the side in which the wiring pattern is drawn out exists among the four sides of the second pad (or second pad) as viewed from the center of the second pad exists are the same direction, the drawing position of the wiring pattern on the side in which the wiring pattern is drawn out in the first pad and the drawing position of the wiring pattern on the side in which the wiring pattern is drawn out in the second pad may not be the same. For example, in the above first embodiment, the first wiring pattern 181a may be drawn out to the right from a position above the center in the vertical direction on the right side of the rectangular first pad 176a electrically connected to the first electrode 87a of the small chip resistor 87, and the second wiring pattern 181b may be drawn out to the right from a position below the center in the vertical direction on the right side of the rectangular second pad 176b electrically connected to the second electrode 87b. Even with this configuration, the direction (to the right) of the four sides of the first pad 176a from which the first wiring pattern 181a is drawn when viewed from the center of the first pad 176a is the same as the direction (to the right) of the four sides of the second pad 176b from which the second wiring pattern 181b is drawn when viewed from the center of the second pad 176b. This reduces the possibility of a difference in temperature distribution between the first pad 176a and the second pad 176b during the initial heating stage of the reflow process.

(8) In each of the above embodiments, the shape of the first pad (or first pad) electrically connected to the first electrode of the small chip component and the second pad (or second pad) electrically connected to the second electrode are not limited to a rectangle, and may be a polygon such as a hexagon or octagon. For example, in a configuration in which the shape of the first pad and the second pad is a hexagon, the direction in which the side from which the first wiring pattern is drawn out exists among the six sides of the first pad as viewed from the center of the first pad is the same as the direction in which the side from which the second wiring pattern is drawn out exists among the six sides of the second pad as viewed from the center of the second pad, thereby reducing the possibility of a difference in temperature distribution occurring in the first pad and the second pad during the initial heating stage of the reflow process.

(9) In each of the above embodiments, instead of the configuration in which the small chip components (the bypass capacitors 85, 97 in the first embodiment, the small chip resistors 87, 101, the bypass capacitor 291 in the second embodiment, and the bypass capacitor 381 in the fourth embodiment) are provided with electrodes in the narrow sense (first electrodes 85a, 87a, 97a, 101a, 291a, 381a and second electrodes 85b, 87b, 97b, 101b, 291b, 381b), the small chip components may be provided with terminals. As already explained in the first embodiment, a "terminal" is a linear metal part provided on an electronic component (including a small chip component) to electrically connect to a corresponding pad (or pad), and an "electrode" is a metal part provided on an electronic component (including a small chip component) to electrically connect to a corresponding pad (or pad) in a surface sense, and does not include the above "terminal".

Specifically, the bypass capacitors 85, 97, 291, 381 may be provided with a linear first terminal extending from one end of the bypass capacitor 85, 97, 291, 381 along a plane perpendicular to the thickness direction of the bypass capacitor 85, 97, 291, 381 to one side in the longitudinal direction, and a linear second terminal extending from the other end of the bypass capacitor 85 opposite the one end in the longitudinal direction to the other side opposite the one side in the longitudinal direction. Also, the small chip resistors 87, 101 may be provided with a linear first terminal extending from one end of the bypass capacitor 85, 101 along a plane perpendicular to the thickness direction of the small chip resistors 87, 101 to one side in the longitudinal direction, and a linear second terminal extending from the other end of the bypass capacitor 85 opposite the one end in the longitudinal direction to the other side opposite the one side in the longitudinal direction.

(10) In each of the above embodiments, instead of the configuration in which the LED driver 126, 314, 326 is provided with a terminal, the LED driver 126, 314, 326 may be provided with an electrode in the narrow sense. As already explained in the first embodiment, a "terminal" is a linear metal part provided on an electronic component (including a small chip component) to electrically connect with a corresponding pad (or pad), and an "electrode" is a metal part provided on an electronic component (including a small chip component) to electrically connect with a corresponding pad (or pad) in a surface sense, and does not include the above "terminal". Specifically, an electrode in the narrow sense may be provided at a position facing the pad (or pad) in the approximately rectangular parallelepiped housing of the LED driver 126, 314, 326, and the pad and the electrode may be electrically connected by solder.

(11) In the first embodiment, the slits 255-258 are provided at locations on the collective substrate 231 corresponding to the area where the bypass capacitor 85 is mounted, but the present invention is not limited to this. A second division groove (a division groove with a thin bottom) that is deeper than a normal first division groove may be formed at the location. The first division groove and the second division groove are formed in a straight line. The plate thickness of the bottom of the second division groove is smaller than the plate thickness of the bottom of the first division groove, and the mechanical strength of the second division groove is lower than the mechanical strength of the first division groove. Therefore, when the collective substrate 231 is divided into valleys with the first division groove and the second division groove existing in a straight line as base points, the stress acting on the periphery of the second division groove is smaller than the stress acting on the periphery of the first division groove. By configuring the assembly substrate 231 so that the second dividing groove is provided at a location corresponding to the area where the bypass capacitor 85 is mounted, it is possible to reduce stress that may act on the connection between the bypass capacitor 85 and the first decorative substrate 56 when the assembly substrate 231 is divided, and also to reduce stress that may act on the bypass capacitor 85 itself.

(12) In the first embodiment, the dividing grooves 232-247 are formed only on the first plate surface 268 side of the collective substrate 231, but this is not limited thereto, and the dividing grooves 232-247 may be provided on both the first plate surface 268 side and the second plate surface 269 side. The dividing grooves 232-247 are formed one by one on each of the first plate surface 268 side and the second plate surface 269 side of the collective substrate 231, and the formation positions of the dividing grooves are approximately the same on the first plate surface 268 side and the second plate surface 269 side. In this configuration, the throw-away substrates 261-267 are provided with a mountain side marking by silk printing, which allows the plate surface that becomes a mountain shape (convex) when the collective substrate 231 is divided into valleys to be confirmed. The mountain side marking is provided on the second plate surface 269 side. By setting the collective board 231 in the dividing jig 281 with the side on which the mountain side markings are printed facing up, the worker can divide the collective board 231 into valleys so that the first board surface 268 has a valley shape (concave). The mountain side markings are printed only on the throw-away boards, and are not printed on the first decorative board 56 that is removed from the collective board 231. In this way, by configuring the throw-away boards 261-267 with the mountain side markings printed on them, it is possible to prevent the collective board 231 from being divided into valleys by mistake.

(13) In the first embodiment, the dividing grooves 232-235, 240, 241, 246, 247 are formed at the boundaries between the first decorative substrate 56 and the throwaway substrates 261, 263, 266 in the collective substrate 231, but this is not limited thereto. The boundaries between the first decorative substrate 56 and the throwaway substrates 261, 263, 266 may be formed with perforations in which the first decorative substrate 56 and the throwaway substrates 261, 263, 266 are alternately connected and not connected. The mechanical strength of the collective substrate 231 at the perforations is lower than the mechanical strength of the area surrounding the perforations. By providing perforations at the boundaries between the first decorative substrate 56 and the throwaway substrates 261, 263, 266, it is possible to reduce the stress that may act on the connection points between the small chip components and the first decorative substrate 56 when the collective substrate 231 is divided, and also to reduce the stress that may act on the small chip components themselves.

(14) In the first embodiment, the collective substrate 231 is configured to have a plurality of first decorative substrates 56, but this is not limited thereto, and the collective substrate 231 may have a plurality of types of substrates. This makes it possible to extract a plurality of types of substrates from a single collective substrate 231.

(15) In the first embodiment, the collective substrate 231 may be silk-screened with pressure position indicators indicating where force should be applied to split the collective substrate 231 into valleys. After fixing the collective substrate 231 to the splitting jig 281, the worker can split the collective substrate 231 by pressing the part where the pressure position indicator is printed downward with a finger. By specifying the place where force should be applied to split the collective substrate 231 into valleys using the pressure position indicators, it is possible to minimize stress that may act on the connection points between the small chip components and the first decorative substrate 56 when splitting the collective substrate 231, and also to minimize stress that may act on the small chip components themselves.

(16) In the first and second embodiments, the small chip components (bypass capacitor 85 and small chip resistor 87) are mounted on the decorative boards 56 and 57 for performing the light-emitting effects, but this is not limited thereto. For example, the small chip components may be mounted on a motor control board for performing a vibration effect that vibrates the pachinko machine 10. In addition, the small chip components may be mounted on at least one of the main control board 61 of the main control device 60, the audio and light-emitting control board of the audio and light-emitting control device 81, the payout control board of the payout control device 77, the power supply and launch control board of the power supply and launch control device 78, and the display control board of the display control device 82.

(17) Instead of a configuration in which the display control device 82 is controlled by the audio/light emitting control device 81 based on a command sent from the main control device 60, the display control device 82 may be configured to control the audio/light emitting control device 81 based on a command sent from the main control device 60. Also, instead of a configuration in which the audio/light emitting control device 81 and the display control device 82 are provided separately, both control devices may be provided as a single control device, the functions of one of the two control devices may be integrated into the main control device 60, or both functions of the two control devices may be integrated into the main control device 60. Also, the content of the command sent from the main control device 60 to the audio/light emitting control device 81 and the content of the command sent from the audio/light emitting control device 81 to the display control device 82 are also arbitrary.

(18) The present invention can also be applied to other types of pachinko machines that differ from the above-described embodiments, such as pachinko machines in which an electric device opens a predetermined number of times when a gaming ball enters a specific area of a special device, pachinko machines in which a right is generated and a jackpot is awarded when a gaming ball enters a specific area of a special device, pachinko machines equipped with other devices, arrange ball machines, mahjong ball machines, and other gaming machines.

The present invention can also be applied to non-pinball gaming machines, such as slot machines, which have multiple reels with multiple patterns circumferentially attached, and which start the rotation of the reels by inserting a medal and operating a start lever, and which, after the reels stop when a stop switch is operated or a predetermined time has passed, award the player with a special prize, such as a medal payout, if a specific pattern or combination of specific patterns is formed on a winning line visible through a display window.

The present invention can also be applied to a gaming machine that combines a pachinko machine and a slot machine, in which the gaming machine body is supported on an outer frame so that it can be opened and closed, has a storage section and an intake device, and the reels start to rotate when a start lever is operated after a predetermined number of gaming balls stored in the storage section have been taken in by the intake device.

<Inventions extracted from the above embodiments>
The following describes the features of the inventions extracted from each of the above-mentioned embodiments, while indicating, as necessary, the effects, etc. In the following, for ease of understanding, the corresponding configurations in each of the above-mentioned embodiments are appropriately indicated in parentheses, but the present invention is not limited to the specific configurations indicated in parentheses.

<Features Group A>
Feature A1. In a gaming machine having a predetermined board (the first decorative board 56, the second decorative board 57, and the light-emitting board 301 in the fourth embodiment) on which predetermined electronic components (the bypass capacitors 85 and 97 in the first embodiment, the small chip resistors 87 and 101, the bypass capacitor 291 in the second embodiment, and the bypass capacitor 381 in the fourth embodiment) are mounted,
The predetermined electronic component includes a pair of electrodes, that is, a first predetermined electrode (first electrodes 85a, 87a, 291a, 381a) and a second predetermined electrode (second electrodes 85b, 87b, 291b, 381b),
The predetermined substrate is
a first predetermined connection portion (first pad 171a, 176a, 293a, 382a) to which the first predetermined electrode is electrically connected;
a first predetermined wiring pattern (first wiring patterns 172a, 181a, 294a, 386a, second wiring patterns 172b, 294b, 386b) drawn out from the first predetermined connection portion;
second predetermined connection portions (second pads 171b, 176b, 293b, 382b) to which the second predetermined electrodes are electrically connected;
second predetermined wiring patterns (second wiring pattern 181b, third wiring pattern 172c, 294c, 386c, fourth wiring pattern 172d, 294d, 386d) drawn out from the second predetermined connection portion;
Equipped with
A gaming machine characterized in that the direction in which the side of the first specified connection part from which the first specified wiring pattern is pulled out exists when viewed from the center of the first specified connection part is the same as the direction in which the side of the second specified connection part from which the second specified wiring pattern is pulled out exists when viewed from the center of the second specified connection part.

According to feature A1, the direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists when viewed from the center of the first predetermined connection part is the same as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection part. Therefore, it is possible to align the temperature distribution in the pair of first and second predetermined connection parts in the initial heating stage of the reflow process, and to align the manner in which the solder paste applied on the first and second predetermined connection parts melts. This makes it possible to prevent the specified electronic component from rotating around the normal direction of the specified board as the rotation axis, and to prevent the occurrence of so-called chip standing, in which the specified electronic component stands up on one connection part (first specified connection part or second specified connection part) with only one electrode (first specified electrode or second specified electrode). Therefore, it is possible to ensure the electrical connection area between the first specified electrode and the first specified connection part, and to ensure the electrical connection area between the second specified electrode and the second specified connection part.

Feature A2. The gaming machine described in Feature A1, characterized in that the direction in which the first predetermined wiring pattern is drawn from the first predetermined connection portion is the same as the direction in which the second predetermined wiring pattern is drawn from the second predetermined connection portion.

Feature A2 reduces the possibility of a difference in temperature distribution occurring within the first and second specified connection parts during the initial heating stage of the reflow process.

Feature A3: The first predetermined connection portion is electrically connected to a first metal region (GND plane layer 93) having an area larger than that of the first predetermined connection portion via the first predetermined wiring pattern,
The gaming machine described in feature A1 or A2, characterized in that the second specified connection portion is electrically connected to a second metal region (power supply plane layer 94) having a larger area than the second specified connection portion via the second specified wiring pattern.

According to feature A3, in the specified connection part (first specified connection part or second specified connection part), the side where the pull-out part of the specified wiring pattern (first specified wiring pattern or second specified wiring pattern) that is electrically connected to the large-area metal region (first metal region or second metal region) is located is prone to a delayed temperature rise in the initial heating stage of the reflow process, but the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the first specified connection part is the same direction as the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the second specified connection part. This makes it possible to align the temperature distribution in the first specified connection part and the second specified connection part in the initial heating stage.

Feature A4. The wiring pattern drawn out from the first predetermined connection portion is only the first predetermined wiring pattern,
A gaming machine described in any one of features A1 to A3, characterized in that the wiring pattern pulled out from the second predetermined connection portion is only the second predetermined wiring pattern.

Feature A4 reduces the possibility of differences in temperature distribution occurring within a pair of first and second predetermined connection parts during the initial heating stage.

Feature A5. The predetermined substrate is
a third predetermined wiring pattern (second wiring patterns 172b, 294b, 386b) drawn out from the first predetermined connection portion;
a fourth predetermined wiring pattern (fourth wiring patterns 172d, 294d, 386d) drawn out from the second predetermined connection portion;
Equipped with
A gaming machine described in any one of features A1 to A3, characterized in that the direction in which the side of the first predetermined connection part from which the third predetermined wiring pattern is pulled out exists when viewed from the center of the first predetermined connection part is the same as the direction in which the side of the second predetermined connection part from which the fourth predetermined wiring pattern is pulled out exists when viewed from the center of the second predetermined connection part.

According to Feature A5, in a configuration having the configuration of Feature A1, in which the direction of the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn as viewed from the center of the first predetermined connection part is the same as the direction of the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn as viewed from the center of the second predetermined connection part, the direction of the side of the first predetermined connection part from which the third predetermined wiring pattern is drawn as viewed from the center of the first predetermined connection part is the same as the direction of the side of the second predetermined connection part from which the fourth predetermined wiring pattern is drawn as viewed from the center of the second predetermined connection part. Therefore, it is possible to align the temperature distribution in the pair of first and second predetermined connection parts in the initial heating stage of the reflow process, and to align the manner in which the solder paste applied on these first and second predetermined connection parts melts. This prevents the specified electronic component from rotating around the normal direction of the specified substrate as the axis of rotation, and also prevents the occurrence of a so-called chip standing in which the specified electronic component stands on one connection part (the first specified connection part or the second specified connection part) with only one electrode (the first specified electrode or the second specified electrode). Therefore, it is possible to ensure the electrical connection area between the first specified electrode and the first specified connection part, and to ensure the electrical connection area between the second specified electrode and the second specified connection part.

Feature A6. The gaming machine described in Feature A5, characterized in that the direction in which the third predetermined wiring pattern is drawn from the first predetermined connection portion is the same as the direction in which the fourth predetermined wiring pattern is drawn from the second predetermined connection portion.

Feature A6 reduces the possibility of differences in temperature distribution occurring within a pair of first and second predetermined connection parts during the initial heating stage of the reflow process.

Feature A7: The first predetermined connection portion is electrically connected to a first metal region (GND plane layer 93) having an area larger than that of the first predetermined connection portion via the first predetermined wiring pattern,
the third predetermined wiring pattern is not electrically connected to a metal region having an area larger than that of the first predetermined connection portion,
the second predetermined connection portion is electrically connected to a second metal region (power supply plane layer 94) having an area larger than that of the second predetermined connection portion via the second predetermined wiring pattern;
The gaming machine described in feature A5 or A6, characterized in that the fourth predetermined wiring pattern is not electrically connected to a metal area having a larger area than the second predetermined connection portion.

According to feature A7, the side where the pull-out part of the specified wiring pattern (first specified wiring pattern or second specified wiring pattern) electrically connected to the large metal area (first metal area or second metal area) exists in the specified connection part (first specified connection part or second specified connection part) is likely to have a delayed temperature rise in the initial heating stage of the reflow process, but the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the first specified connection part is the same direction as the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the second specified connection part. Also, the direction in which the side where the third specified wiring pattern that is not electrically connected to the large metal area from the first specified connection part exists as viewed from the center of the second specified connection part is the same direction as the direction in which the side where the fourth specified wiring pattern that is not electrically connected to the large metal area from the second specified connection part exists as viewed from the center of the second specified connection part. Therefore, the temperature distribution in the first specified connection part and the second specified connection part in the initial heating stage can be aligned.

Feature A8: The location where the second predetermined wiring pattern is connected in the connection target (the pad electrically connected to the eighth output terminal 162 of the LED driver 126) electrically connected to the second predetermined connection portion using the second predetermined wiring pattern exists in the opposite direction to the drawing direction of the second predetermined wiring pattern from the second predetermined connection portion when viewed in a direction of a predetermined axis (the second direction DR2 in FIG. 8(a) and FIG. 8(c)) including the drawing direction of the second predetermined wiring pattern from the second predetermined connection portion, based on the second predetermined connection portion;
A gaming machine described in any one of features A1 to A7, characterized in that the second predetermined wiring pattern is pulled out from the second predetermined connection part in the same direction as the pull-out direction of the first predetermined wiring pattern from the first predetermined connection part, and then routed in the opposite direction based on the second predetermined connection part when viewed in the direction of the specified single axis.

According to feature A8, even in a configuration in which the second predetermined wiring pattern is connected to the connection target at a location that is in the opposite direction to the direction in which the second predetermined wiring pattern is pulled out from the second predetermined connection part when viewed in the direction of a predetermined axis, the second predetermined wiring pattern is pulled out from the second predetermined connection part in the same direction as the direction in which the first predetermined wiring pattern is pulled out from the first predetermined connection part. This reduces the possibility of a difference in temperature distribution occurring within the pair of first and second predetermined connection parts during the initial heating stage of the reflow process.

Feature A9: The predetermined electronic component has a dimension in a first direction perpendicular to a thickness direction of the predetermined electronic component that is larger than a dimension in a second direction perpendicular to the thickness direction of the predetermined electronic component,
A gaming machine described in any one of features A1 to A8, characterized in that at least one of the direction of extension of the first predetermined wiring pattern from the first predetermined connection portion and the direction of extension of the second predetermined wiring pattern from the second predetermined connection portion is a direction perpendicular to the first direction or a direction approximately perpendicular to the first direction.

According to feature A9, when distortion occurs in the specified board, it is possible to reduce the maximum value of stress that can act on the connection point between the specified electronic component and the specified board, and to reduce the maximum value of stress that can act on the specified electronic component itself. This makes it possible to prevent damage to the connection point between the specified electronic component and the specified board, and to prevent damage to the specified electronic component itself.

Feature A10. The first predetermined connection portion, the second predetermined connection portion, the first predetermined wiring pattern, and the second predetermined wiring pattern are provided on a predetermined mounting surface (first mounting surface 84 of the first decorative substrate 56), which is a plate surface on one side of the predetermined substrate;
The gaming machine described in feature A9, wherein at least one of the first predetermined wiring pattern and the second predetermined wiring pattern is a wiring pattern that extends in a straight line on the predetermined mounting surface.

According to feature A10, at least one of the first and second predetermined wiring patterns extends linearly on the predetermined mounting surface. Therefore, in the event that distortion occurs in the predetermined board, it is possible to reduce the maximum value of stress that can act on the connection point between the predetermined electronic component and the predetermined board, and to reduce the maximum value of stress that can act on the predetermined electronic component itself. This makes it possible to prevent damage to the connection point between the predetermined electronic component and the predetermined board, and to prevent damage to the predetermined electronic component itself.

Feature A11. The specified substrate is provided with a non-penetrating specified via hole (via hole 174, 175) extending from the specified mounting surface in a thickness direction of the specified substrate, or a specified through hole (first through hole 383, second through hole 384) penetrating the specified substrate in a thickness direction,
The gaming machine described in feature A10, characterized in that at least one of the first specified wiring pattern and the second specified wiring pattern is a linear wiring pattern that electrically connects the first specified connection portion or the second specified connection portion to the specified via hole or the specified through hole on the specified mounting surface.

According to feature A11, by providing a specified via hole or a specified through hole in the specified substrate and making at least one of the first specified wiring pattern and the second specified wiring pattern a linear wiring pattern, when distortion occurs in the specified substrate, the maximum value of the stress that can act on the connection point between the specified electronic component and the specified substrate can be reduced, and the maximum value of the stress that can act on the specified electronic component itself can be reduced.

Feature A12. The predetermined substrate is
a third predetermined wiring pattern (second wiring patterns 172b, 294b, 386b) drawn out from the first predetermined connection portion;
a fourth predetermined wiring pattern (fourth wiring patterns 172d, 294d, 386d) drawn out from the second predetermined connection portion;
Equipped with
The predetermined electronic component has a dimension in a first direction perpendicular to a thickness direction of the predetermined electronic component that is larger than a dimension in a second direction perpendicular to the thickness direction of the predetermined electronic component,
A gaming machine described in any one of features A1 to A11, characterized in that the direction of pull-out of the first predetermined wiring pattern from the first predetermined connection portion, the direction of pull-out of the second predetermined wiring pattern from the second predetermined connection portion, the direction of pull-out of the third predetermined wiring pattern from the first predetermined connection portion, and the direction of pull-out of the fourth predetermined wiring pattern from the second predetermined connection portion are perpendicular or substantially perpendicular to the first direction.

According to feature A12, in a configuration in which the dimension in the first direction of the specified electronic component is greater than the dimension in the second direction, the direction of extension of the first specified wiring pattern from the first specified connection portion, the direction of extension of the second specified wiring pattern from the second specified connection portion, the direction of extension of the third specified wiring pattern from the first specified connection portion, and the direction of extension of the fourth specified wiring pattern from the second specified connection portion are perpendicular or substantially perpendicular to the first direction. Therefore, when distortion occurs in the specified board, the maximum value of the stress that can act on the connection point between the specified electronic component and the specified board can be reduced, and the maximum value of the stress that can act on the specified electronic component itself can be reduced.

Feature A13. The gaming machine according to any one of Features A1 to A12, characterized in that the specified electronic component is a capacitor (bypass capacitors 85 and 97 in the first embodiment, bypass capacitor 291 in the second embodiment, and bypass capacitor 381 in the fourth embodiment) or a resistor (small chip resistors 87 and 101 in the first embodiment).

According to feature A13, the configuration of feature A1 is provided, and the direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists as viewed from the center of the first predetermined connection part is the same as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists as viewed from the center of the second predetermined connection part. Therefore, the temperature distribution in the pair of first and second predetermined connection parts in the initial heating stage of the reflow process can be made uniform, and the manner in which the solder paste applied on the first and second predetermined connection parts melts can be made uniform. This makes it possible to prevent the capacitor or resistor from rotating around the normal direction of the specified substrate as the rotation axis, and to prevent the so-called chip standing, in which the capacitor or resistor stands up on one connection part (first or second predetermined connection part) with only one electrode (first or second predetermined electrode), can be prevented. Therefore, the electrical connection area between the first predetermined electrode and the first predetermined connection part can be secured, and the electrical connection area between the second predetermined electrode and the second predetermined connection part can be secured.

Feature A14. In a gaming machine having a predetermined board (the first decorative board 56, the second decorative board 57, and the light-emitting board 301 in the fourth embodiment) on which predetermined electronic components (the bypass capacitors 85 and 97 in the first embodiment, the small chip resistors 87 and 101, the bypass capacitor 291 in the second embodiment, and the bypass capacitor 381 in the fourth embodiment) are mounted,
The predetermined electronic component includes a pair of electrodes, that is, a first predetermined electrode (first electrodes 85a, 87a, 291a, 381a) and a second predetermined electrode (second electrodes 85b, 87b, 291b, 381b),
The predetermined substrate is
a first predetermined connection portion (first pad 171a, 176a, 293a, 382a) to which the first predetermined electrode is electrically connected;
a first predetermined wiring pattern (first wiring patterns 172a, 181a, 294a, 386a, second wiring patterns 172b, 294b, 386b) drawn out from the first predetermined connection portion;
second predetermined connection portions (second pads 171b, 176b, 293b, 382b) to which the second predetermined electrodes are electrically connected;
second predetermined wiring patterns (second wiring pattern 181b, third wiring pattern 172c, 294c, 386c, fourth wiring pattern 172d, 294d, 386d) drawn out from the second predetermined connection portion;
Equipped with
A gaming machine characterized in that the direction in which the first predetermined wiring pattern is drawn out from the first predetermined connection portion is the same as the direction in which the second predetermined wiring pattern is drawn out from the second predetermined connection portion.

According to feature A14, since the direction of drawing from the first predetermined connection part of the first predetermined wiring pattern is the same as the direction of drawing from the second predetermined connection part of the second predetermined wiring pattern, the possibility of a difference in temperature distribution in the pair of first and second predetermined connection parts in the initial heating stage of the reflow process can be reduced, and the manner in which the solder paste applied on the first and second predetermined connection parts melts can be made uniform. This prevents the specified electronic component from rotating around the normal direction of the specified board as the axis of rotation, and prevents the specified electronic component from standing up on one connection part (first specified connection part or second specified connection part) with only one electrode (first specified electrode or second specified electrode), which is called a chip standing. Therefore, the electrical connection area between the first specified electrode and the first specified connection part can be secured, and the electrical connection area between the second specified electrode and the second specified connection part can be secured.

Note that any one or more of the features A1 to A14, features B1 to B12, features C1 to C12, features D1 to D12, features E1 to E6, features F1 to F15, feature G1, and feature H1 may be applied to the features A1 to A14. This makes it possible to achieve a synergistic effect by combining the features.

<Characteristics Group B>
Feature B1. In a gaming machine equipped with a predetermined board (the first decorative board 56, the second decorative board 57, and the light-emitting board 301 in the fourth embodiment) on which a predetermined electronic component (the bypass capacitors 85 and 97 in the first embodiment, the small chip resistors 87 and 101, the bypass capacitor 291 in the second embodiment, and the bypass capacitor 381 in the fourth embodiment) is mounted,
The predetermined electronic component has a dimension in a first direction perpendicular to a thickness direction of the predetermined electronic component that is larger than a dimension in a second direction perpendicular to the thickness direction of the predetermined electronic component,
The predetermined substrate is
predetermined connection portions (first pads 171a, 176a, 293a, 382a; second pads 171b, 176b, 293b, 382b) to which the electrodes (first electrodes 85a, 87a, 291a, 381a; second electrodes 85b, 87b, 291b, 381b) of the predetermined electronic components are electrically connected;
Predetermined wiring patterns (first wiring patterns 172a, 181a, 294a, 386a, second wiring patterns 172b, 294b, 386b, second wiring pattern 181b, third wiring pattern 172c, 294c, 386c, fourth wiring pattern 172d, 294d, 386d) drawn out from the predetermined connection portions,
Equipped with
A gaming machine characterized in that the direction in which the specified wiring pattern is drawn out from the specified connection portion is a direction perpendicular or substantially perpendicular to the first direction.

According to feature B1, the direction in which the specified wiring pattern is drawn out from the specified connection portion is perpendicular or substantially perpendicular to the first direction. Therefore, in the event that distortion occurs in the specified board, the maximum value of stress that can act on the connection point between the specified electronic component and the specified board can be reduced, and the maximum value of stress that can act on the specified electronic component itself can be reduced. This makes it possible to prevent damage to the connection point between the specified electronic component and the specified board. Furthermore, by reducing the maximum value of stress that can act on the specified electronic component itself, it is possible to prevent damage to the specified electronic component itself.

Feature B2. The predetermined connection portion and the predetermined wiring pattern are provided on a predetermined mounting surface (the first mounting surface 84 of the first decorative substrate 56), which is a plate surface on one side of the predetermined substrate;
The gaming machine described in feature B1, wherein the specified wiring pattern is a wiring pattern that extends in a straight line on the specified mounting surface.

According to feature B2, the specified wiring pattern extends linearly on the specified mounting surface. Therefore, in the event that distortion occurs in the specified board, it is possible to reduce the maximum value of stress that can act on the connection point between the specified electronic component and the specified board, and also to reduce the maximum value of stress that can act on the specified electronic component itself. This makes it possible to prevent damage to the connection point between the specified electronic component and the specified board, and also to prevent damage to the specified electronic component itself.

Feature B3: The predetermined substrate is provided with a non-penetrating predetermined via hole (via hole 174, 175) extending from the predetermined mounting surface in a thickness direction of the predetermined substrate, or a predetermined through hole (first through hole 383, second through hole 384) penetrating the predetermined substrate in a thickness direction,
The gaming machine described in feature B2, wherein the specified wiring pattern is a linear wiring pattern that electrically connects the specified connection portion and the specified via hole or the specified through hole on the specified mounting surface.

According to feature B3, by providing a specified via hole or a specified through hole in the specified substrate and making the specified wiring pattern a linear wiring pattern, when distortion occurs in the specified substrate, it is possible to reduce the maximum value of the stress that can act on the connection point between the specified electronic component and the specified substrate, and also to reduce the maximum value of the stress that can act on the specified electronic component itself.

Feature B4: The predetermined electronic component includes a first predetermined electrode (first electrode 85a, 87a, 291a, 381a) and a second predetermined electrode (second electrode 85b, 87b, 291b, 381b),
The predetermined substrate is
a first predetermined connection portion (first pad 171a, 176a, 293a, 382a) which is the predetermined connection portion to which the first predetermined electrode is electrically connected;
a first predetermined wiring pattern (first wiring patterns 172a, 181a, 294a, 386a, second wiring patterns 172b, 294b, 386b) which is the predetermined wiring pattern electrically connected to the first predetermined connection portion;
a second predetermined connection portion (second pad 171b, 176b, 293b, 382b) which is the predetermined connection portion to which the second predetermined electrode is electrically connected;
second predetermined wiring patterns (second wiring pattern 181b, third wiring pattern 172c, 294c, 386c, fourth wiring pattern 172d, 294d, 386d) which are the predetermined wiring patterns electrically connected to the second predetermined connection portion;
Equipped with
A gaming machine described in any one of features B1 to B3, characterized in that the direction in which the first predetermined wiring pattern is drawn out from the first predetermined connection portion and the direction in which the second predetermined wiring pattern is drawn out from the second predetermined connection portion are perpendicular or substantially perpendicular to the first direction.

According to feature B4, the direction of drawing from the first predetermined connection portion of the first predetermined wiring pattern and the direction of drawing from the second predetermined connection portion of the second predetermined wiring pattern are perpendicular or substantially perpendicular to the first direction. Therefore, when distortion occurs in the specified board, the maximum value of stress that can act on the connection point between the specified electronic component and the specified board can be reduced, and the maximum value of stress that can act on the specified electronic component itself can be reduced. This makes it possible to prevent damage to the connection point between the specified electronic component and the specified board. Furthermore, by reducing the maximum value of stress that can act on the specified electronic component itself, it is possible to prevent damage to the specified electronic component itself.

Feature B5. The gaming machine described in Feature B4, characterized in that the direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists when viewed from the center of the first predetermined connection part is the same direction as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection part.

According to feature B5, the temperature distribution in the first and second predetermined connection parts during the initial heating stage of the reflow process can be made uniform, and the manner in which the solder paste applied to the first and second predetermined connection parts melts can be made uniform. This prevents the specified electronic component from rotating around the normal direction of the specified substrate as the axis of rotation, and prevents the specified electronic component from standing up on one connection part (the first or second specified connection part) with only one electrode (the first or second specified electrode), a phenomenon known as chip standing. This ensures the electrical connection area between the first and first predetermined connection parts, and the electrical connection area between the second and second predetermined connection parts.

Feature B6. The gaming machine described in Feature B4 or B5, characterized in that the specified electronic component has the first specified electrode and the second specified electrode as a pair of electrodes.

According to feature B6, the configuration of feature B4 is provided, and the direction in which the lead-out position from the first predetermined connection part of the first predetermined wiring pattern exists as viewed from the center of the first predetermined connection part is the same as the direction in which the lead-out position from the second predetermined connection part of the second predetermined wiring pattern exists as viewed from the center of the second predetermined connection part, so that the temperature distribution in the pair of first predetermined connection parts and second predetermined connection parts in the initial heating stage of the reflow process can be made uniform, and the manner in which the solder paste applied on the pair of first predetermined connection parts and second predetermined connection parts melts can be made uniform. This makes it possible to prevent the specified electronic component from rotating around the normal direction of the specified board as the rotation axis, and to prevent the occurrence of so-called chip standing, in which the specified electronic component stands up on one connection part (first specified connection part or second specified connection part) with only one electrode (first specified electrode or second specified electrode). Therefore, it is possible to ensure the electrical connection area between the first specified electrode and the first specified connection part, and to ensure the electrical connection area between the second specified electrode and the second specified connection part.

Feature B7: The first predetermined connection portion is electrically connected to a first metal region (GND plane layer 93) having an area larger than that of the first predetermined connection portion via the first predetermined wiring pattern,
A gaming machine described in any one of features B4 to B6, characterized in that the second specified connection portion is electrically connected to a second metal region (power supply plane layer 94) having a larger area than the second specified connection portion via the second specified wiring pattern.

According to feature B7, in the specified connection part (first specified connection part or second specified connection part), the side where the pull-out part of the specified wiring pattern (first specified wiring pattern or second specified wiring pattern) that is electrically connected to the large-area metal region (first metal region or second metal region) is located is prone to a delayed temperature rise in the initial heating stage of the reflow process, but the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the first specified connection part is the same direction as the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the second specified connection part. This makes it possible to align the temperature distribution in the first specified connection part and the second specified connection part in the initial heating stage.

Feature B8. The wiring pattern drawn out from the first predetermined connection portion is only the first predetermined wiring pattern,
A gaming machine according to any one of features B4 to B7, characterized in that the wiring pattern drawn out from the second predetermined connection portion is only the second predetermined wiring pattern.

According to Feature B8, in a configuration having the configuration of Feature B4, in which the direction of drawing of the first predetermined wiring pattern from the first predetermined connection portion and the direction of drawing of the second predetermined wiring pattern from the second predetermined connection portion are perpendicular or substantially perpendicular to the first direction, the wiring pattern drawn from the first predetermined connection portion is only the first predetermined wiring pattern, and the wiring pattern drawn from the second predetermined connection portion is only the second predetermined wiring pattern. Therefore, when distortion occurs in the specified board, the maximum value of the stress that can act on the connection point between the specified electronic component and the specified board can be reduced, and the maximum value of the stress that can act on the specified electronic component itself can be reduced.

Feature B9. The predetermined substrate is
a third predetermined wiring pattern (second wiring patterns 172b, 294b, 386b) drawn out from the first predetermined connection portion;
a fourth predetermined wiring pattern (fourth wiring patterns 172d, 294d, 386d) drawn out from the second predetermined connection portion;
Equipped with
A gaming machine described in any one of features B4 to B7, characterized in that the direction in which the third predetermined wiring pattern is pulled out from the first predetermined connection portion and the direction in which the fourth predetermined wiring pattern is pulled out from the second predetermined connection portion are perpendicular or substantially perpendicular to the first direction.

According to feature B9, the first, second, third, and fourth predetermined wiring patterns extend in a direction perpendicular or substantially perpendicular to the first direction. Therefore, when distortion occurs in the specified board, the maximum value of stress that can act on the connection points between the specified electronic component and the specified board can be reduced, and the maximum value of stress that can act on the specified electronic component itself can be reduced. This prevents damage to the connection points between the specified electronic component and the specified board, and prevents damage to the specified electronic component itself.

Feature B10: A direction in which a side of the first predetermined connection part, from which the first predetermined wiring pattern is drawn, exists when viewed from a center of the first predetermined connection part is the same as a direction in which a side of the second predetermined connection part, from which the second predetermined wiring pattern is drawn, exists when viewed from a center of the second predetermined connection part;
The gaming machine described in feature B9 is characterized in that the direction in which the side of the first specified connection part from which the third specified wiring pattern is pulled out exists when viewed from the center of the first specified connection part is the same as the direction in which the side of the second specified connection part from which the fourth specified wiring pattern is pulled out exists when viewed from the center of the second specified connection part.

According to feature B10, in the configuration of feature B4, the direction in which the lead-out position from the first predetermined connection part of the first predetermined wiring pattern exists as viewed from the center of the first predetermined connection part is the same as the direction in which the lead-out position from the second predetermined connection part of the second predetermined wiring pattern exists as viewed from the center of the second predetermined connection part, and the direction in which the lead-out position from the first predetermined connection part of the third predetermined wiring pattern exists as viewed from the center of the first predetermined connection part is the same as the direction in which the lead-out position from the second predetermined connection part of the fourth predetermined wiring pattern exists as viewed from the center of the second predetermined connection part. Therefore, it is possible to make the temperature distribution in the first predetermined connection part and the second predetermined connection part uniform in the initial heating stage of the reflow process, and to make the manner in which the solder paste applied on these first predetermined connection part and the second predetermined connection part melt uniform. This makes it possible to prevent the predetermined electronic component from rotating around the normal direction of the predetermined substrate as the rotation axis, and to prevent the occurrence of so-called chip standing, in which the predetermined electronic component stands up on one predetermined connection part only with one predetermined electrode. Therefore, it is possible to ensure the electrical connection area between the predetermined electrode and the predetermined connection part.

Feature B11: The first predetermined connection portion is electrically connected to a first metal region (GND plane layer 93) having an area larger than that of the first predetermined connection portion via the first predetermined wiring pattern,
the third predetermined wiring pattern is not connected to a metal region having an area larger than that of the first predetermined connection portion,
the second predetermined connection portion is electrically connected to a second metal region (power supply plane layer 94) having an area larger than that of the second predetermined connection portion via the second predetermined wiring pattern;
The gaming machine according to feature B9 or B10, wherein the fourth predetermined wiring pattern is not connected to a metal region having a larger area than the second predetermined connection portion.

According to feature B11, among the first and third predetermined wiring patterns drawn from the first predetermined connection part, only the first predetermined wiring pattern is connected to a metal area having a larger area than the first predetermined connection part, and among the second and fourth predetermined wiring patterns drawn from the second predetermined connection part, only the second predetermined wiring pattern is connected to a metal area having a larger area than the second predetermined connection part. Therefore, in the initial heating stage of the reflow process, the possibility of a difference occurring between the manner in which the temperature of the first predetermined wiring pattern rises and the manner in which the temperature of the second predetermined wiring pattern rises can be reduced. In addition, the third wiring pattern drawn from the first predetermined connection part and the fourth predetermined wiring pattern drawn from the second predetermined connection part are not electrically connected to the large metal area. Therefore, in the initial heating stage of the reflow process, the possibility of a difference occurring between the manner in which the temperature of the third predetermined wiring pattern rises and the manner in which the temperature of the fourth predetermined wiring pattern rises can be reduced. This makes it possible to prevent a difference from occurring between the temperature distribution in the first predetermined connection part and the temperature distribution in the second predetermined connection part.

Feature B12. A gaming machine according to any one of Features B1 to B11, characterized in that the specified electronic component is a capacitor (bypass capacitors 85 and 97 in the first embodiment, bypass capacitor 291 in the second embodiment, and bypass capacitor 381 in the fourth embodiment) or a resistor (small chip resistors 87 and 101 in the first embodiment).

According to feature B12, the configuration of feature B1 is provided, and the direction of drawing from the specified connection part of the specified wiring pattern is perpendicular or substantially perpendicular to the first direction. Therefore, in the case where distortion occurs in the specified board, the maximum value of stress that can act on the connection point between the capacitor or resistor and the specified board can be reduced, and the maximum value of stress that can act on the capacitor or resistor itself can be reduced. By reducing the maximum value of stress that can act on the connection point between the capacitor or resistor and the specified board, damage to the connection point between the capacitor or resistor and the specified board can be prevented. In addition, by reducing the maximum value of stress that can act on the capacitor or resistor itself, damage to the capacitor or resistor itself can be prevented.

Note that any one or more of the features A1 to A14, features B1 to B12, features C1 to C12, features D1 to D12, features E1 to E6, features F1 to F15, feature G1, and feature H1 may be applied to the features B1 to B12. This makes it possible to achieve a synergistic effect by combining the features.

<Characteristics Group C>
Feature C1. In a gaming machine having a predetermined board (first decorative board 56, light-emitting board 301) on which a first predetermined electronic component (connectors 111, 112 in the first embodiment, second LED driver 326, connector 327, LED chips 315 to 325 in the third embodiment) and a second predetermined electronic component smaller than the first predetermined electronic component (bypass capacitor 85, small chip resistor 87 in the first embodiment, bypass capacitor 328, small chip resistors 331 to 335 in the third embodiment) are mounted,
The first predetermined electronic component is mounted on a first predetermined plate surface (a second mounting surface 95, a second light emitting surface 303) which is a plate surface on one side of the predetermined board,
the second predetermined electronic component is mounted on a second predetermined plate surface (first mounting surface 84, first light emitting surface 302) side opposite to the first predetermined plate surface of the predetermined board,
A gaming machine characterized in that the second specified electronic component is not mounted in an area on the back side of the area on the first specified board surface where the first specified electronic component is mounted.

According to feature C1, the second specified electronic component is not mounted in the area on the rear side of the area on the first specified board surface where the first specified electronic component is mounted. Therefore, when stress that distorts the specified board acts on the rear side area, it is possible to prevent the connection between the second specified electronic component and the specified board from being damaged by the influence of the stress, and it is also possible to prevent the second specified electronic component itself from being damaged.

Feature C2. The gaming machine described in Feature C1, characterized in that the second specified electronic components are not mounted in any area of the second specified board surface that is less than a specified distance from the area behind the area on the first specified board surface where the first specified electronic components are mounted (connector back-side corresponding areas 203, 204, driver back-side corresponding area 354, LED back-side corresponding areas 361-371).

According to feature C2, the second specified electronic components are not mounted in an area on the second specified board surface that is less than a specified distance from the area on the back side of the area on the first specified board surface where the first specified electronic components are mounted. Therefore, when stress that distorts the specified board acts on the area that is less than a specified distance from the area on the back side, it is possible to prevent the connection points between the second specified electronic components and the specified board from being damaged by the influence of the stress, and also to prevent the second specified electronic components themselves from being damaged.

Feature C3. A specific electronic component (LED chip 310) larger than the second specific electronic component is mounted on the second specific plate surface side of the specific substrate,
The gaming machine described in feature C2 is characterized in that the specific electronic component is mounted in an area (LED back corresponding area 368) on the second specified board surface that is less than a specified distance from an area on the back side of the area on the first specified board surface where the first specified electronic component is mounted.

According to feature C3, in a configuration having the configuration of feature C2, in which the second specified electronic component is not mounted in an area on the second specified board surface that is less than a specified distance from the area on the back side of the area on the first specified board surface where the first specified electronic component is mounted, the specific electronic component is mounted in an area that is less than a specified distance from the area on the back side. This makes it possible to secure a large area on the second specified board surface in which a specific electronic component larger than the second specified electronic component can be placed.

Feature C4: A specific electronic component (LED chip 310) larger than the second specific electronic component is mounted on the second specific plate surface side of the specific substrate,
A gaming machine described in any one of features C1 to C3, characterized in that the specific electronic component is mounted in an area on the second specified board surface behind the area in which the first specified electronic component is mounted on the first specified board surface.

According to feature C4, in a configuration having the configuration of feature C1, in which a second specified electronic component is not mounted in an area on the back side of an area on the first specified board surface where a first specified electronic component is mounted, a specific electronic component is mounted in the area on the back side. This makes it possible to secure a large area on the second specified board surface in which a specific electronic component larger than the second specified electronic component can be arranged.

Feature C5. The predetermined substrate is
A specific connection portion (a pad connected to a power supply terminal 348 of the second LED driver 326 and a pad connected to a GND terminal 349) connected to an electrode of the first predetermined electronic component;
a predetermined connection portion (a first pad 382a, a second pad 382b) connected to electrodes of the second predetermined electronic component (electrodes 381a, 381b of the bypass capacitor 381);
A predetermined wiring pattern (a second wiring pattern 386b, a fourth wiring pattern 386d) that electrically connects the predetermined connection portion and the specific connection portion;
Equipped with
the predetermined wiring pattern is electrically connected to the predetermined connection portion on the second predetermined plate surface outside a region on a rear side of a region on the first predetermined plate surface on which the first predetermined electronic component is mounted,
A gaming machine described in any one of features C1 to C4, characterized in that the second specified electronic component is not mounted in the area on the back side of the area on the first specified board surface where the first specified electronic component is mounted (the area where the second LED driver 326 is mounted) on the second specified board surface.

According to feature C5, the specified wiring pattern is extended on the second specified plate surface to outside the area behind the area on the first specified plate surface where the first specified electronic component is mounted, and electrically connected to the specified connection portion, thereby preventing the second specified electronic component from being placed in the area behind the area.

Feature C6. A gaming machine according to any one of Features C1 to C5, characterized in that the second specified electronic component is not mounted in a specified outer edge area (an area less than 10 mm from the outer edge of the first decorative substrate 56) that is less than a specified distance from the outer edge of the specified substrate.

According to feature C6, the second specified electronic component is arranged on the specified board, avoiding the specified outer edge region. This reduces the possibility that the connection between the second specified electronic component and the specified board or the second specified electronic component itself will be damaged when the worker's hand accidentally touches the second specified electronic component when handling the specified board. In addition, in a method for manufacturing a specified board in which a collective board containing multiple specified boards is divided to extract multiple specified boards, it is possible to reduce stress that may act on the connection between the second specified electronic component and the specified board when dividing the collective board, and to reduce stress that may act on the second specified electronic component itself. This prevents damage to the connection between the second specified electronic component and the specified board when dividing the collective board, and prevents damage to the second specified electronic component itself.

Feature C7. The gaming machine described in Feature C6, characterized in that the first specified electronic component is mounted in the specified outer edge region.

According to feature C7, in a configuration having the configuration of feature C6 above, in which the second specified electronic component is not mounted in the specified outer edge region, by mounting the first specified electronic component in the specified outer edge region, it is possible to ensure a larger area of the region on the specified board in which the first specified electronic component can be mounted, compared to a configuration in which neither the second specified electronic component nor the first specified electronic component is mounted in the specified outer edge region.

Feature C8. The predetermined substrate is provided with a substrate fixing portion (fixing through holes 56d to 56g) for fixing the predetermined substrate,
A gaming machine described in any one of features C1 to C7, characterized in that the second specified electronic component is not mounted in the fixing portion peripheral area (through hole peripheral area 211a to 211d) that is less than a specific distance away from the substrate fixing portion.

According to feature C8, the second specified electronic component is positioned to avoid the peripheral area of the fixed portion, which reduces stress that may act on the connection point between the second specified electronic component and the specified board when the specified board is fixed, and also reduces stress that may act on the second specified electronic component itself.

Feature C9. The gaming machine described in Feature C8, characterized in that the first predetermined electronic component is mounted in the peripheral area of the fixed portion.

According to feature C9, in a configuration having the configuration of feature C8 above, in which the second specified electronic component is not mounted in the peripheral region of the fixed portion, by mounting the first specified electronic component in the peripheral region of the fixed portion, it is possible to ensure a larger area of the region on the specified board in which the first specified electronic component can be mounted, compared to a configuration in which neither the second specified electronic component nor the first specified electronic component is mounted in the peripheral region of the fixed portion.

Feature C10. In the first predetermined board surface of the predetermined board, the second predetermined electronic component is not mounted in a predetermined outer edge region (a region less than 10 mm from the outer edge of the first decorative board 56) that is less than a predetermined distance from the outer edge of the predetermined board;
The gaming machine described in feature C8 or C9, wherein the substrate fixing portion is provided in the specified outer edge region.

According to feature C10, by arranging the fixing portion in the predetermined outer edge region where the second predetermined electronic component cannot be arranged, it is possible to ensure a large area of the area on the predetermined board where the second predetermined electronic component can be mounted. Also, in a method for manufacturing a predetermined board in which a collective board containing multiple predetermined boards is divided to extract multiple predetermined boards, it is possible to reduce stress that may act on the connection points between the second predetermined electronic component and the predetermined board when dividing the collective board, and to reduce stress that may act on the second predetermined electronic component itself. This makes it possible to prevent damage to the connection points between the second predetermined electronic component and the predetermined board when dividing the collective board, and to prevent damage to the second predetermined electronic component itself. By providing the fixing portion on the outer edge, it is possible to reduce the area of the area on the predetermined board where the second predetermined electronic component cannot be mounted.

Feature C11. The gaming machine described in any one of Features C1 to C10, characterized in that the first specified electronic component is a connector (connector 111, 112, 327), an IC (second LED driver 326), or an LED chip (LED chips 315 to 325).

According to feature C11, when the first specified electronic component is a connector, it is possible to reduce the tensile stress that may act on the connection point between the second specified electronic component and the specified board when the harness is attached to the connector, and to reduce the compressive stress that may act on the connection point between the second specified electronic component and the specified board when the harness is removed from the connector. This makes it possible to prevent the connection point between the second specified electronic component and the specified board from being damaged when the harness is attached to or detached from the connector, and to prevent the second specified electronic component itself from being damaged. In addition, when the first specified electronic component is an IC, since the IC is configured to be arranged avoiding the specified back side area, when the IC generates heat and thermal stress acts on the specified board, it is possible to prevent the connection point between the second specified electronic component and the specified board from being damaged due to the influence of the stress, and to prevent the second specified electronic component itself from being damaged. Furthermore, when the first specified electronic component includes an LED chip, the LED chip is arranged to avoid the specified backside area, so that when the LED chip generates heat and thermal stress acts on the specified substrate, the connection between the second specified electronic component and the specified substrate can be prevented from being damaged by the stress, and the second specified electronic component itself can be prevented from being damaged.

Feature C12. The gaming machine according to any one of Features C1 to C11, characterized in that the second specified electronic component is a capacitor (bypass capacitors 85 and 97 in the first embodiment, bypass capacitor 291 in the second embodiment, and bypass capacitor 381 in the fourth embodiment) or a resistor (small chip resistors 87 and 101 in the first embodiment).

According to feature C12, the configuration of feature C1 is provided, and no capacitors or resistors are mounted in the area on the back side of the area on the first specified board surface where the first specified electronic component is mounted on the first specified board surface. Therefore, when stress that distorts the specified board acts on the back side area, it is possible to prevent the connection between the capacitor or resistor and the specified board from being damaged by the influence of the stress, and also to prevent the capacitor or resistor itself from being damaged.

Note that any one or more of the features A1 to A14, features B1 to B12, features C1 to C12, features D1 to D12, features E1 to E6, features F1 to F15, feature G1, and feature H1 may be applied to the features C1 to C12. This makes it possible to achieve a synergistic effect by combining the features.

<Feature D group>
Feature D1. In a gaming machine equipped with a predetermined board (first decorative board 56, second decorative board 57, light-emitting board 301),
The predetermined substrate is mounted with a first predetermined electronic component (connectors 111, 112 in the first embodiment, second LED driver 326, connector 327, and LED chips 315 to 325 in the third embodiment) and a plurality of second predetermined electronic components smaller than the first predetermined electronic component (bypass capacitor 85 and small chip resistor 87 in the first embodiment, bypass capacitor 328 and small chip resistors 331 to 335 in the third embodiment),
The gaming machine is characterized in that the plurality of second specified electronic components are mounted on a first plate surface (first mounting surface 84, first light-emitting surface 302), which is one plate surface of the specified board, and are not mounted on a second plate surface (second mounting surface 95, second light-emitting surface 303), which is the plate surface on the opposite side of the specified board to the first plate surface.

According to feature D1, the second predetermined electronic components are concentrated on the first plate surface side of the predetermined board, and are not mounted on the second plate surface side. Therefore, by handling the predetermined board so that the stress acting on the first plate surface side of the predetermined board is minimized, it is possible to prevent the connection points between the second predetermined electronic components and the predetermined board from being damaged, and also to prevent the second predetermined electronic components themselves from being damaged. For example, in a method for manufacturing a predetermined board in which a collective board in which a plurality of predetermined boards are connected is divided to extract the plurality of predetermined boards, by dividing the collective board so that the first plate surface on which the second predetermined electronic components are mounted has a valley shape (concave), it is possible to prevent tensile stress from acting on the connection points between the second predetermined electronic components and the predetermined board, and also to prevent tensile stress from acting on the second predetermined electronic components themselves. In addition, it is possible to reduce stress that may act on the connection points between the second predetermined electronic components and the predetermined board, and also to reduce stress that may act on the second predetermined electronic components themselves. This prevents damage to the connection points between the second specified electronic components and the specified board when the collective board is divided, and also prevents damage to the second specified electronic components themselves.

Feature D2: A plurality of the first predetermined electronic components are mounted on the predetermined substrate,
some of the plurality of first predetermined electronic components are mounted on the second plate surface side,
A gaming machine described in feature D1, characterized in that other parts of the plurality of first specified electronic components are mounted on the first panel surface side.

According to feature D2, in a configuration in which the first predetermined electronic component is mounted on both the first plate surface side and the second plate surface side of the predetermined board, the configuration includes the above feature D1, and the multiple second predetermined electronic components are concentrated on the first plate surface side of the predetermined board and are not mounted on the second plate surface side. Even in a configuration in which the first predetermined electronic component is mounted on both the first plate surface side and the second plate surface side of the predetermined board, the second predetermined electronic components are concentrated on the first plate surface side of the predetermined board, so that by handling the predetermined board so that the stress acting on the first plate surface side of the predetermined board is minimized, it is possible to prevent damage to the connection between the second predetermined electronic component and the predetermined board, and to prevent damage to the second predetermined electronic component itself. In addition, by configuring the first predetermined electronic component to be mounted on both the first plate surface side and the second plate surface side of the predetermined board, it is possible to increase the degree of freedom in arranging the first predetermined electronic component on the predetermined board.

Feature D3. The gaming machine described in Feature D1 or D2, characterized in that the second specified electronic component is not mounted in the area on the first plate surface behind the area on the second plate surface where the first specified electronic component is mounted.

According to feature D3, when stress that distorts the specified board acts on the area on the first board surface behind the area on the second board surface where the first specified electronic component is mounted, the connection point between the second specified electronic component and the specified board can be prevented from being damaged by the influence of the stress, and the second specified electronic component itself can be prevented from being damaged.

Feature D4. The predetermined substrate is
A specific connection portion (a pad connected to a power supply terminal 348 of the second LED driver 326 and a pad connected to a GND terminal 349) electrically connected to an electrode of the first predetermined electronic component;
a predetermined connection portion (a first pad 382a, a second pad 382b) electrically connected to electrodes of the second predetermined electronic component (electrodes 381a, 381b of the bypass capacitor 381);
Equipped with
A gaming machine described in any one of features D1 to D3, characterized in that the specified connection portion and the specific connection portion are electrically connected.

According to feature D4, by arranging a second specified electronic component, which is electrically connected to a first specified electronic component mounted on the second plate surface side, on the first plate surface side opposite the second plate surface, it is possible to aggregate the second specified electronic components on the first plate surface side and to configure the second specified electronic components not to be mounted on the second plate surface side.

Feature D5. The predetermined substrate is
A specific connection portion (a pad connected to a power supply terminal 348 of the second LED driver 326 and a pad connected to a GND terminal 349) connected to an electrode of the first predetermined electronic component;
a predetermined connection portion (a first pad 382a, a second pad 382b) connected to electrodes of the second predetermined electronic component (electrodes 381a, 381b of the bypass capacitor 381);
A predetermined wiring pattern (a second wiring pattern 386b, a fourth wiring pattern 386d) that electrically connects the predetermined connection portion and the specific connection portion;
Equipped with
the predetermined wiring pattern is electrically connected to the predetermined connection portion on the first plate surface outside a region on the rear side of a region on the second plate surface on which the first predetermined electronic component is mounted,
A gaming machine described in any one of features D1 to D4, characterized in that the second specified electronic component is not mounted in the area on the back side of the area on the first panel surface where the first specified electronic component is mounted (the area where the second LED driver 326 is mounted) on the second panel surface.

According to feature D5, the specified wiring pattern is extended on the first plate surface to outside the area behind the area on the second plate surface where the first specified electronic component is mounted, and electrically connected to the specified connection portion, thereby preventing the second specified electronic component from being placed in the area behind the area.

Feature D6. A gaming machine according to any one of Features D1 to D5, characterized in that the second specified electronic component is a capacitor (bypass capacitors 85 and 97 in the first embodiment, bypass capacitor 291 in the second embodiment, and bypass capacitor 381 in the fourth embodiment) or a resistor (small chip resistors 87 and 101 in the first embodiment).

According to feature D6, the configuration of feature D1 is provided, and the capacitors or resistors are concentrated on the first plate surface side of the specified board, and are not mounted on the second plate surface side. Therefore, by handling the specified board so that the stress acting on the first plate surface side of the specified board is minimized, it is possible to prevent the connection points between the capacitors or resistors and the specified board from being damaged, and also to prevent the capacitors or resistors themselves from being damaged. For example, in a method of manufacturing a specified board in which a collective board in which multiple specified boards are connected is divided to extract multiple specified boards, by dividing the collective board so that the first plate surface on which the capacitors or resistors are mounted has a valley shape (concave), it is possible to prevent tensile stress from acting on the connection points between the capacitors or resistors and the specified board, and also to prevent tensile stress from acting on the capacitors or resistors themselves. In addition, it is possible to reduce stress that may act on the connection points between the capacitors or resistors and the specified board, and also to reduce stress that may act on the capacitors or resistors themselves. This prevents damage to the connections between the capacitors or resistors and the specified substrates when the assembly substrate is divided, and also prevents damage to the capacitors or resistors themselves.

Feature D7. A gaming machine according to any one of Features D1 to D6, characterized in that the second specified electronic component is not mounted in a specified outer edge region (a region less than 10 mm from the outer edge of the first decorative substrate 56) that is less than a specified distance from the outer edge of the specified substrate.

According to feature D7, the second specified electronic component is arranged on the specified board, avoiding the specified outer edge region. This reduces the possibility that the operator's hand will accidentally touch the second specified electronic component when handling the specified board, causing damage to the connection points between the second specified electronic component and the specified board or the second specified electronic component itself. In addition, in a method for manufacturing a specified board in which a collective board containing multiple specified boards is divided to extract multiple specified boards, it is possible to reduce stress that may act on the connection points between the second specified electronic component and the specified board when dividing the collective board, and to reduce stress that may act on the second specified electronic component itself. This prevents damage to the connection points between the second specified electronic component and the specified board when dividing the collective board, and prevents damage to the second specified electronic component itself.

Feature D8. The gaming machine described in Feature D7, characterized in that the first specified electronic component is mounted in the specified outer edge region.

According to feature D8, in a configuration having the configuration of feature D7 above, in which a second specified electronic component is not mounted in the specified outer edge region, by mounting a first specified electronic component in the specified outer edge region, it is possible to ensure a larger area of the region on the specified board in which the first specified electronic component can be mounted, compared to a configuration in which neither the second specified electronic component nor the first specified electronic component is mounted in the specified outer edge region.

Feature D9. The predetermined substrate is provided with a substrate fixing portion (fixing through holes 56d to 56g) for fixing the predetermined substrate,
A gaming machine described in any one of features D1 to D8, characterized in that the second specified electronic component is arranged to avoid the peripheral area (through hole peripheral area 211a to 211d) of the fixed portion that is less than a specific distance away from the substrate fixed portion.

According to feature D9, the second specified electronic component is positioned to avoid the peripheral area of the fixed portion, which reduces stress that may act on the connection point between the second specified electronic component and the specified board when the specified board is fixed, and also reduces stress that may act on the second specified electronic component itself.

Feature D10. The gaming machine described in Feature D9, characterized in that the first predetermined electronic component is mounted in the peripheral area of the fixed portion.

According to feature D10, in a configuration having the configuration of feature D9 above, in which the second specified electronic component is not mounted in the peripheral region of the fixed portion, by mounting the first specified electronic component in the peripheral region of the fixed portion, it is possible to ensure a larger area of the region on the specified board in which the first specified electronic component can be mounted, compared to a configuration in which neither the second specified electronic component nor the first specified electronic component is mounted in the peripheral region of the fixed portion.

Feature D11. The second electronic component is not mounted in a predetermined peripheral region (a region less than 10 mm from the peripheral edge of the first decorative substrate 56) on the first plate surface of the predetermined substrate, the second electronic component being mounted in the predetermined peripheral region (a region less than 10 mm from the peripheral edge of the first decorative substrate 56) that is less than a predetermined distance from the peripheral edge of the predetermined substrate,
An amusement machine described in feature D9 or D10, characterized in that the substrate fixing portion is provided in the specified outer edge region.

According to feature D11, by arranging the fixing portion in the predetermined outer edge region where the second predetermined electronic component cannot be arranged, it is possible to ensure a large area of the area on the predetermined board where the second predetermined electronic component can be mounted. Also, in a method for manufacturing a predetermined board in which a collective board containing multiple predetermined boards is divided to extract multiple predetermined boards, it is possible to reduce stress that may act on the connection points between the second predetermined electronic component and the predetermined board when dividing the collective board, and to reduce stress that may act on the second predetermined electronic component itself. This makes it possible to prevent damage to the connection points between the second predetermined electronic component and the predetermined board when dividing the collective board, and to prevent damage to the second predetermined electronic component itself. By providing the fixing portion on the outer edge, it is possible to reduce the area of the area on the predetermined board where the second predetermined electronic component cannot be mounted.

Feature D12. A gaming machine according to any one of Features D1 to D11, characterized in that it has at least one of the following configurations: a specific capacitor (bypass capacitor 352 in the third embodiment) is mounted as the first specific electronic component on the second plate surface side of the specific board, and a specific capacitor (bypass capacitor 328 in the third embodiment) is mounted as the second specific electronic component on the first plate surface side of the specific board; and a specific resistor (chip resistors 336 to 346 in the third embodiment) is mounted as the first specific electronic component on the second plate surface side of the specific board, and a specific resistor (small chip resistors 331 to 335 in the third embodiment) is mounted as the second specific electronic component on the first plate surface side of the specific board.

According to feature D12, in a configuration in which a specific capacitor, which is a first specific electronic component, and a specific capacitor, which is a second specific electronic component, are mounted on a specific board, by arranging the specific capacitor on the first board surface side, it is possible to consolidate the second specific electronic component on the first board surface side, and to achieve a state in which the second specific electronic component is not mounted on the second board surface side. Also, in a configuration in which a specific resistor, which is a first specific electronic component, and a specific resistor, which is a second specific electronic component, are mounted on a specific board, by arranging the specific resistor on the first board surface side, it is possible to consolidate the second specific electronic component on the first board surface side, and to achieve a state in which the second specific electronic component is not mounted on the second board surface side.

Note that any one or more of the features A1 to A14, features B1 to B12, features C1 to C12, features D1 to D12, features E1 to E6, features F1 to F15, feature G1, and feature H1 may be applied to the features D1 to D12. This makes it possible to achieve a synergistic effect by combining the features.

<Features Group E>
Feature E1. In a gaming machine equipped with a predetermined board (first decorative board 56),
The predetermined substrate is mounted with a first predetermined electronic component (LED driver 126, LED chip 142) and a second predetermined electronic component (bypass capacitor 85, small chip resistor 87) smaller than the first predetermined electronic component,
a resist is provided between a plurality of connection portions (first pads 178 a, second pads 178 b) to which a plurality of electrodes (terminals 151 to 162, first electrode 142 a, second electrode 142 b) of the first predetermined electronic component are electrically connected on the predetermined substrate;
the resist is not provided between a plurality of connection portions (first pad 171 a, first pad 176 a, second pad 171 b, second pad 176 b) to which a plurality of electrodes (first electrodes 85 a, 87 a, second electrodes 85 b, 87 b) of the second predetermined electronic component are electrically connected on the predetermined substrate,
a contour mark (contour silk 213, 215) for dividing an area on the predetermined board on which the first predetermined electronic component is mounted is provided around the area;
A gaming machine, characterized in that there is no outline marking to define the area around the area on the specified board on which the second specified electronic component is mounted.

According to feature E1, in visual inspection after mounting the first and second specified electronic components, the contour markings provided around the first specified electronic components can be used to check whether the first specified electronic components have been omitted from mounting, and whether the first specified electronic components have been misaligned. By not providing a contour marking around the second specified electronic components, it is possible to prevent gaps from occurring between the specified board and the metal mask in the area where the second specified electronic components are mounted. This prevents solder paste from getting between the connections where no resist is applied, resulting in electrical contact between the two connections.

Feature E2. The gaming machine described in Feature E1, characterized in that on the specified board, outside the area in which the second specified electronic component is mounted, a component identification mark (identification silk 217, 218) is provided to indicate that the electronic component mounted in that area is the second specified electronic component.

According to feature E2, it is possible to visually confirm that the electronic component mounted on the specified board is the second specified electronic component based on the component identification marking. In addition, in a configuration having the configuration of feature E1 described above, in which the area on the specified board on which the second specified electronic component is mounted is not surrounded by an outline marking that defines the area, it is possible to confirm whether the second specified electronic component is mounted or not based on the component identification marking.

Feature E3: A first component identification mark (identification silk 214, 216) is provided outside the area where the first specified electronic component is mounted on the specified board, indicating that the electronic component mounted in that area is the first specified electronic component;
a second component identification mark (identification silk 217, 218) is provided outside an area on the specified board where the second specified electronic component is mounted, the second component identification mark indicating that the electronic component mounted in the area is the second specified electronic component;
A gaming machine described in feature E1 or E2, characterized in that the character size of the second part identification mark is the same as the character size of the first part identification mark.

According to feature E3, it is possible to visually confirm that the electronic component mounted on the specified board is the first specified electronic component based on the first component identification mark, and it is possible to visually confirm that the electronic component mounted on the specified board is the second specified electronic component based on the second component identification mark. Furthermore, in a configuration having the configuration of feature E1 above and in which no contour mark is provided around the area on the specified board in which the second specified electronic component is mounted to define the area, it is possible to confirm whether or not the second specified electronic component is mounted based on the component identification mark.

The configuration of feature E1 described above is provided, and the second specified electronic component is smaller than the first specified electronic component, but the character size of the second component identification mark is the same as the character size of the first component identification mark. This makes it easy to visually confirm that the electronic component mounted on the specified board is the second specified electronic component.

Feature E4: A predetermined control component (the LED driver 126 in the first embodiment, the second LED driver 326 in the fourth embodiment) is mounted on the predetermined board,
The predetermined substrate is
predetermined connection portions (second pads 171b, 382b) electrically connected to electrodes of the second predetermined electronic components (second electrode 85b of the bypass capacitor 85, second electrode 381b of the bypass capacitor 381);
A specific connection portion (a pad electrically connected to the power supply terminal 151, a pad electrically connected to the power supply terminal 348) electrically connected to a specific terminal (power supply terminals 151, 348) of the specific control component;
Equipped with
the predetermined connection portion and the specific connection portion are electrically connected to each other,
A gaming machine described in any one of features E1 to E3, characterized in that no control components (ICs) other than the specified control component are arranged between the specified terminal and the second specified electronic component.

Feature E4 can prevent other control components from malfunctioning due to the influence of noise components at a specific terminal of a specific control component.

Feature E5. The gaming machine described in Feature E4, characterized in that no electronic components other than the specified control component are disposed between the specified terminal and the second specified electronic component.

Feature E5 makes it possible to prevent other electronic components from malfunctioning due to the influence of noise components at a specific terminal of a specific control component.

Feature E6. A gaming machine according to any one of Features E1 to E5, characterized in that the second specified electronic component is a capacitor (bypass capacitors 85 and 97 in the first embodiment, bypass capacitor 291 in the second embodiment, and bypass capacitor 381 in the fourth embodiment) or a resistor (small chip resistors 87 and 101 in the first embodiment).

Feature E6 has the configuration of feature E1, and can prevent gaps from occurring between the specified substrate and the metal mask in the area where the capacitor or resistor is mounted. This can prevent solder paste from getting between the connection parts where the resist is not applied, causing electrical contact between the two connection parts.

Note that any one or more of the features A1 to A14, features B1 to B12, features C1 to C12, features D1 to D12, features E1 to E6, features F1 to F15, feature G1, and feature H1 may be applied to the features E1 to E6. This makes it possible to achieve a synergistic effect by combining the features.

<Feature Group F>
Feature F1. In a gaming machine having a predetermined board (first decorative board 56, second decorative board 57, light-emitting board 301) on which predetermined electronic components (bypass capacitors 85, 97 in the first embodiment, small chip resistors 87, 101, bypass capacitor 381 in the fourth embodiment) are mounted,
The specified electronic component has a dimension in a first direction (the longitudinal direction of the bypass capacitors 85, 97, 381, and the longitudinal direction of the small chip resistors 87, 101) perpendicular to the thickness direction of the specified electronic component that is larger than a dimension in a second direction (the lateral direction of the bypass capacitors 85, 97, 381, and the lateral direction of the small chip resistors 87, 101) perpendicular to the thickness direction of the specified electronic component,
The specified substrate has a dimension in a specified direction (first direction DR1, long axis directions LD, LDA) along a plate surface of the specified substrate that is larger than a dimension in a specific direction (second direction DR2, short axis directions SD, SDA) that is a direction along the plate surface of the specified substrate and perpendicular to the specified direction,
A gaming machine characterized in that the specified electronic component is mounted on the specified board such that the first direction of the specified electronic component is parallel to the specified direction of the specified board.

According to feature F1, since the specified electronic component is mounted on the specified board such that the first direction of the specified electronic component is parallel to the specified direction of the specified board, compared to a configuration in which the specified electronic component is mounted on the specified board such that the first direction of the specified electronic component is not parallel to the specified direction of the specified board, it is possible to reduce stress that may act on the connection point between the specified electronic component and the specified board when distortion occurs on the specified board, and to reduce stress that may act on the specified electronic component itself. This makes it possible to prevent damage to the connection point between the specified electronic component and the specified board. In addition, by reducing stress that may act on the specified electronic component itself when distortion occurs on the specified board, it is possible to prevent damage to the specified electronic component itself.

Feature F2. The specified substrate includes specific electronic components (LED chips 317, 324, chip resistors 338, 345) that are larger than the specified electronic components;
The specific electronic component is configured such that a dimension in a specific first direction (the longitudinal direction of the LED chips 317, 324 and the longitudinal direction of the chip resistors 338, 345) perpendicular to the thickness direction of the specific electronic component is larger than a dimension in a specific second direction (the transverse direction of the LED chips 317, 324 and the transverse direction of the chip resistors 338, 345) perpendicular to the thickness direction of the specific electronic component,
The gaming machine described in feature F1, wherein the specific electronic component is mounted on the specified substrate in a manner in which the specific first direction of the specific electronic component is not parallel to the specific direction of the specified substrate.

According to Feature F2, in a configuration in which a specific electronic component is mounted on a specific board in such a manner that the specific first direction of the specific electronic component is not parallel to the specific direction of the specific board, the configuration of Feature F1 is provided, and the specific electronic component is mounted on the specific board such that the first direction of the specific electronic component is parallel to the specific direction of the specific board. Therefore, in a configuration in which stress that may act on the connection point between the specific electronic component and the specific board and stress that may act on the specific electronic component itself when distortion occurs in the specific board are reduced, the degree of freedom in mounting the specific electronic component on the specific board can be increased.

Feature F3. The gaming machine described in Feature F1 or F2, characterized in that the outer shape of the specified board is neither rectangular nor approximately rectangular.

According to Feature F3, in a configuration in which the outer shape of the specified board is neither rectangular nor approximately rectangular, the configuration of Feature F1 is provided, and the specified electronic component is mounted on the specified board such that the first direction of the specified electronic component is parallel to the specified direction of the specified board. Therefore, compared to a configuration in which the first direction of the specified electronic component is perpendicular to the specified direction of the specified board, it is possible to reduce stress that may act on the connection point between the specified electronic component and the specified board when distortion occurs in the specified board, and also to reduce stress that may act on the specified electronic component itself.

Feature F4. The gaming machine according to any one of Features F1 to F3, characterized in that the specified electronic component is a capacitor (bypass capacitors 85 and 97 in the first embodiment, bypass capacitor 291 in the second embodiment, and bypass capacitor 381 in the fourth embodiment) or a resistor (small chip resistors 87 and 101 in the first embodiment).

Feature F4, compared to a configuration having the configuration of feature F1 above and in which the capacitor or resistor is mounted on the specified substrate in such a manner that the first direction of the capacitor or resistor is not parallel to the specified direction of the specified substrate, can reduce stress that may act on the connection point between the capacitor or resistor and the specified substrate when distortion occurs on the specified substrate, and can also reduce stress that may act on the capacitor or resistor itself. By reducing stress that may act on the connection point between the capacitor or resistor and the specified substrate when distortion occurs on the specified substrate, it is possible to prevent damage to the connection point between the capacitor or resistor and the specified substrate. In addition, by reducing stress that may act on the capacitor or resistor itself when distortion occurs on the specified substrate, it is possible to prevent damage to the capacitor or resistor itself.

Feature F5. The predetermined substrate is
predetermined connection portions (first pads 171a, 176a, 293a, 382a; second pads 171b, 176b, 293b, 382b) to which the electrodes (first electrodes 85a, 87a, 291a, 381a; second electrodes 85b, 87b, 291b, 381b) of the predetermined electronic components are electrically connected;
Predetermined wiring patterns (first wiring patterns 172a, 181a, 294a, 386a, second wiring patterns 172b, 294b, 386b, second wiring pattern 181b, third wiring pattern 172c, 294c, 386c, fourth wiring pattern 172d, 294d, 386d) drawn out from the predetermined connection portions,
Equipped with
A gaming machine described in any one of features F1 to F4, characterized in that the direction in which the specified wiring pattern is drawn out from the specified connection portion is perpendicular or substantially perpendicular to the first direction.

According to feature F5, the specified wiring pattern extends in a direction perpendicular or substantially perpendicular to the first direction. Therefore, in the event that distortion occurs in the specified board, it is possible to reduce the maximum value of stress that can act on the connection point between the specified electronic component and the specified board, and to reduce the maximum value of stress that can act on the specified electronic component itself. This makes it possible to prevent damage to the connection point between the specified electronic component and the specified board, and to prevent damage to the specified electronic component itself.

Feature F6. The predetermined connection portion and the predetermined wiring pattern are provided on a predetermined mounting surface (the first mounting surface 84 of the first decorative substrate 56), which is a plate surface on one side of the predetermined substrate;
The gaming machine described in feature F5, wherein the specified wiring pattern is a wiring pattern that extends in a straight line on the specified mounting surface.

According to feature F6, the specified wiring pattern extends linearly on the specified mounting surface. Therefore, in the event that distortion occurs in the specified board, it is possible to reduce the maximum value of stress that can act on the connection point between the specified electronic component and the specified board, and to reduce the maximum value of stress that can act on the specified electronic component itself. This makes it possible to prevent damage to the connection point between the specified electronic component and the specified board, and to prevent damage to the specified electronic component itself.

Feature F7: The predetermined substrate includes a non-penetrating predetermined via hole (via hole 174, 175) extending from the predetermined mounting surface in a thickness direction of the predetermined substrate, or a predetermined through hole (first through hole 383, second through hole 384) penetrating the predetermined substrate in a thickness direction,
The gaming machine described in feature F6, wherein the specified wiring pattern is a linear wiring pattern that electrically connects the specified connection portion and the specified via hole or the specified through hole on the specified mounting surface.

According to feature F7, by providing a specified via hole or a specified through hole in the specified substrate and making the specified wiring pattern a linear wiring pattern, when distortion occurs in the specified substrate, it is possible to reduce the maximum value of the stress that can act on the connection point between the specified electronic component and the specified substrate, and also to reduce the maximum value of the stress that can act on the specified electronic component itself.

Feature F8. The predetermined electronic component includes a first predetermined electrode (first electrode 85a, 87a, 291a, 381a) and a second predetermined electrode (second electrode 85b, 87b, 291b, 381b),
The predetermined substrate is
a first predetermined connection portion (first pad 171a, 176a, 293a, 382a) to which the first predetermined electrode is electrically connected;
a first predetermined wiring pattern (first wiring patterns 172a, 181a, 294a, 386a, second wiring patterns 172b, 294b, 386b) electrically connected to the first predetermined connection portion;
second predetermined connection portions (second pads 171b, 176b, 293b, 382b) to which the second predetermined electrodes are electrically connected;
second predetermined wiring patterns (second wiring pattern 181b, third wiring patterns 172c, 294c, 386c, fourth wiring patterns 172d, 294d, 386d) electrically connected to the second predetermined connection portions;
Equipped with
A gaming machine described in any one of features F1 to F7, characterized in that the direction in which the first predetermined wiring pattern is drawn out from the first predetermined connection portion and the direction in which the second predetermined wiring pattern is drawn out from the second predetermined connection portion are perpendicular or approximately perpendicular to the first direction of the predetermined electronic component.

According to feature F8, the direction of drawing from the first predetermined connection portion of the first predetermined wiring pattern and the direction of drawing from the second predetermined connection portion of the second predetermined wiring pattern are perpendicular or substantially perpendicular to the first direction. Therefore, when distortion occurs in the specified board, the maximum value of stress that can act on the connection point between the specified electronic component and the specified board can be reduced, and the maximum value of stress that can act on the specified electronic component itself can be reduced. This makes it possible to prevent damage to the connection point between the specified electronic component and the specified board, and to prevent damage to the specified electronic component itself.

Feature F9. The gaming machine described in Feature F8, characterized in that the direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists when viewed from the center of the first predetermined connection part is the same direction as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection part.

According to feature F9, it is possible to align the temperature distribution in the first and second predetermined connection parts during the initial heating stage of the reflow process, and to align the manner in which the solder paste applied to the first and second predetermined connection parts melts. This prevents the specified electronic component from rotating around the normal direction of the specified substrate as the axis of rotation, and prevents the specified electronic component from standing up on one connection part (the first specified connection part or the second specified connection part) with only one electrode (the first specified electrode or the second specified electrode), which is called a chip standing. Therefore, it is possible to ensure the electrical connection area between the first specified electrode and the first specified connection part, and to ensure the electrical connection area between the second specified electrode and the second specified connection part.

Feature F10. The gaming machine described in Feature F8 or F9, wherein the predetermined electronic component has a pair of electrodes, the first predetermined electrode and the second predetermined electrode.

According to feature F10, the configuration of feature F8 is provided, and the direction in which the lead-out position from the first predetermined connection part of the first predetermined wiring pattern exists as viewed from the center of the first predetermined connection part is the same as the direction in which the lead-out position from the second predetermined connection part of the second predetermined wiring pattern exists as viewed from the center of the second predetermined connection part, so that the temperature distribution in the pair of first predetermined connection parts and second predetermined connection parts in the initial heating stage of the reflow process can be made uniform, and the manner in which the solder paste applied on the pair of first predetermined connection parts and second predetermined connection parts melts can be made uniform. This makes it possible to prevent the specified electronic component from rotating around the normal direction of the specified board as the rotation axis, and to prevent the occurrence of so-called chip standing, in which the specified electronic component stands up on one connection part (first specified connection part or second specified connection part) with only one electrode (first specified electrode or second specified electrode). Therefore, it is possible to ensure the electrical connection area between the first specified electrode and the first specified connection part, and to ensure the electrical connection area between the second specified electrode and the second specified connection part.

Feature F11: The first predetermined connection portion is electrically connected to a first metal region (GND plane layer 93) having an area larger than that of the first predetermined connection portion via the first predetermined wiring pattern,
A gaming machine described in any one of features F8 to F10, characterized in that the second specified connection portion is electrically connected to a second metal region (power supply plane layer 94) having a larger area than the second specified connection portion via the second specified wiring pattern.

According to feature F11, in a specified connection part (first specified connection part or second specified connection part), the side where the pull-out part of the specified wiring pattern (first specified wiring pattern or second specified wiring pattern) that is electrically connected to a large-area metal region (first metal region or second metal region) is located is prone to a delayed temperature rise in the initial heating stage of the reflow process, but the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the first specified connection part is the same direction as the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the second specified connection part. This makes it possible to align the temperature distribution in the first specified connection part and the second specified connection part in the initial heating stage.

Feature F12: The wiring pattern drawn out from the first predetermined connection portion is only the first predetermined wiring pattern,
A gaming machine described in any one of features F8 to F11, characterized in that the wiring pattern pulled out from the second predetermined connection portion is only the second predetermined wiring pattern.

According to feature F12, in a configuration having the configuration of feature F8, in which the direction of drawing of the first predetermined wiring pattern from the first predetermined connection portion and the direction of drawing of the second predetermined wiring pattern from the second predetermined connection portion are perpendicular or substantially perpendicular to the first direction, the wiring pattern drawn from the first predetermined connection portion is only the first predetermined wiring pattern, and the wiring pattern drawn from the second predetermined connection portion is only the second predetermined wiring pattern. Therefore, when distortion occurs in the specified board, the maximum value of the stress that can act on the connection point between the specified electronic component and the specified board can be reduced, and the maximum value of the stress that can act on the specified electronic component itself can be reduced.

Feature F13. The predetermined substrate is
a third predetermined wiring pattern (second wiring patterns 172b, 294b, 386b) drawn out from the first predetermined connection portion;
a fourth predetermined wiring pattern (fourth wiring patterns 172d, 294d, 386d) drawn out from the second predetermined connection portion;
Equipped with
A gaming machine described in any one of features F8 to F11, characterized in that the direction in which the third predetermined wiring pattern is drawn out from the first predetermined connection portion and the direction in which the fourth predetermined wiring pattern is drawn out from the second predetermined connection portion are perpendicular or substantially perpendicular to the first direction of the predetermined electronic component.

According to feature F13, the first, second, third, and fourth predetermined wiring patterns extend in a direction perpendicular or substantially perpendicular to the first direction. Therefore, when distortion occurs in the specified board, the maximum value of stress that can act on the connection points between the specified electronic component and the specified board can be reduced, and the maximum value of stress that can act on the specified electronic component itself can be reduced. This prevents damage to the connection points between the specified electronic component and the specified board, and prevents damage to the specified electronic component itself.

Feature F14: A direction in which a side of the first predetermined connection part, from which the first predetermined wiring pattern is drawn, exists when viewed from a center of the first predetermined connection part is the same as a direction in which a side of the second predetermined connection part, from which the second predetermined wiring pattern is drawn, exists when viewed from a center of the second predetermined connection part;
The gaming machine described in feature F13, characterized in that the direction in which the side of the first specified connection part from which the third specified wiring pattern is pulled out exists when viewed from the center of the first specified connection part is the same direction as the direction in which the side of the second specified connection part from which the fourth specified wiring pattern is pulled out exists when viewed from the center of the second specified connection part.

Feature F14 makes it possible to align the temperature distribution within the pair of first and second predetermined connection parts during the initial heating stage of the reflow process, and to align the manner in which the solder paste applied to these first and second predetermined connection parts melts. This makes it possible to prevent the specified electronic component from rotating around the axis of rotation that is the normal direction of the specified substrate, and to prevent the specified electronic component from standing up on one of the specified connection parts with only one specified electrode, a phenomenon known as chip standing. This makes it possible to ensure the electrical connection area between the specified electrode and the specified connection part.

Feature F15: The first predetermined connection portion is electrically connected to a first metal region (GND plane layer 93) having an area larger than that of the first predetermined connection portion via the predetermined wiring pattern,
the third predetermined wiring pattern is not electrically connected to a metal region having an area larger than that of the first predetermined connection portion,
the second predetermined connection portion is electrically connected to a second metal region (power supply plane layer 94) having an area larger than that of the second predetermined connection portion via the predetermined wiring pattern;
The gaming machine described in feature F13 or F14, characterized in that the fourth predetermined wiring pattern is not electrically connected to a metal area having a larger area than the second predetermined connection portion.

According to feature F15, the side where the pull-out part of the specified wiring pattern (first specified wiring pattern or second specified wiring pattern) electrically connected to the large metal area (first metal area or second metal area) exists in the specified connection part (first specified connection part or second specified connection part) is likely to have a delayed temperature rise in the initial heating stage of the reflow process, but the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the first specified connection part is the same direction as the direction in which the side where the temperature rise is likely to be delayed in the initial heating stage exists as viewed from the center of the second specified connection part. Also, the direction in which the side where the third specified wiring pattern that is not electrically connected to the large metal area from the first specified connection part exists as viewed from the center of the second specified connection part is the same direction as the direction in which the side where the fourth specified wiring pattern that is not electrically connected to the large metal area from the second specified connection part exists as viewed from the center of the second specified connection part. Therefore, the temperature distribution in the first specified connection part and the second specified connection part in the initial heating stage can be aligned.

Note that any one or more of the features A1 to A14, features B1 to B12, features C1 to C12, features D1 to D12, features E1 to E6, features F1 to F15, feature G1, and feature H1 may be applied to the features F1 to F15. This makes it possible to achieve a synergistic effect by combining the features.

<Feature Group G>
Feature G1. In a gaming machine having a predetermined board (first decorative board 56, light-emitting board 301) on which a predetermined control part (LED driver 126 in the first embodiment, second LED driver 326 in the fourth embodiment) and a predetermined capacitor (bypass capacitor 85 in the first embodiment, bypass capacitor 381 in the fourth embodiment) are mounted,
The predetermined substrate includes a power supply wiring pattern (third wiring pattern 172c, 386c, fourth wiring pattern 172d, 386d) that supplies drive power for the predetermined control component to a predetermined terminal (power terminal 151, 348) of the predetermined control component,
The predetermined capacitor is electrically connected to the power supply wiring pattern and the ground (GND plane layer 93),
A gaming machine characterized in that no control components (ICs) other than the specified control component are disposed between the specified terminal and the specified capacitor.

Feature G1. By having a specified capacitor absorb the noise components of the drive power supply supplied to a specified terminal of a specified control component, the specified control component can be prevented from malfunctioning due to the influence of the noise components. In addition, by having a specified capacitor absorb the noise components generated by the specified control component, it is possible to prevent other electronic components from malfunctioning due to the influence of the noise components.

Note that one or more of the features A1 to A14, features B1 to B12, features C1 to C12, features D1 to D12, features E1 to E6, features F1 to F15, feature G1, and feature H1 may be applied to the feature G1. This makes it possible to achieve a synergistic effect by combining the features.

<Feature H Group>
Feature H1. In a gaming machine equipped with a predetermined board (first decorative board 56),
A first predetermined electronic component (the LED driver 126 and the LED chip 142 in the first embodiment) and a second predetermined electronic component (the bypass capacitor 85 and the small chip resistor 87 in the first embodiment) smaller than the first predetermined electronic component are mounted on the predetermined substrate,
a contour mark (contour silk 213, 215) for dividing an area on the predetermined board on which the first predetermined electronic component is mounted is provided around the area;
A gaming machine characterized in that there is no outline marking to define the area around the area on the specified board on which the second specified electronic component is mounted.

According to feature H1, in visual inspection after mounting the first and second specified electronic components, the contour markings provided around the first specified electronic components can be used to check whether the first specified electronic components have been omitted from mounting, and whether the first specified electronic components have been misaligned. In a configuration in which the second specified electronic components are smaller than the first specified electronic components, no contour markings are provided around the second specified electronic components, thereby preventing a worker from erroneously determining that the specified electronic components have been inserted based on the contour markings alone, when in fact the specified electronic components have been omitted from mounting.

Note that one or more of the features A1 to A14, features B1 to B12, features C1 to C12, features D1 to D12, features E1 to E6, features F1 to F15, features G1, and features H1 may be applied to the feature H1. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the above-mentioned feature group A, feature group B, feature group C, feature group D, feature group E, feature group F, feature group G, and feature group H can solve the following problems.

Pachinko machines and slot machines are known as types of gaming machines. In these gaming machines, a lottery is held when a certain lottery condition is met, and a bonus is awarded to the player depending on the result of the lottery. It is also common for the machines to be configured to provide effects that allow the player to predict or recognize the result of the lottery. These gaming machines are equipped with a board on which electronic components for progressing the game and for executing effects are mounted.

Specific examples of pachinko machines include a lottery held when a gaming ball enters a ball entry section in the play area, a changing display of pictures on the display screen of the display device, and if the lottery results in a winning result, a combination of specific pictures is displayed in a final stopped state on the display screen, and the machine transitions to a special game state that is advantageous to the player. When the machine transitions to the special game state, for example, a ball entry device or the like in the play area begins to open and close, and game balls are paid out based on the ball entering the ball entry device.

Here, in gaming machines such as those exemplified above, electronic components need to be suitably mounted on the circuit board, and there is still room for improvement in this regard.

The following shows the basic configuration of a gaming machine to which each of the above features can be applied or to which each feature can be applied.

Pachinko game machine: A game machine that has an operating means operated by the player, a game ball launching means that launches game balls based on the operation of the operating means, a ball passage that guides the launched game balls to a specified game area, and various game components arranged within the game area, and that awards a special prize to the player when the game ball passes through a specified passage section of each of the game components.

Slot machines and other reel-type gaming machines: A gaming machine equipped with a picture display device that variably displays multiple pictures, in which the variable display of the multiple pictures is started by operating a start operation means, the variable display of the multiple pictures is stopped by operating a stop operation means or after a predetermined time has passed, and a bonus is given to the player according to the picture after the stop.

10... Pachinko machine, 56... First decorative board, 56d to 56g... Fixing through holes, 57... Second decorative board, 84... First mounting surface, 85... Bypass capacitor, 85a... First electrode, 85b... Second electrode, 87... Small chip resistor, 87a... First electrode, 87b... Second electrode, 93... GND plane layer, 94... Power plane layer, 95... Second mounting surface, 97... Bypass capacitor, 101... Small chip resistor, 111, 112... Connector, 126... LED driver, 142... LED chip, 142a... First electrode, 142b... Second electrode, 151... Power terminal, 152, 153... Terminal, 154 ...GND terminal, 155 to 162...terminal, 171a...first pad, 171b...second pad, 172a...first wiring pattern, 172b...second wiring pattern, 172c...third wiring pattern, 172d...fourth wiring pattern, 174, 175...via hole, 176a...first pad, 176b...second pad, 178a...first pad, 178b...second pad, 181a...first wiring pattern, 181b...second wiring pattern, 203, 204...connector back side corresponding area, 211a to 211d...through hole surrounding area, 213...outline silk, 214...identification silk, 215...outline silk, 21 6 to 218...Identification silk, 291...Bypass capacitor, 291a...First electrode, 291b...Second electrode, 293a...First pad, 293b...Second pad, 294a...First wiring pattern, 294b...Second wiring pattern, 294c...Third wiring pattern, 294d...Fourth wiring pattern, 301...Light emitting substrate, 302...First light emitting surface, 303...Second light emitting surface, 310...LED chip, 315 to 325...LED chip, 326...Second LED driver, 327...Connector, 328...Bypass capacitor, 331 to 335...Small chip resistor, 336 to 346...Chip resistor, 348 ...power supply terminal, 349...GND terminal, 352...bypass capacitor, 353, 354...area corresponding to the back side of the driver, 355, 361-371...area corresponding to the back side of the LED, 381...bypass capacitor, 381a...first electrode, 381b...second electrode, 382a...first pad, 382b...second pad, 383...first through hole, 384...second through hole, 386a...first wiring pattern, 386b...second wiring pattern, 386c...third wiring pattern, 386d...fourth wiring pattern, DR1...first direction, DR2...second direction, LD, LDA...long axis direction, SD, SDA...short axis direction.

Claims (1)

In a gaming machine having a predetermined substrate on which a predetermined electronic component is surface- mounted using a reflow process ,
the predetermined electronic component includes a pair of electrodes, that is, a first predetermined electrode and a second predetermined electrode,
The predetermined substrate is
a first predetermined connection portion to which the first predetermined electrode is electrically connected;
a first predetermined wiring pattern extending from the first predetermined connection portion;
a second predetermined connection portion to which the second predetermined electrode is electrically connected;
a second predetermined wiring pattern extending from the second predetermined connection portion;
Equipped with
a direction in which a side of the first predetermined connection portion, from which the first predetermined wiring pattern is drawn, exists when viewed from a center of the first predetermined connection portion is the same as a direction in which a side of the second predetermined connection portion, from which the second predetermined wiring pattern is drawn, exists when viewed from a center of the second predetermined connection portion ;
the first predetermined connection portion is electrically connected to a first metal region having an area larger than that of the first predetermined connection portion via the first predetermined wiring pattern;
A gaming machine characterized in that the second predetermined connection portion is electrically connected to a second metal region having a larger area than the second predetermined connection portion via the second predetermined wiring pattern .

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